Implement NGX's Vulkan API over the existing CUDA backend. Compute shaders
pack the game's sampled images into buffers shared with CUDA (device-local
memory exported through the Wine bridge), and a device event in the game's
command buffer holds its queue until the result is written back, keeping
frame age at zero. DLSS reads inputs through pitch-linear textures and its
native output kernel writes the shared buffer directly; input and
completion waits are adaptive.
Make it work across engines: shared buffers are concurrent over every
compute-capable queue family (Indiana Jones records DLSS on async compute),
depth kept in an R32F colour image is accepted under a depth aspect, and the
extension-requirement query allows a null list. Spare buffer sets are
imported on the first frame and never while a frame is pending, since an
import can block on GPU work that is waiting for us; host staging covers any
shortfall.
Fix two exit hazards. A game quitting without NGX shutdown left the GPU
waiting on an event that only a killed thread would set, resetting the ring
10 s later: the bridge now runs a shim hook before teardown and skips all
CUDA destroy/sync calls once Wine is shutting the process down. The shim's
own entry point skips CRT static destructors at process termination, where
locks held by killed threads made the exit spin forever.
Add a Vulkan DLSS harness (dynamic, recreate, discard, invalid, exit,
compute-queue and in-flight modes), staging/depth probes, ABI/config tests,
and an OptiScaler settings overlay for Vulkan games.
Shim
- Adaptive output-event wait: sleep to ~120 us before the predicted
completion (smoothed per wait site), spin near it, back off when late.
D4R_SHIM_OUTPUT_POLL_US restores a fixed interval.
- Defer the input-marker wait into the worker thread with VRAM interop
(D4R_SHIM_DEFER_MARKER, default on), taking the host setup off the
critical path.
MicroCUDA
- Experimental ZLUDA-free backend in wine_nvcuda_bridge, plus
tools/microcuda and scripts/build_microcuda.sh. Serves accuracy, fast
and native kernels; unregistered modules fall back to the reference
path. Unclassified writes invalidate prepared weights.
M kernels
- SWIN_PREP_IDENTITY_AT: key weight prep by allocation identity
(MicroCUDA); enc3 tube uses it with 8 slots. ZLUDA ignores it.
- dec2 (gfx1101): SWIN_PACKED_RESIDUAL, byte-identical, ~1.6% faster.
- Opt-in gfx12 hardware fp8 conversion (SWIN_FP8_HWCVT), unverified
on hardware.
Native K translators
- ctile: handle variants that re-materialize the parameter base (mvlo).
- rewrite_output: check live-in registers, not just outputs.
- build.sh: native input covers all 8 flag variants, output the 4 HDR
"max" variants; depth-tile skip stays mvhi-only.
Tools
- dump_runner and bench_dlss_kernel harness additions.
Preset K, byte-identical to the previous output in all captured buffers
and the harness image, measured on an RX 7700 XT:
- LDS row padding so WMMA operand loads hit distinct banks
- WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for
enc0/dec0/dec3, more waves per window in enc4/dec4/dec5
- cheaper operand plumbing in common/wmma_layout.h (packed f16
conversions, no dynamic vector indexing), raw buffer weight loads,
accumulator-init vectors prepared once
- enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split
- dec5 as four dependent phase kernels
- Reprepare enc3 weights each launch to avoid stale caches after feature recreation
- Require per-slot input markers before evaluating recorded frames
- Advance split-frame timelines only through completed frames
- Add cancellation and readiness tests plus recreation consistency checks
- Update architecture and native kernel documentation
ref #8
- Explicitly route OptiScaler to d4r\nvngx.dll in release packages.
- Extract INI generation into a helper that preserves line endings
and rejects missing or duplicate settings.
- Check NGX routing separately from file presence and return failure
when the installation is incomplete or misconfigured.
- Add an optional OptiScaler patch for external DLSS backends while
preserving AMD identity for FSR4, with matching launch guidance.
- Align portable and launcher marker polling defaults at 200 us.
- Log when d4r's model override replaces game or OptiScaler presets.
- Add configuration, package, routing and coexistence regression tests.
- Update installation documentation, add FSR/DLSS comparison videos
and ignore local .tools artifacts.
Refs: #7, #14
- Add default-off PreferAccuracy for all native kernel families,
including RDNA4 FP8 variants.
- Restore intermediate FP8 quantization, per-MMA FP16 rounding,
denormal handling and NGX synchronization in accuracy mode.
- Select separately marked accuracy kernels and use a separate JIT
cache; reject mixed sets and never silently substitute fast kernels.
- Add a pinned GLIBC 2.41 build environment for ZLUDA/LLVM, the DLLs
and both kernel sets, with ABI checks and toolchain provenance.
- Support parallel target builds and pre-extracted PTX; correct
ROCm header paths and Clang-CL input handling.
- Bump to 0.1.3 and update release notes, documentation and tests.
Validation: 11 tests passed; all 912 kernels built; E/K/M GPU harness
runs completed with accuracy off/on. Packaged libraries loaded under
GLIBC 2.41 and require no GLIBC version newer than 2.38.
RTX image-quality parity remains unverified.
Fixes#6
Refs #6
- Fix Cyberpunk 2077 preset-K black artifacts by preserving FP16/FP64
denormal requirements while limiting denormal suppression to FP32.
- Fix stale direct-output redirects after array destruction, preventing
reused handles from inheriting an earlier feature's output buffer.
- Log rejected resource formats and dimensions, including failures after
startup, with rate limiting for repeated errors.
- Add opt-in blocking output synchronization with a dedicated bridge
export and fallback to context synchronization.
- Report output-wait CPU and wall time, and defer GPU timing queries
until asynchronous evaluation has completed. The CPU-overhead
mitigation for #7 still needs reporter confirmation.
- Reject release libraries requiring GLIBC newer than the configured
baseline, defaulting to 2.41, and document compatible builds.
Validation: shim and bridge builds pass; targeted redirect-lifetime and
format-logging checks pass.
Fixes#5Fixes#8
Refs #7
RDNA4 (experimental; untested on RDNA4 hardware)
- kernels/common/wmma_layout.h picks the WMMA operand/accumulator layout
per target; K (pwin_*) and M (swin_*) index through it, so the same
sources build for gfx11 and gfx12. D4R_WMMA_LAYOUT=12 on gfx11 is a test
shim that runs the gfx12 indexing on gfx11 WMMA.
- M can use native e4m3 FP8 WMMA on gfx12 (D4R_NATIVE_FP8=1). Texture
tails (enc0_tail, dec0_head) get gfx12 f16 and FP8 paths that match
ZLUDA's gfx12 lowering.
- ZLUDA patch 0007: gfx12 WMMA helpers, optional native FP8 MMA
(D4R_ZLUDA_WMMA_FP8_NATIVE), a layout override for testing, and an
architecture argument for d4r_emit. Texture kernels are now compiled
offline per target through d4r_emit (D4R_ZLUDA_EMIT) instead of on the
local GPU.
- New d4r.ini option [Kernels] NativeFp8 (default on), wired through the
shim and d4r_config.py. On gfx12 the bridge serves kernels/<arch>-fp8
when it is on.
- The bridge picks the KFD GPU with the most SIMDs (so an iGPU is not
chosen over a discrete GPU); D4R_GPU_ARCH overrides it.
- kernels/build.sh and package_release.sh build gfx1100-gfx1103 and
gfx1200/gfx1201 (plus -fp8 variants), and D4R_BUNDLE_TEX takes
per-target folders.
Performance (RDNA3; harness byte-identical unless noted)
- ZLUDA patch 0006: m16n8k8 f16 MMAs on WMMA (E; not bit-exact, 52-55 dB
per layer, D4R_ZLUDA_WMMA_K8=0 disables it), per-key weight-image slots
for native prep kernels (d4r_prep_key_at, d4r_prep_key_slots), and
wave64 builds of MMA-free kernels (D4R_ZLUDA_WAVE64).
- M: packed FP8 encoding, conflict-free patch-merge reads, scalar weight
loads in enc1, and weight prep once per weight set for the six enc3
tube blocks.
- K: CU mode for the six non-wide pwin layers.
- Texture kernels: every DLSS flag variant is built natively (24 K output,
8 M post, 4 M downsample, 4 M enc0), not only Townfall's; post and K
output run as wave64.
- M direct output: rrlite_downsample_kernel writes the shim's output
buffer; the shim's default direct-output presets are now 11,13.
Tools
- dump_runner takes the prep grid from d4r_prep_blocks and refuses
texture/surface dumps.
- New pwin_check.py, swin_check.py, model_enc3.py and tail_check.hip.
Docs: README GPU table and RDNA4 notes, building (patches 0002-0007,
d4r_emit), native-kernels (RDNA4 section), performance (new numbers),
packaging README. Version 0.1.2.
- Shim: reuse VRAM interop buffers across features instead of freeing them;
ROCm 7.2.x's hipExternalMemoryGetMappedBuffer retains its view twice, so
freed buffers never released their memory (~130 MB per quality change)
- Bridge: close the exported fd after hipImportExternalMemory
- Shim: accept R16G16B16A16_TYPELESS motion vectors and convert 4-channel
motion vectors to RG16F on the GPU, keeping VRAM interop (Dying Light:
The Beast rendered black)
- Harness: D4R_HARNESS_RECREATE=N quality-change cycles,
D4R_HARNESS_MV_RGBA16=1 motion vector format
- Supported games: TLOU, Control, Cyberpunk 2077, Rift Apart, HZD Remastered,
Subnautica 2, Alan Wake 2, Silent Hill 2, Dying Light: The Beast; general notes
- README: GPU support section (native kernels only for gfx1101); ignore videos/
ayo