ayo
ac4ee6c225
Add a native D3D12 FSR Ray Regeneration route for gfx1200/gfx1201, using the game's device and queue with embedded HLSL guide preparation and output composition. Preserve the vkd3d compatibility route for RDNA3 and expose explicit route overrides and diagnostics. Improve Windows runtime compatibility: - Retry rejected application-ID initialization with a project identity. - Defer expensive RR backend creation until feature creation. - Recover from transient submission failures without disabling later frames. - Add shared-buffer export fallbacks through explicit heaps and a private device on the same adapter. - Safely evict old RR descriptor sets when input views change. - Treat requested RR presets as hints when a configured model is available. - Expand SR/RR input formats and handle diffuse/specular hit distances, packed normals, depth-stencil resources, and unused FSR guides. Reduce SR overhead by batching output downloads and format conversion under one completion wait. Optimize strict M enc2/tube attention with bounded FP32 accumulation and the original FP64 fallback for ambiguous rounding cases. Extend RDNA4 tooling with gfx1200/gfx1201 native FP8 RR model builds, capability checks, architecture-aware deployment, and experimental K/M kernel paths. Require matching model and runtime arithmetic families. Add optional embedded FSR shader optimizations keyed by shader hash and exact original SPIR-V contents. Preserve reflected metadata and record optimizer provenance, artifact hashes, and cache identity. Simplify Windows installation with automatic backend dependency downloads, download progress and ETA, backed-up absolute OptiScaler library paths, and recovery from interrupted RR model builds. Add build-kernels.bat and a kernels-only build matrix for all eleven registered RDNA targets, with code-object target validation and SHA256 manifests. Expand conversion probes, numerical stress tests, temporal benchmark tooling, installer/deployment tests, and setup documentation. Document synthetic regression and timing results, experimental build options, and remaining RDNA4 hardware validation requirements.
85 lines
5.1 KiB
Markdown
85 lines
5.1 KiB
Markdown
# RDNA 4 optimization candidates (2026-10-17)
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These changes expose target-specific paths for gfx1200 and gfx1201. The available
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GPU is an RX 7700 XT (gfx1101), so **no RDNA 4 speedup or output equivalence has
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been measured**. Compilation and instruction checks do not establish either.
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Existing packages and games were not updated.
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## Paths
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- **K:** `build-native-k-experiment.ps1 -F16Wmma` exposes the existing gfx12 native
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FP16-accumulator WMMA implementation. It requires the strict K baseline, rejects
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gfx11 and incompatible packed-accumulator storage, and records the selection in
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candidate metadata. It remains experimental pending layer and temporal-frame
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equality checks. The default kernel arithmetic is unchanged.
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- **M:** `build-native-m-fp8.ps1 -GpuArch gfx1200|gfx1201` builds the existing native
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FP8 path for either target, including optional hardware packing and token lanes.
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The ISA gate requires FP8 WMMA instructions. The separate strict FP16 candidate
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builder now supports both gfx12 targets with native lane exchange; gfx11-only
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LDS/DS flags are excluded. Neither candidate is selected automatically.
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- **DLSS RR D/E:** the Windows model builder now accepts `--gpu-arch gfx1200|gfx1201`.
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It uses the existing native FP8 cooperative-matrix shaders, omits gfx11's widened
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weight copies and records `arithmetic gfx12`. Every native network shader must
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declare Float8EXT, Float8CooperativeMatrixEXT and CooperativeMatrixKHR.
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The Windows Vulkan bridge enables and requires the float8 extension/features on
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gfx12. Model deployment requires matching runtime `gpu-target.json`; the bridge
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rejects a model from the other arithmetic family. Exact conversion decorations
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remain enabled; relaxed arithmetic is not introduced. The NGX regression helper
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accepts the same `--gpu-arch` to select its format module and native directory.
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- **FSR RR:** gfx12 no longer receives `wmma_rdna3_workaround` by default. The local
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dxil-spirv implementation applies gfx11-specific column mapping and FP16 RTZ
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under that setting. gfx11 retains it. Explicit process overrides survive; lookup
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uses the Windows environment rather than the C runtime's stale snapshot.
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This removes an inappropriate target setting; native FSR execution and its
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performance still depend on the target Vulkan driver's capabilities.
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A subsequent change now selects direct D3D12 on gfx12 by default, bypassing
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this compatibility route entirely. See [native route status](windows-fsr-rr.md).
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AMD documents RDNA 4's native FP8 matrix support in its
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[matrix-core guide](https://gpuopen.com/learn/using_matrix_core_amd_rdna4/).
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That hardware capability does not establish Windows Vulkan driver support.
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## Build examples
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Use a fresh ignored output directory for each candidate. Replace DLL paths with
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the locally supplied pinned binaries. Do not install candidates before validating
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their outputs and paired timings on the target GPU.
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```powershell
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scripts/windows/build-native-k-experiment.ps1 -GpuArch gfx1201 -Layer enc1 -F16Wmma -OutputDirectory build/my-k-gfx1201
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scripts/windows/build-native-m-fp8.ps1 -GpuArch gfx1201 -DlssDll PATH/nvngx_dlss.dll -HardwarePacking -TokenLanes -OutputDirectory build/my-m-gfx1201
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python tools/windows/build_rr_model.py --gpu-arch gfx1201 --preset D --dll PATH/nvngx_dlssd.dll --output build/my-rr-d-gfx1201
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```
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Use gfx1200 consistently for that target. Build the shim/probe with the matching
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`D4R_GPU_ARCH`. Deployment can stage a verified private model with
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`deploy_rr_model.py --model MODEL --runtime RUNTIME`; selection still requires
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`--enable` or an explicit model path. No relaxed model is built by this recipe.
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## Checks performed
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- K enc1 FP16 WMMA candidates compile for both targets. All eleven baseline K and
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five baseline M objects additionally compile for gfx1201.
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- All five M native FP8 modules compile for both targets, with native WMMA and
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hardware packing instructions verified by the builder. Strict FP16 M candidate
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sets also compile for both targets.
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- Complete D/gfx1201 and E/gfx1200 RR models compile. All eleven native network
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stages per model pass the SPIR-V native FP8 capability gate.
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- The shim and standalone RR runner build for gfx1201; the gfx1101 shim, probe and
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runner also rebuild successfully.
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- 13 RR Python tests and 16 existing CTest checks pass on gfx1101. Some legacy
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CTest names contain gfx1201/gfx12; these runs used the configured gfx1101 target.
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- Native DLSS RR passes six synthetic camera/reset frames against the existing
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reference, byte-for-byte. Evidence: `build/rdna4-opt-rr-rdna3-regression-v3/`.
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- FSR RR passes 24 moving-camera synthetic frames with exact same-frame output
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widening. Tail RMSE is approximately 0.1066 versus noisy input 0.4862. The log
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confirms gfx1101 still selects `wmma_rdna3_workaround`. Evidence:
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`build/rdna4-opt-fsr-rdna3-regression-v3/`.
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The additional NGX `--contracts --without-sr` run fails at
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`RR advertised on unsupported WARP adapter`, before inference. That capability
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contract is unresolved; the successful six-frame run does not clear it.
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Candidate artifacts remain under `build/rdna4-opt-*`. RDNA 4 layer/frame equality,
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real-game quality, GPU timings and paired performance comparisons remain open.
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