itchyfeetleech
49439afb81
ACO sizes a shader's registers to the waves its shared memory leaves room for, so stages that declare less shared memory also get fewer registers and more waves. Three stages hold buffers whose lifetimes do not overlap: - Encoder 0 at D4R_RR_RELAXED=3: with the one-wave block the gather no longer needs a pass of its own. The generated shader runs gather, block and tail in one 32-thread group and hands the features over in shared memory that the block's XT and KVS reuse (rr2_w.comp RR2_XF_SHARED). No gather pass, no record in the arena (36 MB of it lay past the arena at 720p). D4R_RR2_SPLIT=1 keeps the pass. - enc1: the merge input (GT) is in registers before XT or KVS is written: 17 -> 9 KiB, 240 -> 144 vector registers, 6 -> 10 waves per SIMD. - dec0_1: r and the MLP sum for the tail are written after the block is done with XT and KVS, as binary16 pairs: 14 -> 8 KiB, 192 -> 120 registers, 8 -> 12 waves per SIMD. Also D4R_ENGINE_RR_STAGE_STAMPS=1: a timestamp after every network stage and output group, printed per stage by d4r-rr. Every image of six temporal frames byte-identical to the previous model (1280x720 -> 1440p, 1114x626 -> 1080p, 853x480 -> 1440p, robustness2). RX 9070 XT, RADV, 720p -> 1440p: frame 4.09 -> 4.00 ms (enc0 798 -> 772 us, enc1 286 -> 266, dec0_1 660 -> 623). Other stages' SPIR-V is unchanged. Signed-off-by: itchyfeetleech <[email protected]>
322 lines
19 KiB
Python
322 lines
19 KiB
Python
#!/usr/bin/env python3
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"""Generate preset F's encoder 0 shader: ptx2rr.py's translation of NVIDIA's per-pixel feature gather and of its guide
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tail, around the native block (engine/rr/rr2_m.comp, KIND 4).
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usage: gen_rr2_enc0.py ENC0.ptx ENC0.generated.comp OUT.comp
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gen_rr2_enc0.py DEC0_1.ptx DEC0_1.generated.comp OUT.comp --dec0_1
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NVIDIA's kernel runs one 32-lane warp per 8x8-token window and keeps everything in registers. Its matrix products
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(the embedding, the attention block and the guide head) are one contiguous run of the translated main, which is cut
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out:
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wave w the translation up to the first product: the gather; the first product's A fragments (the window's 64
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feature slots per token) go to the shared array XF
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4 waves rr2_block(): embedding, attention, MLP, the tokens to the arena, the guide head to the shared array HD
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wave w the last product's D fragments are loaded from HD and the translation continues after it: the guide tail
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With --group N (2 to 4) a workgroup holds N windows along x: waves 0 ... N - 1 run the translated code of one window
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each and the block then runs once per window; the stage's dispatch is 1 / N as wide ("xN" in rr.txt). Measured on
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an RX 9070 XT (2026-10-13) that is slower than one window per workgroup (network +0.4 ms at 1280x720 with N = 4).
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With --one-wave (D4R_RR_RELAXED=3) the block is engine/rr/rr2_w.comp in NVIDIA's own 32-thread group: the gather, the
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block and the tail all run on the one wave, and XF shares its 4 KiB with the block's XT and KVS (rr2_w.comp
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RR2_XF_SHARED), so nothing goes through memory. (The gather was made a pass of its own because on the four-wave block
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it ran on one wave while three waited; on one wave there is nothing to wait for.)
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With --dec0_1 the same for dec0's second kernel (rr2_m.comp KIND 5): nothing before the block (it reads its tokens
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from the arena); after it the last product's D fragments (the MLP sum) and the registers holding r are loaded from
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MSH / RSH, and the translated tail forms y = r + MLP * s2 and computes the kernel's outputs from it.
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The translated parts hold code derived from the user's DLL: the output is model data, do not commit it.
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"""
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import re
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import sys
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from pathlib import Path
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sys.path.insert(0, str(Path(__file__).resolve().parent))
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from phase_dump import mma_statements, phases_of # noqa: E402
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def tiles(mm):
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"""per mma of a phase: (m-tile, n-tile, k-step), as phase_dump.py orders them"""
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dset = {tuple(m[2]): n for n, m in enumerate(mm)}
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prev = {n: dset.get(tuple(m[5])) for n, m in enumerate(mm)}
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step = {}
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for n in range(len(mm)):
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s, q = 0, n
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while prev[q] is not None:
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q = prev[q]
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s += 1
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step[n] = s
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a_tile, b_tile = {}, {}
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for s in range(max(step.values()) + 1):
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for t, key in enumerate(dict.fromkeys(tuple(m[3]) for n, m in enumerate(mm) if step[n] == s)):
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a_tile[(s, key)] = t
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for t, key in enumerate(dict.fromkeys(tuple(m[4]) for n, m in enumerate(mm) if step[n] == s)):
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b_tile[(s, key)] = t
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return [(a_tile[(step[n], tuple(m[3]))], b_tile[(step[n], tuple(m[4]))], step[n]) for n, m in enumerate(mm)]
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def f16vars_of(decls):
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names = set()
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for l in decls:
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if re.match(r'\s*(precise )?float16_t ', l):
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names |= set(re.findall(r'\b(rs\d+)\b', l))
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return names
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REG = r'\b(?:rs|rd|r|f|p|l)\d+(?:_low|_high)?\b'
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# what makes a statement of the gather more than index arithmetic on the parameter block
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DATA = re.compile(r'fetch0|texture|shfl_|GX\d|GA\d|GW\d|SH\d|sust_|movm_|mma_')
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def tail_inputs(pre, tail):
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"""The gather's values the tail reads: (recomputed, saved). Recomputed are the statements, in order, of values
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that are index arithmetic on the parameter block (assigned once, outside any block); saved are the names of the
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others, which the gather pass writes to the window's record."""
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assigned, depth = {}, 0
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for i, l in enumerate(pre):
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m = re.match(r'\s*(\w+) = (.*)', l)
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if m:
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assigned.setdefault(m.group(1), []).append((i, depth, m.group(2)))
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depth += l.count('{') - l.count('}')
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used, own = [], set()
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for l in tail:
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m = re.match(r'\s*(\w+) = (.*)', l)
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for v in re.findall(REG, m.group(2) if m else l):
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if v not in own and v in assigned and v not in used:
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used.append(v)
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if m:
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own.add(m.group(1))
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def closure(v, seen):
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"""statement indices v needs, or None when it is not plain index arithmetic"""
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if v in seen:
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return seen[v]
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seen[v] = None
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defs = assigned.get(v)
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if defs is None:
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seen[v] = set() # never assigned in the gather: a declaration's zero
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return seen[v]
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if len(defs) != 1 or defs[0][1] != 0 or DATA.search(defs[0][2]):
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return None
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need = {defs[0][0]}
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for u in re.findall(REG, defs[0][2]):
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c = closure(u, seen)
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if c is None:
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return None
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need |= c
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seen[v] = need
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return need
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lines, saved, seen = set(), [], {}
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for v in used:
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c = closure(v, seen)
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if c is None:
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saved.append(v)
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else:
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lines |= c
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return [pre[i] for i in sorted(lines)], saved
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def split_layout(xf_word, pre, tail, f16vars):
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"""(recomputed statements, saved names, the record's words, the GLSL locating a window's record)"""
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recomputed, saved = tail_inputs(pre, tail)
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for v in saved:
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if not (v in f16vars or re.fullmatch(r'r\d+', v)):
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raise SystemExit(f'the tail reads {v} from the gather: not a 16- or 32-bit register')
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record = 1024 + 32 * len(saved)
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# the records' rows of windows lie in up to three ranges of the arena (the runtime's choice, where the network's
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# regions are dead during encoder 0): words XF_WORD, +2, +4 their byte addresses, +1 and +3 the first two's rows
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where = (f' const uint rr2_gx = (param.w[0] + (param.w[20] & 0xffffu) + 7u) / 8u;\n'
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f' uint rr2_y = gl_WorkGroupID.y, rr2_base = param.w[{xf_word}u];\n'
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f' if (rr2_y >= param.w[{xf_word + 1}u]) {{\n'
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f' rr2_y -= param.w[{xf_word + 1}u]; rr2_base = param.w[{xf_word + 2}u];\n'
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f' if (rr2_y >= param.w[{xf_word + 3}u]) {{ rr2_y -= param.w[{xf_word + 3}u]; rr2_base = param.w[{xf_word + 4}u]; }}\n'
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f' }}\n'
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f' const uint rr2_rec = rr2_base / 4u + {record}u * (rr2_y * (param.w[0] / 8u + 1u) + gl_WorkGroupID.x);\n')
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return recomputed, saved, record, where
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def gather_pass(xf_word, head, decls, pre, tail, first, f16vars):
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"""Encoder 0 as two passes (--split gather | block): the translated gather in NVIDIA's own 32-thread groups, which
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writes each window's record to the arena, and the native block with the translated tail in 128-thread groups.
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One shader holding both runs the gather on one of the block's four waves while the other three wait, which
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costs more than the record's trip through memory (RX 9070 XT, 1280x720, 2026-10-13: gather 0.40 -> 0.24 ms).
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The record: 1024 words of A fragments ([token slot][64 FP8 feature slots], as the block's XF), then per lane the
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gather's values the tail reads. Its address: the byte address of row y's range (parameter words XF_WORD to
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XF_WORD + 4) + 4 * RECORD * (y' * (W / 8 + 1) + x), y' the row within its range."""
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recomputed, saved, record, where = split_layout(xf_word, pre, tail, f16vars)
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var = lambda r: r.lstrip('%')
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store = [' if (rr2_valid) { // the first product\'s A fragments: lane 4g + t, register q -> row, 4 k',
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' const uint l_ = gl_SubgroupInvocationID, g_ = l_ >> 2u, t_ = l_ & 3u;']
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seen = set()
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for mm_, (i, j, s) in zip(first, tiles(first)):
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if (i, s) in seen:
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continue
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seen.add((i, s))
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for q, r in enumerate(mm_[3]):
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store.append(f' rr2_arena.w[rr2_rec + rr2_uninter({16 * i + 8 * (q & 1)}u + g_) * 16u + {(32 * s + 16 * (q >> 1)) // 4}u + t_] = {var(r)};')
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for n, v in enumerate(saved):
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bits = f'uint(float16BitsToUint16({v}))' if v in f16vars else v
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store.append(f' rr2_arena.w[rr2_rec + 1024u + {len(saved)}u * l_ + {n}u] = {bits};')
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store.append(' }')
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print(f'gather pass: record of {record} words, the tail reads {", ".join(saved) or "nothing"} from it')
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return (head + '\nlayout(set = 0, binding = 2, std430) buffer Rr2Arena { uint w[]; } rr2_arena;\n'
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'uint rr2_uninter(uint c) { return (c & ~31u) | (((c & 15u) >> 1u) << 2u) | (c & 1u) | (((c >> 4u) & 1u) << 1u); }\n\n'
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'void main()\n{\n' + '\n'.join(decls) + '\n' + where +
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' const bool rr2_valid = gl_WorkGroupID.x < rr2_gx;\n'
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' if (rr2_valid) { // NVIDIA\'s warp: the translation before the first product\n' + '\n'.join(pre) + '\n }\n' +
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'\n'.join(store) + '\n}\n'), record
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def main():
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ptx, src, out = sys.argv[1:4]
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dec = '--dec0_1' in sys.argv
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# --group N: windows per workgroup (1 to 4; wave w runs the translated code of window w)
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G = int(sys.argv[sys.argv.index('--group') + 1]) if '--group' in sys.argv else 1
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kernel = 'rr2_dec0_kernel_1' if dec else 'rr2_enc0_kernel'
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lines = Path(ptx).read_text().replace('\r', '').split('\n')
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k = next(i for i, l in enumerate(lines) if f'.entry {kernel}(' in l)
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phases = phases_of(mma_statements(lines, k, len(lines)), lines)
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first, last = phases[0], phases[-1]
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var = lambda r: r.lstrip('%')
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g = Path(src).read_text().split('\n')
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m = next(i for i, l in enumerate(g) if l.startswith('void main()'))
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# --one-wave (D4R_RR_RELAXED=3): the block as rr2_w.comp, in NVIDIA's own 32-thread group, the tail on the same wave
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one_wave = '--one-wave' in sys.argv
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if one_wave and (dec or G != 1):
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raise SystemExit('--one-wave is for encoder 0 with one window per workgroup')
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head = '\n'.join(g[:m])
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if not one_wave:
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head = head.replace('layout(local_size_x = 32, local_size_y = 1, local_size_z = 1) in;',
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'layout(local_size_x = 128, local_size_y = 1, local_size_z = 1) in;')
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if dec: # the tail's tanh from rr2_pack.py's table (ptx2rr.py's RR_TANH_TABLE; its offset from OUT's rr2_stage.h)
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v = head.index('\n') + 1
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table = re.search(r'#define W_TANH (\d+)u', (Path(out).parent / 'rr2_stage.h').read_text()).group(1)
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head = head[:v] + f'#define RR_TANH_TABLE {table}u\n' + head[v:]
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body = g[m + 2:]
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while body and body[-1].strip() in ('', '}'):
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last_line = body.pop()
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if last_line.strip() == '}':
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break
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nd = next(i for i, l in enumerate(body) if not re.match(r' (precise |bool |uint64_t |float |uint |int |float16_t |f16vec2 )', l))
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calls = [i for i, l in enumerate(body) if 'mma_e4m3_f16' in l]
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a = calls[0] - 1 # '{ uint md0_, ...;'
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b = next(i for i in range(calls[-1], len(body)) if body[i].strip() == '}')
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if not body[a].strip().startswith('{ uint md0_'):
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raise SystemExit('unexpected statement before the first product: ' + body[a])
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pre, cut, tail = body[nd:a], body[a:b + 1], body[b + 1:]
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if sum(l.count('{') - l.count('}') for l in pre):
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raise SystemExit('the first product is inside a block of the translated main')
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# values the tail takes from the cut region other than the last product's results
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assigned = lambda ls: {mm_.group(1) for l in ls for mm_ in [re.match(r'\s*(\w+) = ', l)] if mm_}
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restored = {var(r) for mm_ in last for r in mm_[2]}
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rmap = {} # dec0_1: the register holding r for (row offset, column offset): y = r + (D half) * s2 in the tail
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if dec:
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place = {}
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for mm_, (i, j, s_) in zip(last, tiles(last)):
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for q, r in enumerate(mm_[2]):
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place[r] = (16 * i + 8 * q, 8 * j)
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text_tail = '\n'.join(lines[last[-1][1]:])
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half = {}
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for mo in re.finditer(r'mov\.b32\s+\{(%rs\d+),\s*(%rs\d+)\},\s*(%r\d+);', text_tail):
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if mo.group(3) in place:
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half[mo.group(1)] = (*place[mo.group(3)], 0)
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half[mo.group(2)] = (*place[mo.group(3)], 1)
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prod = {}
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for mo in re.finditer(r'mul\.f16\s+(%rs\d+),\s*(%rs\d+),\s*(%rs\d+);', text_tail):
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if mo.group(2) in half:
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prod[mo.group(1)] = half[mo.group(2)]
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for mo in re.finditer(r'add\.f16\s+(%rs\d+),\s*(%rs\d+),\s*(%rs\d+);', text_tail):
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if mo.group(2) in prod:
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rmap[var(mo.group(3))] = prod[mo.group(2)]
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# the same step in a module rewritten by build/rr/f/nv/ptx_contract.py (D4R_RR_FUSE builds): one fused instruction
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for mo in re.finditer(r'fma\.rn\.f16\s+(%rs\d+),\s*(%rs\d+),\s*(%rs\d+),\s*(%rs\d+);', text_tail):
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if mo.group(2) in half:
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rmap[var(mo.group(4))] = half[mo.group(2)]
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if len(rmap) != 2 * 2 * len(last):
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raise SystemExit(f'found {len(rmap)} residual registers, expected {4 * len(last)}')
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restored |= set(rmap)
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used = set(re.findall(r'\b[a-z]+\d+\b', '\n'.join(tail)))
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lost = sorted((assigned(cut) - assigned(pre) - restored) & used)
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# (values assigned again in the tail before their use are fine; the kernel has none on the reference build)
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keep = []
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cut_set = assigned(cut)
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for name in lost: # thread indices and the like: their assignment is carried over when it depends on nothing cut
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line = next(l for l in reversed(cut) if re.match(rf'\s*{name} = ', l))
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if set(re.findall(r'\b[a-z]+\d+\b', line.split('=', 1)[1])) & cut_set:
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raise SystemExit(f'the tail needs {name}, which the cut region computes: {line.strip()}')
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keep.append(' ' + line)
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split = sys.argv[sys.argv.index('--split') + 1] if '--split' in sys.argv else None
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xf_word = int(sys.argv[sys.argv.index('--xf-word') + 1]) if split else 0
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if split == 'gather':
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text, record = gather_pass(xf_word, '\n'.join(g[:m]), body[:nd], pre, tail, first, f16vars_of(body[:nd]))
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Path(out).write_text(text)
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Path(out).with_suffix('.record').write_text(str(record))
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return
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if dec:
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first = []
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store = [' if (rr2_valid) { // the first product\'s A fragments: lane 4g + t, register q -> row, 4 k',
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' const uint l_ = gl_SubgroupInvocationID, g_ = l_ >> 2u, t_ = l_ & 3u;']
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seen = set()
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for mm_, (i, j, s) in zip(first, tiles(first) if first else []):
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if (i, s) in seen:
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continue
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seen.add((i, s))
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for q, r in enumerate(mm_[3]):
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store.append(f' XF[gl_SubgroupID * 1024u + uninter({16 * i + 8 * (q & 1)}u + g_) * 16u + {(32 * s + 16 * (q >> 1)) // 4}u + t_] = {var(r)};')
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store.append(' }')
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load = [' { // the guide head as the last product\'s D fragments (rows g, g + 8; columns 2t, 2t + 1)',
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' const uint l_ = gl_SubgroupInvocationID, g_ = l_ >> 2u, t_ = l_ & 3u;']
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f16vars = set()
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for l in body[:nd]:
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if re.match(r'\s*(precise )?float16_t ', l):
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f16vars |= set(re.findall(r'\b(rs\d+)\b', l))
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for mm_, (i, j, s) in zip(last, tiles(last)):
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for q, r in enumerate(mm_[2]):
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row = f'({16 * i + 8 * q}u + g_)'
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load.append(f' {var(r)} = HDV({row}, {8 * j}u + 2u * t_) | (HDV({row}, {8 * j + 1}u + 2u * t_) << 16u);')
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for name, (ro, co, hf) in rmap.items():
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v = f'RSV({ro}u + g_, {co + hf}u + 2u * t_)'
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load.append(f' {name} = ' + (f'uint16BitsToFloat16(uint16_t({v}));' if name in f16vars else f'{v};'))
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load.append(' }')
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# the native block's source, without its #version line (this shader has its own)
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block = (Path(__file__).resolve().parent / ('rr2_w.comp' if one_wave else 'rr2_m.comp')).read_text().split('\n', 1)[1]
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if split == 'block': # the second pass: the block on the gather pass's record, then the tail on wave 0
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recomputed, saved, record, where = split_layout(xf_word, pre, tail, f16vars)
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restore = [' ' + (f'{v} = uint16BitsToFloat16(uint16_t(arena.w[rr2_rec + 1024u + {len(saved)}u * l_ + {n}u]));' if v in f16vars
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else f'{v} = arena.w[rr2_rec + 1024u + {len(saved)}u * l_ + {n}u];') for n, v in enumerate(saved)]
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load[2:2] = restore
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Path(out).write_text(
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head + '\n#extension GL_GOOGLE_include_directive : require\n#define RR2_EMBED 1\n#define RR2_GROUP 1\n#define RR2_XF_ARENA 1\n' +
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block + '\nuint HDV(uint row, uint col) { return col < 4u ? uint(float16BitsToUint16(HD[gl_SubgroupID * 256u + row * 4u + col])) : 0u; }\n\n'
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'void main()\n{\n' + '\n'.join(body[:nd]) + '\n' + where +
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' const bool rr2_valid = gl_SubgroupID < 1u && gl_WorkGroupID.x < rr2_gx;\n'
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' rr2_xf = rr2_rec;\n rr2_block();\n barrier();\n if (rr2_valid) {\n' +
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' // the gather\'s index arithmetic the tail reads\n' + '\n'.join(recomputed) + '\n' +
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'\n'.join(load + keep) + '\n' + '\n'.join(tail) + '\n }\n}\n')
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return
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wx = (lambda t: t) if one_wave else (lambda t: t.replace('gl_WorkGroupID.x', f'({G}u * gl_WorkGroupID.x + gl_SubgroupID)'))
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text = (head + f'\n#extension GL_GOOGLE_include_directive : require\n#define RR2_EMBED 1\n#define RR2_GROUP {G}\n' +
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('#define RR2_XF_SHARED 1\n' if one_wave else '') + block + '\n' +
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('uint HDV(uint row, uint col) { return uint(float16BitsToUint16(rr2_msh(row, col))); }\n'
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'uint RSV(uint row, uint col) { return uint(float16BitsToUint16(rr2_rsh(row, col))); }\n\n' if dec else
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'uint HDV(uint row, uint col) { return col < 4u ? uint(float16BitsToUint16(HD[gl_SubgroupID * 256u + row * 4u + col])) : 0u; }\n\n') +
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'void main()\n{\n' + '\n'.join(body[:nd]) +
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'\n // this wave\'s window, when the level has it\n'
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' const uint rr2_gx = (param.w[0] + (param.w[20] & 0xffffu) + 7u) / 8u;\n'
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f' const bool rr2_valid = gl_SubgroupID < {G}u && {G}u * gl_WorkGroupID.x + gl_SubgroupID < rr2_gx;\n'
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' if (rr2_valid) { // NVIDIA\'s warp: the translation before the first product\n' + wx('\n'.join(pre)) + '\n }\n' +
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('' if dec else '\n'.join(store)) +
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# (the block runs unconditionally, also for a window past the level's last one: it writes nothing there, and
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# inside a branch the driver compiles it much slower)
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('\n barrier();\n rr2_block();\n barrier();\n' if G == 1 else
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f'\n barrier();\n for (uint w_ = 0u; w_ < {G}u; ++w_) {{\n rr2_win = w_;\n'
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' rr2_block();\n barrier();\n }\n') + ' if (rr2_valid) {\n' +
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'\n'.join(load + keep) + '\n' + wx('\n'.join(tail)) + '\n }\n}\n')
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Path(out).write_text(text)
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print(f'{out}: {len(pre)} gather lines, {len(cut)} cut, {len(tail)} tail lines, {len(seen)} A fragment sets')
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if __name__ == '__main__':
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main()
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