ayo
22026ede12
Preset K, byte-identical to the previous output in all captured buffers and the harness image, measured on an RX 7700 XT: - LDS row padding so WMMA operand loads hit distinct banks - WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for enc0/dec0/dec3, more waves per window in enc4/dec4/dec5 - cheaper operand plumbing in common/wmma_layout.h (packed f16 conversions, no dynamic vector indexing), raw buffer weight loads, accumulator-init vectors prepared once - enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split - dec5 as four dependent phase kernels
17 lines
546 B
Plaintext
17 lines
546 B
Plaintext
// fast numerics: intermediate activations f16 (no FP8 re-quantisation), f32 accumulation through GEMM chains
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// RX 7700 XT: VGPR cap 160 removes the scratch use; byte-identical to the default build, gfx1101 only
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// d4r-build-flags-gfx1101: -DSWIN_MAX_VGPR=160
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#define SWIN_NO_Q8
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#define SWIN_F32ACC
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#ifndef SWIN_MAX_VGPR
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#define SWIN_MAX_VGPR 128
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#endif
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#ifndef SWIN_MLP_R
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#define SWIN_MLP_R(NW) 2
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#endif
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#include "swin_block.h"
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#ifndef SWIN_NW
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#define SWIN_NW 8
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#endif
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SWIN_MODULE_W(rrlite_dec1_4x4, 64, 2, SWIN_NW, 0, false, CommonParams, 96)
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