ayo
0e851b7f90
- Add native preset K kernels for gfx1030–gfx1036 using software matrix products, with fast and accuracy builds and RDNA2 motion kernels. - Follow OptiScaler's DLSS and RR preset overrides, sanitize unsupported values and select the preset matching the feature's quality mode. - Enable FSR 4 under NVIDIA GPU spoofing by exposing real AMD PCI IDs to OptiScaler and FidelityFX modules; bundle AMD's loader and upscaler. - Keep K on native kernels in engine auto mode unless HIP is selected, and fall back to CUDA for M/L when shader_float8 is unavailable. - Add native-engine K GPU timings, preset recreation harness controls and regression coverage; fix the input-wait test's glibc name clash. - Update configuration, installer guidance and release documentation, simplify the README and move gameplay videos to docs/videos.md. RDNA2 kernels remain untested on RDNA2 hardware; software matrix arithmetic was validated against WMMA on RDNA3.
296 lines
11 KiB
C
296 lines
11 KiB
C
// Native kernels (gfx11 / gfx12 wave32 WMMA) for the DLSS 4 (preset K) DltssPaddedWinLayer blocks.
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// Semantics: kernels/tools/pwin_model.py (verified against the PTX interpreter, kernels/tools/ptxsim.py).
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//
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// Layout conventions (transposed WMMA, as in the preset M kernels): a GEMM Y = X W is computed as
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// Y^T = W^T X^T with the weights as the WMMA A operand (lane l: output channel l & 15) and the activations
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// as the B operand (lane l: token l & 15). The f32 result then has lane l = token l & 15 and VGPR i =
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// output channel wm_acc_row(i) of the 16-channel tile ("D^T"); ../common/wmma_layout.h has the per-target
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// register layouts (gfx11: channel 2i + (l >> 4); gfx12: channel i + 8 (l >> 4)).
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#pragma once
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#include <hip/hip_runtime.h>
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#include <stdint.h>
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#include "../common/wmma_layout.h"
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#if defined(D4R_ACCURACY) && defined(PWIN_F32ACC)
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#undef PWIN_F32ACC
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#endif
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// D4R_FAST_MATH: the opt-in approximate variant (FMA contraction allowed; not bit-identical to NVIDIA's rounding)
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#ifndef D4R_FAST_MATH
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#pragma clang fp contract(off)
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#endif
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typedef _Float16 half_t;
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typedef _Float16 hv2 __attribute__((ext_vector_type(2)));
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typedef _Float16 h16 __attribute__((ext_vector_type(16)));
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typedef float f8v __attribute__((ext_vector_type(8)));
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typedef uint32_t u8v __attribute__((ext_vector_type(8)));
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typedef uint32_t u4v __attribute__((ext_vector_type(4)));
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__device__ __forceinline__ half_t half_reciprocal(half_t h)
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{
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#ifdef PWIN_NATIVE_HRECIP
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return __builtin_amdgcn_rcph(h);
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#else
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return (half_t)__builtin_amdgcn_rcpf((float)h);
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#endif
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}
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__device__ __forceinline__ half_t half_rsqrt(half_t h)
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{
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#ifdef PWIN_NATIVE_HRECIP
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return __builtin_amdgcn_rsqh(h);
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#else
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return (half_t)__builtin_amdgcn_rsqf((float)h);
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#endif
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}
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// LDS row padding in halves: activation rows of N halves are stored N + PWIN_PAD apart, so the 16 token rows a
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// WMMA operand load (op_lds / lds_row16) touches start on distinct banks (row stride = 16 mod 32 bytes). With
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// unpadded 128- or 256-byte rows every lane hits the same banks (measured: 6x slower WMMA feed). 0 = old layout.
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#ifndef PWIN_PAD
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#define PWIN_PAD 8
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#endif
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#define LDSR(N) ((N) + PWIN_PAD)
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__device__ __forceinline__ uint32_t lane_id()
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{
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return __builtin_amdgcn_mbcnt_lo(~0u, 0u);
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}
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// RDNA2: the f16-accumulator WMMA variants need the instruction; the f32 path (software products) serves them
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#ifdef __GFX10__
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#undef PWIN_NATIVE_F16ACC
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#undef PWIN_F16ACC_NATIVE
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#endif
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typedef wm_op op_t; // WMMA operand: u8v (gfx11) or u4v (gfx12)
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// one k16 step with the f16 accumulator of NVIDIA's f16 wmma (rounded after the step)
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// PWIN_F32ACC: keep the accumulator in f32 through the chain (rounded to f16 where the values are used)
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__device__ __forceinline__ f8v mma16(const op_t& a, const op_t& b, f8v c)
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{
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#if defined(PWIN_NATIVE_F16ACC) && !defined(PWIN_F32ACC) && D4R_WMMA_LAYOUT == 11
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h16 hc = {};
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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hc[2 * i] = (half_t)c[i];
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const h16 hd = __builtin_amdgcn_wmma_f16_16x16x16_f16_w32(
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__builtin_bit_cast(h16, a), __builtin_bit_cast(h16, b), hc, false);
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f8v d;
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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d[i] = (float)hd[2 * i];
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#else
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f8v d = wm_mma(a, b, c);
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#ifndef PWIN_F32ACC
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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d[i] = (float)(half_t)d[i];
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#endif
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#endif
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return d;
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}
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__device__ __forceinline__ f8v splat8(float v)
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{
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return (f8v){v, v, v, v, v, v, v, v};
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}
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__device__ __forceinline__ uint32_t other_half(uint32_t v)
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{
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return __builtin_amdgcn_permlanex16(v, v, 0x76543210u, 0xfedcba98u, false, false);
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}
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__device__ __forceinline__ uint32_t pack2(half_t lo, half_t hi)
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{
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return __builtin_bit_cast(uint32_t, (hv2){lo, hi});
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}
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__device__ __forceinline__ half_t lo16(uint32_t v)
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{
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return __builtin_bit_cast(hv2, v)[0];
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}
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__device__ __forceinline__ half_t hi16(uint32_t v)
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{
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return __builtin_bit_cast(hv2, v)[1];
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}
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// D^T f16 values (own[i] = channel wm_acc_row(i) of token l & 15) -> operand of the same token (the
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// channels become K)
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__device__ __forceinline__ op_t operand_from_dt(const half_t own[8])
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{
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return wm_op_from_acc(own);
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}
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__device__ __forceinline__ op_t operand_from_f8(f8v d)
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{
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return wm_op_from_f8(d);
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}
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// element c (0..15) of a row of 16 halves (VALU code; not a WMMA operand)
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__device__ __forceinline__ half_t op_get(const u8v& v, int c)
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{
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return (c & 1) ? hi16(v[c >> 1]) : lo16(v[c >> 1]);
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}
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__device__ __forceinline__ u8v lds_row16(const half_t* p)
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{
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const u4v a = *(const u4v*)p, b = *(const u4v*)(p + 8);
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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}
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// Global activation traffic (tokens in, rows out): PWIN_NT_LOAD / PWIN_NT_STORE mark it non-temporal so
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// it does not evict the weight images from the caches. Same data either way.
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__device__ __forceinline__ u8v gload_row16(const half_t* p)
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{
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#ifdef PWIN_NT_LOAD
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const u4v a = __builtin_nontemporal_load((const u4v*)p), b = __builtin_nontemporal_load((const u4v*)(p + 8));
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#else
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const u4v a = *(const u4v*)p, b = *(const u4v*)(p + 8);
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#endif
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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}
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__device__ __forceinline__ void gstore16(half_t* p, u4v v)
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{
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#ifdef PWIN_NT_STORE
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__builtin_nontemporal_store(v, (u4v*)p);
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#else
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*(u4v*)p = v;
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#endif
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}
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__device__ __forceinline__ void gstore_row16(half_t* dst, const u8v& v)
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{
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gstore16(dst, (u4v){v[0], v[1], v[2], v[3]});
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gstore16(dst + 8, (u4v){v[4], v[5], v[6], v[7]});
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}
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// WMMA operands from rows of 16 channels: LDS, global (PWIN_NT_LOAD as above), prep images (32-byte slots)
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__device__ __forceinline__ op_t op_lds(const half_t* p)
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{
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return wm_op_load(p);
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}
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__device__ __forceinline__ op_t op_gload(const half_t* p)
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{
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#if D4R_WMMA_LAYOUT == 12
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#ifdef PWIN_NT_LOAD
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return __builtin_nontemporal_load((const u4v*)(p + 8 * wm_half()));
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#else
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return *(const u4v*)(p + 8 * wm_half());
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#endif
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#else
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return gload_row16(p);
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#endif
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}
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__device__ __forceinline__ op_t op_img(const u8v* __restrict__ img, int idx)
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{
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return wm_op_image(img, idx);
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}
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// 8 floats of image slot `slot` + this lane's half (f32 accumulator-init vectors the prep kernel stores after the
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// operand tiles: slot pair (2 v, 2 v + 1) = rows wm_acc_row_h(., h) of vector v), slot uniform
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__device__ __forceinline__ f8v img_vec(const u8v* __restrict__ img, int slot)
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{
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const uint32_t h = lane_id() >> 4;
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#if defined(PWIN_VEC_SCALAR) // both layouts: slot pair (2 v, 2 v + 1) = the two halves' rows
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// both halves' slots with wave-uniform (scalar) loads, then one select per value (instead of a per-lane
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// vector load, or 8 shifts + 8 f16 -> f32 conversions from the weights); the same f32 values
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const u8v x0 = img[slot], x1 = img[slot + 1];
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u8v x;
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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x[i] = h ? x1[i] : x0[i];
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return __builtin_bit_cast(f8v, x);
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#elif D4R_WMMA_LAYOUT == 12 || defined(PWIN_NO_BUFFER_IMG)
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const u8v x = img[slot + (int)h];
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return __builtin_bit_cast(f8v, x);
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#else
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const __amdgpu_buffer_rsrc_t r = __builtin_amdgcn_make_buffer_rsrc((void*)img, (short)0, 0x7fffffff, 0x31004000);
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const uint32_t vo = h * 32u, so = 32u * (uint32_t)slot;
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const u4v a = __builtin_amdgcn_raw_buffer_load_b128(r, vo, so, 0), b = __builtin_amdgcn_raw_buffer_load_b128(r, vo + 16, so, 0);
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return __builtin_bit_cast(f8v, (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]});
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#endif
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}
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// slot (tile, lane l & 15) of an operand image in global memory: tile is wave-uniform, so the row address stays a
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// scalar base and only the lane indexes it (global loads with an SGPR base and a VGPR offset; written as one
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// index tile * 16 + m every load paid 64-bit VALU address arithmetic)
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__device__ __forceinline__ op_t op_imgt(const u8v* __restrict__ img, int tile)
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{
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#if D4R_WMMA_LAYOUT == 12 || defined(PWIN_NO_BUFFER_IMG)
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return wm_op_image(img + 16 * tile, (int)(lane_id() & 15));
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#else
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// gfx11: a raw buffer load (resource from img: base in SGPRs, 0x31004000 = gfx11 raw dword3, validated), the
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// tile offset as the scalar offset and the lane's 32-byte slot as the vector offset: no VALU address math
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const __amdgpu_buffer_rsrc_t r = __builtin_amdgcn_make_buffer_rsrc((void*)img, (short)0, 0x7fffffff, 0x31004000);
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const uint32_t vo = (lane_id() & 15) * 32u, so = 512u * (uint32_t)tile;
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const u4v a = __builtin_amdgcn_raw_buffer_load_b128(r, vo, so, 0), b = __builtin_amdgcn_raw_buffer_load_b128(r, vo + 16, so, 0);
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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#endif
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}
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// operand -> slot idx of an operand image in LDS (read back with op_img)
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__device__ __forceinline__ void op_img_store(u8v* img, int idx, const op_t& v)
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{
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#if D4R_WMMA_LAYOUT == 12
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((u4v*)img)[2 * idx + wm_half()] = v;
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#else
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if (!wm_half())
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img[idx] = v;
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#endif
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}
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// operand (16 channels of this lane's token) -> row of `count` (8 or 16) channels in global memory, if ok
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__device__ __forceinline__ void op_gstore(half_t* dst, const op_t& v, bool ok, int count = 16)
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{
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#if D4R_WMMA_LAYOUT == 12
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if (ok && (wm_half() == 0 || count >= 16))
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gstore16(dst + 8 * wm_half(), v);
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#else
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if (!wm_half() && ok)
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{
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gstore16(dst, (u4v){v[0], v[1], v[2], v[3]});
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if (count >= 16)
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gstore16(dst + 8, (u4v){v[4], v[5], v[6], v[7]});
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}
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#endif
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}
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// operand -> row of 16 channels in LDS
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__device__ __forceinline__ void op_store(half_t* dst, const op_t& v)
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{
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wm_op_store(dst, v);
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}
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__device__ __forceinline__ void block_sync()
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{
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__syncthreads();
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}
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__device__ __forceinline__ int mirror(int v, int n)
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{
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v = v < 0 ? -v : v;
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return v < 2 * n - 2 - v ? v : 2 * n - 2 - v;
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}
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// ------------------------------------------------ pre-swizzled f16 weight fragments (NVIDIA)
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// logical B[k][n] of one 16x16 fragment (512 bytes)
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__device__ __forceinline__ int frag_offset(int k, int n)
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{
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return 64 * (n & 7) + 16 * ((k & 7) >> 1) + 8 * (n >> 3) + 4 * (k >> 3) + 2 * (k & 1);
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}
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// Diagnostic phase stamps (-DPWIN_PROF): per-wave SHADER_CYCLES deltas summed into d4r_dbg[k], wave counts into
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// d4r_dbg[32 + k] (read back by bench/native/pwbench). Region k ends at PROF(k). Off: no code.
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#ifdef PWIN_PROF
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__device__ unsigned long long d4r_dbg[64];
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#define PROF_INIT uint32_t prof_last_ = (uint32_t)__builtin_readcyclecounter()
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#define PROF(k) \
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do \
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{ \
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const uint32_t n_ = (uint32_t)__builtin_readcyclecounter(); \
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if (lane_id() == 0) \
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{ \
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__hip_atomic_fetch_add(&d4r_dbg[k], (unsigned long long)((n_ - prof_last_) & 0xfffffu), __ATOMIC_RELAXED, \
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__HIP_MEMORY_SCOPE_AGENT); \
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__hip_atomic_fetch_add(&d4r_dbg[32 + (k)], 1ull, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); \
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} \
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prof_last_ = n_; \
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} while (0)
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#else
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#define PROF_INIT do {} while (0)
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#define PROF(k) do {} while (0)
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#endif
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