ayo
2558fcbd39
- Match render/compute adapters and gate RR models by GPU capabilities - Add RDNA2 native texture kernels and fix FP16 rounding - Harden model builds, cache validation and packaging - Add startup tracing, timeouts, documentation and regression tests
73 lines
3.5 KiB
C
73 lines
3.5 KiB
C
// Structured path-B tile fill. Same color/depth values and 24-column LDS layout
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// as the original kernel; work-items traverse x/y directly without integer division.
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#pragma once
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#ifndef D4R_OUTPUT_TILE_PITCH
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#define D4R_OUTPUT_TILE_PITCH 24
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#endif
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static_assert(D4R_OUTPUT_TILE_PITCH >= 24 && D4R_OUTPUT_TILE_PITCH <= 32, "LDS tile pitch capacity");
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RT void output_color_pack(f4 color, float exposure, uint32_t* a, uint32_t* b)
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{
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const float r = fmaxn(color[0], 0.0f), g = fmaxn(color[1], 0.0f), blue = fmaxn(color[2], 0.0f);
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const float qr = r * 0.25f, hg = g * 0.5f, qb = blue * 0.25f;
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const float y = exposure * ((qr + hg) + qb);
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const float co = __builtin_fmaf(r, 0.5f, g * 0.0f) - blue * 0.5f;
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const float cg = (hg - qr) - qb;
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float weight;
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if (y < 1000.0f)
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weight = rcp_a(y + 1.0f);
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else
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{
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const float z = __builtin_fmaf(y, 9.0f, 1.0f);
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const float ln = lg2_a(z) * asf(0x3F317218u);
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const float q = div_a(ln, 9.0f) + asf(0xBC4FAE29u);
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weight = rcp_a(y) * q;
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}
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// f2h_rn: rounded to f32 and then to f16, as ZLUDA's compile does (no v_fma_mixlo of the product)
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*a = pack16(ashu(f2h_rn(y * weight)), ashu(f2h_rn((exposure * co) * weight)));
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*b = pack16(ashu(f2h_rn((exposure * cg) * weight)), ashu(f2h_rn(color[3])));
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}
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RT int output_tile_coord(int relative, int lo, int hi)
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{
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return relative > 0 ? __builtin_elementwise_min(lo + relative, hi) : lo;
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}
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RT void output_tile_fill(const AS4 uint8_t* args, int x0, int y0, int width, int height,
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float exposure, AS3 uint8_t* color_tile, AS3 uint8_t* depth_tile)
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{
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const uint64_t color = *(const AS4 uint64_t*)(args + 200);
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const uint64_t depth = *(const AS4 uint64_t*)(args + 248);
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const int cx0 = *(const AS4 int32_t*)(args + 208), cy0 = *(const AS4 int32_t*)(args + 212);
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const int cx1 = *(const AS4 int32_t*)(args + 216), cy1 = *(const AS4 int32_t*)(args + 220);
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const int dx0 = *(const AS4 int32_t*)(args + 96), dy0 = *(const AS4 int32_t*)(args + 100);
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const int dx1 = *(const AS4 int32_t*)(args + 104), dy1 = *(const AS4 int32_t*)(args + 108);
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bool fill_depth = true;
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#ifdef D4R_K_NO_DEPTH_TILE
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// Pinned K LUT has |slope|<=1. Its 4x3 color stencil stays in the four-texel
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// halo for positive upsampling scale<=1, so no color read aliases depth LDS.
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// Keep the original fill outside the proven geometry. Input depth is unchanged.
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const float scale_x = *(const AS4 float*)(args + 40), scale_y = *(const AS4 float*)(args + 44);
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fill_depth = !(scale_x > 0.0f && scale_x <= 1.0f && scale_y > 0.0f && scale_y <= 1.0f);
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#endif
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// Path B selects a footprint at most 24 x 24. At each iteration 0<=x<width,
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// 0<=y<height: color accesses stay within 4608 bytes, depth within 2304 bytes.
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for (int y = __builtin_amdgcn_workitem_id_y(); y < height; y += 16)
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for (int x = __builtin_amdgcn_workitem_id_x(); x < width; x += 16)
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{
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const int sx = x0 + x, sy = y0 + y;
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const f4 c = tex_fetch(color, output_tile_coord(sx, cx0, cx1), output_tile_coord(sy, cy0, cy1));
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uint32_t a, b;
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output_color_pack(c, exposure, &a, &b);
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AS3 uint32_t* dst = (AS3 uint32_t*)(color_tile + y * (8 * D4R_OUTPUT_TILE_PITCH) + x * 8);
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dst[0] = a;
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dst[1] = b;
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if (fill_depth)
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{
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const f4 d = tex_fetch(depth, output_tile_coord(sx, dx0, dx1), output_tile_coord(sy, dy0, dy1));
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*(AS3 float*)(depth_tile + y * (4 * D4R_OUTPUT_TILE_PITCH) + x * 4) = d[0];
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}
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}
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}
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