ayo
a627439025
Shim - Adaptive output-event wait: sleep to ~120 us before the predicted completion (smoothed per wait site), spin near it, back off when late. D4R_SHIM_OUTPUT_POLL_US restores a fixed interval. - Defer the input-marker wait into the worker thread with VRAM interop (D4R_SHIM_DEFER_MARKER, default on), taking the host setup off the critical path. MicroCUDA - Experimental ZLUDA-free backend in wine_nvcuda_bridge, plus tools/microcuda and scripts/build_microcuda.sh. Serves accuracy, fast and native kernels; unregistered modules fall back to the reference path. Unclassified writes invalidate prepared weights. M kernels - SWIN_PREP_IDENTITY_AT: key weight prep by allocation identity (MicroCUDA); enc3 tube uses it with 8 slots. ZLUDA ignores it. - dec2 (gfx1101): SWIN_PACKED_RESIDUAL, byte-identical, ~1.6% faster. - Opt-in gfx12 hardware fp8 conversion (SWIN_FP8_HWCVT), unverified on hardware. Native K translators - ctile: handle variants that re-materialize the parameter base (mvlo). - rewrite_output: check live-in registers, not just outputs. - build.sh: native input covers all 8 flag variants, output the 4 HDR "max" variants; depth-tile skip stays mvhi-only. Tools - dump_runner and bench_dlss_kernel harness additions.
184 lines
11 KiB
Bash
Executable File
184 lines
11 KiB
Bash
Executable File
#!/usr/bin/env bash
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# Builds the native replacements for DLSS kernels into one directory that ZLUDA serves them from
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# (D4R_ZLUDA_NATIVE_DIR, or NativeKernelDirFast in d4r.ini). See docs/native-kernels.md.
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#
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# usage: kernels/build.sh [all|k|l|m|tex] [OUT_DIR] (default: all, kernels/out/native)
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#
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# D4R_ROCM_DIR ROCm installation with clang and the HIP device libraries (default /opt/rocm)
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# D4R_GPU_ARCH target GPU (default gfx1101): an RDNA3 (gfx110x) or RDNA4 (gfx120x) target; the kernels
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# need wave32 WMMA, and kernels/common/wmma_layout.h picks the register layout per target
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# D4R_NATIVE_FP8 1 (RDNA4 only): the variant for ZLUDA's native FP8 WMMA (d4r.ini [Kernels] NativeFp8):
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# M's layers on FP8 WMMA with NVIDIA's e4m3 activations, texture tails matching ZLUDA's
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# D4R_ZLUDA_WMMA_FP8_NATIVE lowering. K is the same in both variants.
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# D4R_PREFER_ACCURACY 1: preserve FP8 quantization, per-MMA f16 rounding and denormal handling;
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# build a separate set (default output: kernels/out/native/accuracy).
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# Texture kernels (tex) are NVIDIA's PTX with parts replaced, so they additionally need:
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# D4R_DLSS_DLL nvngx_dlss.dll 310.7 (its PTX is extracted into kernels/extracted/, never committed)
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# D4R_ZLUDA_EMIT ZLUDA's d4r_emit (patches/zluda applied; `cargo build --release -p ptx --example d4r_emit`),
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# which compiles PTX offline for D4R_GPU_ARCH (no GPU of that kind needed)
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# D4R_DLSS_PTX_DIR optional pre-extracted PTX directory for parallel per-target builds
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set -euo pipefail
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shopt -s extglob
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HERE="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
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WHAT="${1:-all}"
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ACCURACY="${D4R_PREFER_ACCURACY:-0}"
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[[ "$ACCURACY" == 0 || "$ACCURACY" == 1 ]] || { echo "D4R_PREFER_ACCURACY must be 0 or 1" >&2; exit 2; }
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DEFAULT_OUT="$HERE/out/native"
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[[ "$ACCURACY" == 1 ]] && DEFAULT_OUT+="/accuracy"
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OUT="$(realpath -m "${2:-$DEFAULT_OUT}")"
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ROCM="${D4R_ROCM_DIR:-/opt/rocm}"
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ARCH="${D4R_GPU_ARCH:-gfx1101}"
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FP8="${D4R_NATIVE_FP8:-0}"
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case "$ARCH" in
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gfx11[0-9][0-9]) [[ "$FP8" == 1 ]] && { echo "D4R_NATIVE_FP8 needs an RDNA4 (gfx12) target" >&2; exit 2; } ;;
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gfx12[0-9][0-9]) ;;
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*) echo "unsupported D4R_GPU_ARCH $ARCH (RDNA3 gfx110x or RDNA4 gfx120x)" >&2; exit 2 ;;
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esac
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CLANG="$ROCM/lib/llvm/bin/clang++"
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[[ -x "$CLANG" ]] || { echo "clang++ not found in $ROCM/lib/llvm/bin (set D4R_ROCM_DIR)" >&2; exit 2; }
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mkdir -p "$OUT"
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case "$WHAT" in all|k|l|m|tex) ;; *) echo "unknown kernel family: $WHAT" >&2; exit 2 ;; esac
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# Never certify a directory containing older fast binaries as an accuracy set.
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if [[ "$ACCURACY" == 1 ]] && compgen -G "$OUT/*.hsaco" >/dev/null &&
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{ [[ ! -f "$OUT/d4r-accuracy.txt" ]] || [[ "$(cat "$OUT/d4r-accuracy.txt")" != 1 ]]; }; then
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echo "accuracy kernels need an empty output directory or an existing accuracy set: $OUT" >&2
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exit 2
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fi
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rm -f "$OUT/d4r-accuracy.txt"
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# HIP source -> raw code object (the kernel name inside matches the DLSS kernel it replaces)
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build_hip() {
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local src="$1" extra="${2:-}" name
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name="$(basename "$src" .hip)"
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local tmp flags
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tmp="$(mktemp -d)"
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# per-kernel compiler flags from a "// d4r-build-flags: ..." line in the source. A line for the target
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# ("// d4r-build-flags-gfx1101:", or "// d4r-build-flags-gfx12:" for any gfx12 target) replaces it.
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flags="$(sed -n 's|^// d4r-build-flags: *||p' "$src")"
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for tag in "$ARCH" "${ARCH%??}"; do
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if grep -q "^// d4r-build-flags-$tag:" "$src"; then
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flags="$(sed -n "s|^// d4r-build-flags-$tag: *||p" "$src")"
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break
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fi
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done
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[[ "$ACCURACY" == 1 ]] && extra+=" -DD4R_ACCURACY"
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# shellcheck disable=SC2086
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(cd "$tmp" && "$CLANG" -x hip --offload-arch="$ARCH" --offload-device-only -O3 $flags $extra -I"$ROCM/include" \
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--rocm-path="$ROCM" --rocm-device-lib-path="$ROCM/amdgcn/bitcode" -I"$(dirname "$src")" \
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-o "$OUT/$name.hsaco" "$src" -save-temps=cwd --no-gpu-bundle-output)
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printf '%-52s %s\n' "$name" "$(grep -hE '^; (NumVgprs|ScratchSize|Occupancy)' "$tmp"/*.s | tail -3 | paste -sd' ')"
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rm -rf "$tmp"
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}
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if [[ "$WHAT" == all || "$WHAT" == k ]]; then
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echo "== DLSS 4 (preset K) transformer layers"
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for src in "$HERE"/k/dltss_pwin_*.hip; do build_hip "$src"; done
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fi
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if [[ "$WHAT" == all || "$WHAT" == m || "$WHAT" == l ]]; then
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echo "== DLSS 4.5 (presets L/M) shared Swin layers"
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for src in "$HERE"/m/rrlite_*.hip; do build_hip "$src" "$([[ "$FP8" == 1 ]] && echo -DD4R_FP8_WMMA)"; done
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fi
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if [[ "$WHAT" == all || "$WHAT" == tex || "$WHAT" == l ]]; then
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echo "== texture kernels (NVIDIA PTX with native parts)"
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: "${D4R_DLSS_DLL:?set D4R_DLSS_DLL to nvngx_dlss.dll (310.7)}"
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: "${D4R_ZLUDA_EMIT:?set D4R_ZLUDA_EMIT to d4r_emit from a ZLUDA build with patches/zluda}"
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PTX_DIR="${D4R_DLSS_PTX_DIR:-$HERE/extracted/ptx}"
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if [[ -z "${D4R_DLSS_PTX_DIR:-}" ]]; then
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python3 "$HERE/tools/extract_dlss_ptx.py" "$D4R_DLSS_DLL" "$PTX_DIR"
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elif [[ ! -d "$PTX_DIR" ]]; then
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echo "missing extracted PTX directory: $PTX_DIR" >&2; exit 2
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fi
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# kernel : source of its native part [: w64 = compiled as wave64 (two CUDA warps per wave; RDNA3 issues
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# FP32 work for all 64 lanes at once). Only for kernels without MMAs; measured faster, bit-identical:
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# post 0.89 -> 0.77 ms, hiluma output 0.905 -> 0.887 ms (downsample was slower as wave64).]
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# Every flag combination DLSS selects (motion vectors hi/lo, HDR/LDR, depth inverted/regular, ...) gets
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# the same treatment, so games other than the one measured run the native versions too.
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specs=()
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if [[ "$WHAT" != l ]]; then
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specs+=(rrlite_dec0_4x4_folded:dec0_head)
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for mv in mvhi mvlo; do
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for range in hdr ldr; do
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specs+=("rrlite_enc0_4x4_${mv}_${range}_folded:enc0_tail")
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for v in 3_1 3_2; do specs+=("rrlite_post_${v}_${mv}_${range}_folded:sust_only:w64"); done
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for depth in depthinv depthreg; do
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for kind in "" _max; do
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[[ -z "$kind" ]] && specs+=("hiluma_engine_output_${depth}_${mv}_${range}_v1_rel:sust_only:w64")
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specs+=("hiluma_engine_output_${depth}_${mv}_${range}${kind}_v2_rel:sust_only:w64")
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done
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done
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done
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done
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fi
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# L's unfolded variants keep their complete neural arithmetic. The folded M
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# GEMM heads/tails are incompatible; substitute only the surface stores.
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specs+=(rrlite_dec0_4x4:sust_only)
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for mv in mvhi mvlo; do
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for range in hdr ldr; do
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specs+=("rrlite_enc0_4x4_${mv}_${range}:sust_only")
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for v in 3_1 3_2; do specs+=("rrlite_post_${v}_${mv}_${range}:sust_only:w64"); done
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done
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done
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# downsample: wave64 is slower on RDNA3 and faster on RDNA4 (RX 9070 XT: 0.37 -> 0.34 ms at 4K, same output)
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downsample_mode=""
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[[ "$ARCH" == gfx12* ]] && downsample_mode=":w64"
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for mode in static dynamic; do
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for range in hdr ldr; do specs+=("rrlite_downsample_kernel_${mode}_${range}:sust_only${downsample_mode}"); done
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done
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# The fast set serves K's hiluma input/output kernels from native code translated from the PTX
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# (kernels/native): these builds replace the sust_only build of the same name. Every flag variant whose
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# code the translators prove compatible is covered (they refuse anything else): input = all 8
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# depth x motion x range variants; output = the 4 HDR "max" variants (the LDR max kernels are a different
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# kernel structure and keep the sust_only build). D4R_K_NO_DEPTH_TILE (skip the depth tile fill) is proven
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# for mvhi only: mvlo kernels read the depth tile, so they keep the fill (measured: byte-exact only then).
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# The accuracy set keeps ZLUDA's compile (denormals preserved).
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native_outs=() native_ins=()
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for depth in depthinv depthreg; do
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for mv in mvhi mvlo; do
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native_outs+=("hiluma_engine_output_${depth}_${mv}_hdr_max_v2_rel")
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for range in hdr ldr; do native_ins+=("hiluma_engine_input_${depth}_${mv}_${range}_v2_rel"); done
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done
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done
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for spec in "${specs[@]}"; do
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IFS=: read -r kernel src mode <<< "$spec"
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[[ "$ACCURACY" == 0 && " ${native_outs[*]} " == *" $kernel "* ]] && continue
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# accuracy sets are wave32, except M's post and downsample kernels on RDNA4: their wave64 builds keep the
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# denormal handling and gave the same image on an RX 9070 XT (post 0.79 -> 0.67 ms, downsample 0.43 -> 0.39 ms)
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w64=0
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if [[ "$mode" == w64 ]]; then
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[[ "$ACCURACY" == 0 ]] && w64=1
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[[ "$ARCH" == gfx12* && "$kernel" == rrlite_@(post|downsample)_* ]] && w64=1
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fi
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D4R_PREFER_ACCURACY="$ACCURACY" D4R_TEX_ACCURACY_WAVE64="$w64" \
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D4R_ZLUDA_WAVE64="$w64" D4R_ROCM_DIR="$ROCM" D4R_GPU_ARCH="$ARCH" \
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D4R_TEX_FP8="$FP8" D4R_DLSS_PTX_DIR="$PTX_DIR" "$HERE/tex/build_tex.sh" "$kernel" "$src" "$OUT"
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done
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if [[ "$WHAT" != l && "$ACCURACY" == 0 ]]; then
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# NVIDIA's PTX translated to HIP (native/ptx2hip.py) and rebuilt natively; the generated sources stay in a
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# temporary directory. They run through the same texture/surface helpers as the other texture kernels
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# and are byte-identical to ZLUDA's compile of the PTX (validated per variant in the harness).
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ptx_of() { grep -l -E "\.entry[[:space:]]+$1[[:space:]]*\(" "$PTX_DIR"/*.ptx | head -1; }
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NAT="$HERE/native"
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NT="$(mktemp -d)"
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trap 'rm -rf "$NT"' EXIT
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for native_out in "${native_outs[@]}"; do
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ptx="$(ptx_of "$native_out")"; [[ -n "$ptx" ]] || { echo "no PTX defines $native_out" >&2; exit 2; }
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# hiluma output (path B for Quality..UltraPerf), LDS tile as a function, global-memory redirect stores
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python3 "$NAT/ptx2hip.py" --ctile --as1 "$ptx" "$native_out" > "$NT/output_translated.hip"
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python3 "$NAT/rewrite_output.py" "$NT/output_translated.hip" > "$NT/$native_out.hip"
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depth_tile=(); [[ "$native_out" == *_mvhi_* ]] && depth_tile=(-DD4R_K_NO_DEPTH_TILE)
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D4R_ROCM_DIR="$ROCM" D4R_GPU_ARCH="$ARCH" "$NAT/build_native.sh" "$NT/$native_out.hip" "$OUT/$native_out.hsaco" \
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-DD4R_NATIVE_F2I "${depth_tile[@]}" -DD4R_AS1_STORES
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done
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for native_in in "${native_ins[@]}"; do
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ptx="$(ptx_of "$native_in")"; [[ -n "$ptx" ]] || { echo "no PTX defines $native_in" >&2; exit 2; }
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# hiluma input: per-thread LDS scratch and local array in registers (in_lds2reg.py), wave32
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python3 "$NAT/ptx2hip.py" --ifconv --sink "$ptx" "$native_in" > "$NT/in_ifs.hip"
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python3 "$NAT/in_lds2reg.py" "$NT/in_ifs.hip" > "$NT/$native_in.hip"
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D4R_ROCM_DIR="$ROCM" D4R_GPU_ARCH="$ARCH" WAVE=32 "$NAT/build_native.sh" "$NT/$native_in.hip" "$OUT/$native_in.hsaco"
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done
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fi
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fi
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[[ "$ACCURACY" == 1 ]] && printf '1\n' > "$OUT/d4r-accuracy.txt"
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echo "native kernels in $OUT"
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