woutermans 1038825225 Hardware e4m3 decode in dec0's tail on the native-FP8 build ...

make_ptx.py turns the 32 cvt.rn.f16x2.e4m3x2 of rrlite_dec0_4x4_folded into calls of d4r_dec_e4m3x2 (tex_common.h) when D4R_TEX_FP8=1: v_cvt_pk_f32_fp8 and two conversions to f16 instead of ZLUDA's integer lowering (about 25 instructions each; the kernel goes from 4058 to 3418 instructions). The conversion equals ZLUDA's e4m3_to_f16_bits for every code except the NaN codes 0x7f / 0xff, checked over all 65536 code pairs on an RX 9070 XT, and the head never stages those codes (it clamps to +-448 before encoding). Harness frames are byte-identical in the accuracy and the fast set, over a 16-frame moving sequence in the accuracy set. dec0 at 2227x1253 render: 0.43 -> 0.38 ms (accuracy), 0.36 -> 0.30 ms (fast). -DD4R_TEX_SOFT_E4M3 gives ZLUDA's lowering; builds without D4R_TEX_FP8 keep the PTX instruction.

2026-10-07 01:15:36 +02:00

..

build_tex.sh

Hardware e4m3 decode in dec0's tail on the native-FP8 build

2026-10-07 01:15:36 +02:00

dec0_head.hip

Hardware e4m3 in the texture tails: enc0 tail and dec0 head

2026-10-06 23:25:14 +02:00

enc0_tail.hip

Hardware e4m3 in the texture tails: enc0 tail and dec0 head

2026-10-06 23:25:14 +02:00

make_ptx.py

Hardware e4m3 decode in dec0's tail on the native-FP8 build

2026-10-07 01:15:36 +02:00

sust_only.hip

d4r: official NVIDIA DLSS on AMD GPUs under Linux and Proton

2026-09-27 15:26:56 -04:00

tex_common.h

Hardware e4m3 decode in dec0's tail on the native-FP8 build

2026-10-07 01:15:36 +02:00