woutermans
417abc64b5
0008 was already taken by 0008-native-post-phase-kernels.patch, so the five patches that follow it in the build order shift up by one: ray-reconstruction PTX support, native-FP8 conversion, packed FP8 operands, shadow-store coalescing and signed FP8 conversion. The patches themselves are unchanged; only their numbers and the references in README.md, docs/building.md, docs/native-kernels.md, docs/rr-engine.md, packaging/SOURCES.txt and scripts/build_release_glibc241.sh move.
35 lines
2.2 KiB
Diff
35 lines
2.2 KiB
Diff
diff --git a/ptx/lib/zluda_ptx_impl.cpp b/ptx/lib/zluda_ptx_impl.cpp
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--- a/ptx/lib/zluda_ptx_impl.cpp
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+++ b/ptx/lib/zluda_ptx_impl.cpp
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@@ -877,21 +877,18 @@
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typedef _Float16 half_vector __attribute__((ext_vector_type(2)));
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typedef uint16_t magnitude_vector __attribute__((ext_vector_type(2)));
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const uint32_t bits = std::bit_cast<uint32_t>(input);
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- // Positive half encodings are ordered by magnitude. Clamp both lanes
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- // with one packed integer min, then retain NaNs as positive quiet NaNs.
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- // Restore original signs after conversion, including negative zero.
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const magnitude_vector magnitude = std::bit_cast<magnitude_vector>(bits & 0x7fff7fffu);
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- const magnitude_vector saturated =
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+ // Clamp finite overflow and infinities explicitly. Map NaNs to signed
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+ // infinity: native infinity encodes as 0x7f/0xff, whereas native NaN is
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+ // always 0xff. This preserves the sign without post-conversion masks.
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+ const magnitude_vector bounded =
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__builtin_elementwise_min(magnitude, magnitude_vector{0x5f00u, 0x5f00u});
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const magnitude_vector kept{
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- magnitude[0] > 0x7c00u ? uint16_t(0x7e00u) : saturated[0],
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- magnitude[1] > 0x7c00u ? uint16_t(0x7e00u) : saturated[1]};
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- const half_vector halves = std::bit_cast<half_vector>(kept);
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- const float x = float(halves[0]), y = float(halves[1]);
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- const uint32_t encoded = d4r_cvt_pk_fp8_f32(x, y, 0, false);
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- // AMD canonicalizes NaNs to 0xff. PTX retains each input's sign.
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- const uint16_t packed = uint16_t((encoded & 0x7f7fu) |
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- ((bits >> 8) & 0x80u) | ((bits >> 16) & 0x8000u));
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+ magnitude[0] > 0x7c00u ? uint16_t(0x7c00u) : bounded[0],
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+ magnitude[1] > 0x7c00u ? uint16_t(0x7c00u) : bounded[1]};
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+ const uint32_t signed_bits = std::bit_cast<uint32_t>(kept) | (bits & 0x80008000u);
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+ const half_vector halves = std::bit_cast<half_vector>(signed_bits);
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+ const uint16_t packed = uint16_t(d4r_cvt_pk_fp8_f32(float(halves[0]), float(halves[1]), 0, false));
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return std::bit_cast<Fp8x2>(packed);
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}
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