On the gfx12 native-FP8 path the Swin layers kept GEMM activations as f16
in LDS and encoded them to e4m3 again at every operand load. They are now
encoded once where they are produced, with v_cvt_pk_fp8_f32, and stored as
bytes (SWIN_A8); the patch merge reads the stored output codes. The M
downsample kernels are built as wave64 on gfx12.
RX 9070 XT, 1280x720 -> 3840x2160, D3D12 harness, DLSS 310.7: whole
evaluation 5.9 ms -> 2.8 ms of GPU time with the GPU otherwise idle, 2.4 ms
at 80-98% GPU utilisation. Harness output is byte-identical to the previous
kernels; the accuracy build matches swin_model.py on sampled blocks.
Builds without D4R_FP8_WMMA (RDNA3, and RDNA4 with NativeFp8 off) compile to
the same instructions as before.
Preset K, byte-identical to the previous output in all captured buffers
and the harness image, measured on an RX 7700 XT:
- LDS row padding so WMMA operand loads hit distinct banks
- WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for
enc0/dec0/dec3, more waves per window in enc4/dec4/dec5
- cheaper operand plumbing in common/wmma_layout.h (packed f16
conversions, no dynamic vector indexing), raw buffer weight loads,
accumulator-init vectors prepared once
- enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split
- dec5 as four dependent phase kernels
- Reprepare enc3 weights each launch to avoid stale caches after feature recreation
- Require per-slot input markers before evaluating recorded frames
- Advance split-frame timelines only through completed frames
- Add cancellation and readiness tests plus recreation consistency checks
- Update architecture and native kernel documentation
ref #8
RDNA4 (experimental; untested on RDNA4 hardware)
- kernels/common/wmma_layout.h picks the WMMA operand/accumulator layout
per target; K (pwin_*) and M (swin_*) index through it, so the same
sources build for gfx11 and gfx12. D4R_WMMA_LAYOUT=12 on gfx11 is a test
shim that runs the gfx12 indexing on gfx11 WMMA.
- M can use native e4m3 FP8 WMMA on gfx12 (D4R_NATIVE_FP8=1). Texture
tails (enc0_tail, dec0_head) get gfx12 f16 and FP8 paths that match
ZLUDA's gfx12 lowering.
- ZLUDA patch 0007: gfx12 WMMA helpers, optional native FP8 MMA
(D4R_ZLUDA_WMMA_FP8_NATIVE), a layout override for testing, and an
architecture argument for d4r_emit. Texture kernels are now compiled
offline per target through d4r_emit (D4R_ZLUDA_EMIT) instead of on the
local GPU.
- New d4r.ini option [Kernels] NativeFp8 (default on), wired through the
shim and d4r_config.py. On gfx12 the bridge serves kernels/<arch>-fp8
when it is on.
- The bridge picks the KFD GPU with the most SIMDs (so an iGPU is not
chosen over a discrete GPU); D4R_GPU_ARCH overrides it.
- kernels/build.sh and package_release.sh build gfx1100-gfx1103 and
gfx1200/gfx1201 (plus -fp8 variants), and D4R_BUNDLE_TEX takes
per-target folders.
Performance (RDNA3; harness byte-identical unless noted)
- ZLUDA patch 0006: m16n8k8 f16 MMAs on WMMA (E; not bit-exact, 52-55 dB
per layer, D4R_ZLUDA_WMMA_K8=0 disables it), per-key weight-image slots
for native prep kernels (d4r_prep_key_at, d4r_prep_key_slots), and
wave64 builds of MMA-free kernels (D4R_ZLUDA_WAVE64).
- M: packed FP8 encoding, conflict-free patch-merge reads, scalar weight
loads in enc1, and weight prep once per weight set for the six enc3
tube blocks.
- K: CU mode for the six non-wide pwin layers.
- Texture kernels: every DLSS flag variant is built natively (24 K output,
8 M post, 4 M downsample, 4 M enc0), not only Townfall's; post and K
output run as wave64.
- M direct output: rrlite_downsample_kernel writes the shim's output
buffer; the shim's default direct-output presets are now 11,13.
Tools
- dump_runner takes the prep grid from d4r_prep_blocks and refuses
texture/surface dumps.
- New pwin_check.py, swin_check.py, model_enc3.py and tail_check.hip.
Docs: README GPU table and RDNA4 notes, building (patches 0002-0007,
d4r_emit), native-kernels (RDNA4 section), performance (new numbers),
packaging README. Version 0.1.2.
woutermans