Expand Windows GPU support, add native FSR RR, and improve SR interop
Add a native D3D12 FSR Ray Regeneration route for gfx1200/gfx1201, using the game's device and queue with embedded HLSL guide preparation and output composition. Preserve the vkd3d compatibility route for RDNA3 and expose explicit route overrides and diagnostics. Improve Windows runtime compatibility: - Retry rejected application-ID initialization with a project identity. - Defer expensive RR backend creation until feature creation. - Recover from transient submission failures without disabling later frames. - Add shared-buffer export fallbacks through explicit heaps and a private device on the same adapter. - Safely evict old RR descriptor sets when input views change. - Treat requested RR presets as hints when a configured model is available. - Expand SR/RR input formats and handle diffuse/specular hit distances, packed normals, depth-stencil resources, and unused FSR guides. Reduce SR overhead by batching output downloads and format conversion under one completion wait. Optimize strict M enc2/tube attention with bounded FP32 accumulation and the original FP64 fallback for ambiguous rounding cases. Extend RDNA4 tooling with gfx1200/gfx1201 native FP8 RR model builds, capability checks, architecture-aware deployment, and experimental K/M kernel paths. Require matching model and runtime arithmetic families. Add optional embedded FSR shader optimizations keyed by shader hash and exact original SPIR-V contents. Preserve reflected metadata and record optimizer provenance, artifact hashes, and cache identity. Simplify Windows installation with automatic backend dependency downloads, download progress and ETA, backed-up absolute OptiScaler library paths, and recovery from interrupted RR model builds. Add build-kernels.bat and a kernels-only build matrix for all eleven registered RDNA targets, with code-object target validation and SHA256 manifests. Expand conversion probes, numerical stress tests, temporal benchmark tooling, installer/deployment tests, and setup documentation. Document synthetic regression and timing results, experimental build options, and remaining RDNA4 hardware validation requirements.
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@@ -85,6 +85,14 @@ __device__ inline void decode(const u8* p, Storage fmt, float* value) {
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case r32f: value[0] = singles[0]; break;
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case depth24: value[0] = float(*reinterpret_cast<const u32*>(p) & 0xffffffu) / 16777215.f; break;
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case r16unorm: value[0] = float(halves[0]) / 65535.f; break;
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case rgb9e5: {
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// Microsoft spec: c = (p >> offset) & 0x1FF, E = p >> 27, v = c * 2^(E - 24);
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// no implicit leading bit. 2^(E - 24) is a normal float for every E.
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u32 packed = *reinterpret_cast<const u32*>(p);
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const float scale = as_float(((packed >> 27) + 103u) << 23);
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for (unsigned i = 0; i < 3; ++i) value[i] = float((packed >> (9 * i)) & 511u) * scale;
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break;
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}
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default: break; // Host rejects formats which have no tested decoder.
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}
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}
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@@ -103,6 +111,20 @@ __device__ inline void encode(u8* p, Storage fmt, const float* value) {
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case rgb10a2:
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*reinterpret_cast<u32*>(p) = quantize(value[0], 1023) | (quantize(value[1], 1023) << 10) |
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(quantize(value[2], 1023) << 20) | (quantize(value[3], 3) << 30); break;
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case rgb9e5: {
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// Shared exponent from the largest channel (D3D11.3 spec 3.2.2): negative and
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// NaN clamp to 0, the maximum is (511/512) * 2^16.
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float c[3];
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for (unsigned i = 0; i < 3; ++i) c[i] = value[i] > 0 ? (value[i] < 65408.f ? value[i] : 65408.f) : 0.f;
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float largest = c[0] > c[1] ? c[0] : c[1]; largest = largest > c[2] ? largest : c[2];
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int floorLog2 = int((as_uint(largest) >> 23) & 255u) - 127;
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int shared = (floorLog2 < -16 ? -16 : floorLog2) + 16; // biased exponent, 0..31
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float step = as_float(u32(shared - 24 + 127) << 23); // 2^(shared - 24)
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if (u32(largest / step + .5f) == 512u) { ++shared; step *= 2.f; }
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u32 packed = u32(shared) << 27;
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for (unsigned i = 0; i < 3; ++i) packed |= (u32(c[i] / step + .5f) & 511u) << (9 * i);
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*reinterpret_cast<u32*>(p) = packed; break;
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}
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default: break; // Only color/output formats are encoded in the runtime.
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}
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}
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