Expand Windows GPU support, add native FSR RR, and improve SR interop

Add a native D3D12 FSR Ray Regeneration route for gfx1200/gfx1201,
using the game's device and queue with embedded HLSL guide preparation
and output composition. Preserve the vkd3d compatibility route for
RDNA3 and expose explicit route overrides and diagnostics.

Improve Windows runtime compatibility:
- Retry rejected application-ID initialization with a project identity.
- Defer expensive RR backend creation until feature creation.
- Recover from transient submission failures without disabling later frames.
- Add shared-buffer export fallbacks through explicit heaps and a private
  device on the same adapter.
- Safely evict old RR descriptor sets when input views change.
- Treat requested RR presets as hints when a configured model is available.
- Expand SR/RR input formats and handle diffuse/specular hit distances,
  packed normals, depth-stencil resources, and unused FSR guides.

Reduce SR overhead by batching output downloads and format conversion
under one completion wait. Optimize strict M enc2/tube attention with
bounded FP32 accumulation and the original FP64 fallback for ambiguous
rounding cases.

Extend RDNA4 tooling with gfx1200/gfx1201 native FP8 RR model builds,
capability checks, architecture-aware deployment, and experimental K/M
kernel paths. Require matching model and runtime arithmetic families.

Add optional embedded FSR shader optimizations keyed by shader hash and
exact original SPIR-V contents. Preserve reflected metadata and record
optimizer provenance, artifact hashes, and cache identity.

Simplify Windows installation with automatic backend dependency downloads,
download progress and ETA, backed-up absolute OptiScaler library paths,
and recovery from interrupted RR model builds.

Add build-kernels.bat and a kernels-only build matrix for all eleven
registered RDNA targets, with code-object target validation and SHA256
manifests. Expand conversion probes, numerical stress tests, temporal
benchmark tooling, installer/deployment tests, and setup documentation.

Document synthetic regression and timing results, experimental build
options, and remaining RDNA4 hardware validation requirements.

tools/windows/exact_pv_probe.hip

@@ -0,0 +1,45 @@
+// Stress the bounded FP32 path against the original sequential FP64 dot.
+#define SWIN_BOUNDED_PV
+#include "../../kernels/m/swin_common.h"
+struct PvParams { uint32_t* output; };
+__device__ uint32_t pv_random(uint32_t& state) {
+    state ^= state << 13; state ^= state >> 17; state ^= state << 5;
+    return state;
+}
+extern "C" __global__ void exact_pv_probe(PvParams p) {
+    const unsigned index = blockIdx.x * 32 + threadIdx.x;
+    uint32_t state = index + 1;
+    half_t a[16], b[16];
+    for (int k = 0; k < 16; ++k) {
+        uint16_t x = pv_random(state), y = pv_random(state);
+        x = (x & 0x8000u) | ((x & 0x7fffu) % 0x7c00u);
+        y = (y & 0x8000u) | ((y & 0x7fffu) % 0x7c00u);
+        a[k] = __builtin_bit_cast(half_t, x);
+        b[k] = __builtin_bit_cast(half_t, y);
+    }
+    switch (index % 4) {
+        case 0: break; // Entire finite FP16 exponent range, signed products.
+        case 1: // Cancellation, including products too small for an FP32 sum.
+            for (int k = 0; k < 8; ++k) { a[k + 8] = -a[k]; b[k + 8] = b[k]; }
+            b[15] = (half_t)0.0f;
+            break;
+        case 2: // Every finite magnitude with exact midpoint perturbations.
+        case 3:
+            for (int k = 0; k < 16; ++k) { a[k] = (half_t)0.0f; b[k] = (half_t)1.0f; }
+            a[0] = __builtin_bit_cast(half_t, (uint16_t)((index / 4) % 0x7c00u));
+            {
+                const uint16_t bits = __builtin_bit_cast(uint16_t, a[0]);
+                const half_t next = __builtin_bit_cast(half_t, (uint16_t)(bits + (bits < 0x7bffu)));
+                a[1] = (half_t)((float)next - (float)a[0]);
+            }
+            b[1] = (half_t)0.5f;
+            a[2] = __builtin_bit_cast(half_t, (uint16_t)1);
+            b[2] = __builtin_bit_cast(half_t, (uint16_t)((index & 1) ? 0x8001u : 1u));
+            break;
+    }
+    double reference = 0.0;
+    for (int k = 0; k < 16; ++k) reference += (double)a[k] * (double)b[k];
+    const uint16_t expected = __builtin_bit_cast(uint16_t, (half_t)reference);
+    const uint16_t actual = __builtin_bit_cast(uint16_t, exact_pv_dot<1>(a, b));
+    p.output[index] = uint32_t(expected) | (uint32_t(actual) << 16);
+}