engine/rr: native preset F (DLSS 4.5 Ray Reconstruction) and the reference's fused roundings
- engine/compile_rr2.py, runtime_rr2.inc, engine/rr/rr2_m.comp, exposure_f.comp, gen_rr2_enc0.py, rr2_pack.py, rr2_ref.py: the rr2_* model (nvngx_dlssd.dll 310.9's third network) as d4r's own shaders - exposure, enc0 gather/block split, enc1-5 and dec4-0 through one matrix shader, translated output passes; weights packed from the DLL, argument blocks from the capture - ptx2rr: match the driver's fused roundings - opaque-zero OR around cvt.rn.f16.f32 against v_fma_mix, half-away-from-zero formatted stores, UNORM 10:10:10:2 as RGBA32F of q/1023, OCML tanhF with the AMDGPU exp lowering, binary16 fma and fetch roundings; --probe for register bisection against ZLUDA - dec0_m/swin_m/enc0_*: RR_MIX build option (D4R_RR_MIX=1), one v_fma_mix rounding per 32-deep step, ~5% faster, not bit-exact; default build stays exact - runtime_rr.inc: RModel/REngine dispatch to the D4RR0002 model; replay_rr: RGBA32F and A2B10G10R1010 texel sizes, roughnessPacked bit, larger debug staging - shim: engine\rr-f model slot, 310.9 version probe so preset F is only claimed when the CUDA path has it; d4r.ini / d4r_config.py Model = F; run_rr_engine_compare.sh D4R_RR_DLL - kernels/rr/swin_native.h + rr_swin_native_test.cpp: HIP port of encoder 1 for the FP8-product and rounding cost measurements - engine/rr/README: preset F's block, options, capture-by-capture results, timings and the open camera-matrix difference
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@@ -48,7 +48,23 @@ layout(set = 0, binding = 7, rgba8_snorm) uniform writeonly image2D S144;
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#define LDB(dst, base, n, kt, nt) coopMatLoad((dst), w8.w, (base) + 256u * ((kt) * ((n) / 16u) + (nt)), 16u, RM)
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#define RND(m) [[unroll]] for (int i_ = 0; i_ < 8; ++i_) (m)[i_] = rnd16((m)[i_]);
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#define Q8(dst, src) Q8PAIRS(dst, src)
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// One 32-deep step onto an accumulator that holds binary16 values. The reference (and the default here) adds the
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// accumulator inside the f32 products and rounds the result to binary16. RR_MIX (build_native_model.sh with
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// D4R_RR_MIX=1) keeps the accumulator as binary16, sums the products from zero and takes f16(P + acc), which the
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// driver compiles to one v_fma_mix per element in place of two conversions: about 5% faster, but a single rounding
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// where the reference has two, so a value can come out one binary16 step away (engine/rr/README.md).
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// RAC is the accumulator type, RV(x) a binary16 value as its element; K32H is the step on a binary16 matrix.
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#ifdef RR_MIX
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#define RAC HAC
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#define RV(x) (x)
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#define K32(acc, a0, b0, a1, b1) { ACC p_ = coopMatMulAdd((a1), (b1), coopMatMulAdd((a0), (b0), ACC(0.0))); [[unroll]] for (int i_ = 0; i_ < 8; ++i_) (acc)[i_] = float16_t(p_[i_] + float((acc)[i_])); }
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#define K32H(acc, a0, b0, a1, b1) K32(acc, a0, b0, a1, b1)
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#else
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#define RAC ACC
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#define RV(x) float(x)
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#define K32(acc, a0, b0, a1, b1) { (acc) = coopMatMulAdd((a1), (b1), coopMatMulAdd((a0), (b0), (acc))); RND(acc) }
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#define K32H(acc, a0, b0, a1, b1) { ACC p_ = coopMatMulAdd((a1), (b1), coopMatMulAdd((a0), (b0), ACC(acc))); [[unroll]] for (int i_ = 0; i_ < 8; ++i_) (acc)[i_] = float16_t(p_[i_]); }
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#endif
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const uint HEAD = W_WK1 - W_WK0, BRANCH = W_W1_1 - W_W1_0;
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// shared memory, aliased by phase: expand and prologue [LOW | EX], then the attention [K | V^T]
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@@ -111,8 +127,8 @@ void main()
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[[unroll]] for (uint kt = 0u; kt < 4u; ++kt) coopMatLoad(lb[kt], LOW, n * 256u + 4u * kt, 16u, CM);
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[[unroll]] for (uint mm = 0u; mm < 2u; ++mm) {
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const uint m = 2u * wv + mm;
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ACC a;
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[[unroll]] for (int i = 0; i < 8; ++i) a[i] = float(w16.w[W_BE / 2u + 16u * m + 8u * hl + uint(i)]);
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RAC a;
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[[unroll]] for (int i = 0; i < 8; ++i) a[i] = RV(w16.w[W_BE / 2u + 16u * m + 8u * hl + uint(i)]);
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K32(a, we[mm][0], lb[0], we[mm][1], lb[1])
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K32(a, we[mm][2], lb[2], we[mm][3], lb[3])
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B8 q;
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@@ -167,13 +183,13 @@ void main()
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barrier();
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// ---------------------------------------------------------------- the residual: window tokens + table 0
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ACC R[2];
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RAC R[2];
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[[unroll]] for (uint m = 0u; m < 2u; ++m) {
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HAC x;
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coopMatLoad(x, XR, wv * 512u + 16u * m, 32u, CM);
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[[unroll]] for (int i = 0; i < 8; ++i) {
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precise float16_t c = float16_t(x[i]) + w16.w[W_TABLE0 / 2u + 16u * m + 8u * hl + uint(i)];
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R[m][i] = float(c);
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R[m][i] = RV(c);
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}
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}
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@@ -190,12 +206,12 @@ void main()
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LDA(wk[kt], W_WK0 + HEAD * hd, 32u, c, kt);
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LDB(wvb[kt], W_WV0 + HEAD * hd, 32u, kt, c);
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}
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ACC a = ACC(0.0);
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RAC a = RAC(RV(float16_t(0.0)));
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K32(a, wk[0], xb[0], wk[1], xb[1])
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A8 ka;
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Q8(ka, a)
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coopMatStore(ka, POOL, n * 128u + 4u * c, 8u, RM);
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ACC v = ACC(0.0);
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RAC v = RAC(RV(float16_t(0.0)));
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K32(v, xa[0], wvb[0], xa[1], wvb[1])
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A8 va;
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Q8(va, v)
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@@ -241,15 +257,15 @@ void main()
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precise float16_t n = rv[m][i] * g;
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Nb[m][i] = q8h(n);
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precise float16_t a = rv[m][i] + w16.w[W_TABLE1 / 2u + k];
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R[m][i] = float(a);
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R[m][i] = RV(a);
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}
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}
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for (uint br = 0u; br < 4u; ++br) {
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const uint w1 = W_W1_0 + BRANCH * br, b1 = W_B1_0 + BRANCH * br, w2 = W_W2_0 + BRANCH * br;
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B8 Hb[2];
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[[unroll]] for (uint c = 0u; c < 2u; ++c) {
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ACC h;
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[[unroll]] for (int i = 0; i < 8; ++i) h[i] = float(w16.w[b1 / 2u + 16u * c + 8u * hl + uint(i)]);
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RAC h;
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[[unroll]] for (int i = 0; i < 8; ++i) h[i] = RV(w16.w[b1 / 2u + 16u * c + 8u * hl + uint(i)]);
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A8 a0, a1;
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LDA(a0, w1, 32u, c, 0u); LDA(a1, w1, 32u, c, 1u);
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K32(h, a0, Nb[0], a1, Nb[1])
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