kernels/tex: native token-lane parts for preset L's enc0 and dec0
L's unfolded enc0 and dec0 are still ZLUDA's compile of NVIDIA's PTX and cost 2.95 ms of the preset's 5.86 ms per frame (RX 9070 XT, 1280x720 -> 4K). The embedding, the patch expand, the Swin block (32 channels, 2 heads, at pixel resolution) and the patch merge are now native token-lane code; the texture work around them stays ZLUDA's compile. enc0l_tail.hip cuts in at the barrier after the feature staging and dec0l_block.hip before the output code that reads the block's f16 result out of the last MMAs; make_ptx.py splices either in when D4R_TEX_SRC names it and build.sh selects both for the gfx12 native-FP8 builds. swin_tex.h carries the indexing the two tails share; swin_tok.h gains the pixel-order token layout (SWIN_TOK_NATURAL), ZLUDA's attention key order (SWIN_PV_ZLUDA_ORDER) and swin_tok_core, which the encoded tests reuse. swin_common.h takes the block weight layout (moved out of swin_block.h) and the exact and approximate reciprocal / mix forms the tails need without the HIP headers (D4R_NO_HIP_RUNTIME). The f32 sums stay in ZLUDA's order (K slots of the FP8 WMMAs, key order of the f16 attention product) and rsqrt/rcp use the hardware approximations ZLUDA lowers to, so the harness's final frame is byte-identical to the translated kernels: all four enc0 flag variants, 720p and 1080p render, 1440p and 4K output, static and moving scenes, 100 frames, and the accuracy set. With M's own sum order about one token in 20,000 differed. M's layers compile to the same instructions and its frame is byte-identical. enc0 1.69 -> 0.63 ms and dec0 1.26 -> 0.54 ms at 720p->4K, 2.73 -> 1.16 and 2.28 -> 1.01 at 1080p->4K; the preset 5.83 -> 4.06 and 8.63 -> 5.69 ms. -DD4R_SWIN_K32_MIX rounds the f16 products earlier for 0.56 and 0.49 ms and is not byte-identical, so it is not built by default. The repo's tests pass (36, 3 skipped).
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// Native block of preset L's unfolded rrlite_dec0_4x4, RDNA4 native FP8 only.
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//
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// The original kernel is, per 8x8-pixel block (one wave): the patch expand of the block's 16 half-resolution
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// tokens (K 64 -> 4 x 32 channels), x0 = f16(q8(expand) + skip) with enc0's pixel tokens as the skip input, a
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// Swin block (C 32, 2 heads, 4x4 windows), and output code that turns the block's f16 result into four surfaces.
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// make_ptx.py keeps the output code as ZLUDA's compile of the PTX and replaces everything before it with a call
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// of d4r_dec0l_block. The function leaves the block's result in shared memory in the register layout the
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// output code reads (the D fragments of NVIDIA's last 16 MMAs), which the edited PTX loads back.
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// The arithmetic is the token-lane block of ../m/swin_tok.h in the order of ZLUDA's lowering (see
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// enc0l_tail.hip): harness frames are byte-identical to the original kernel's.
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#include "tex_common.h"
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#if !defined(D4R_TEX_FP8) || D4R_WMMA_LAYOUT != 12
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#error "dec0l_block.hip needs the gfx12 native-FP8 build (D4R_TEX_FP8=1)"
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#endif
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#include "swin_tex.h"
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namespace
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{
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using namespace d4r_swin;
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constexpr int DC = 32, DNH = 2, DCIN = 64, DNT = DC / 16;
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using DL = TokLayout<DC, DNH, 0, DCIN>;
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constexpr TokTables<DC, DNH, 0, DCIN> g_dl_tok = make_tok_tables<DC, DNH, 0, DCIN>();
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} // namespace
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__attribute__((device)) d4r_swin::wslot g_dl_w16[DL::TOTAL];
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__attribute__((device)) d4r_swin::h8 g_dl_c16[DL::CTOTAL];
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DEV __attribute__((used)) uint32_t d4r_prep_blocks = ((DL::TOTAL > DL::CTOTAL ? DL::TOTAL : DL::CTOTAL) + 127) / 128;
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// the prep reads only prm.w (offset 0): the hook skips it while that pointer repeats
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DEV __attribute__((used)) uint32_t d4r_prep_key_at = 0 + 1;
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struct Dec0LParams
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{
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uint64_t w;
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uint8_t rest[160]; // 168-byte parameter block
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};
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KERNEL __attribute__((amdgpu_flat_work_group_size(128, 128))) void rrlite_dec0_4x4_prep(Dec0LParams prm)
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{
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const int idx = (int)(__builtin_amdgcn_workgroup_id_x() * 128 + __builtin_amdgcn_workitem_id_x());
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const uint8_t* w = (const uint8_t*)prm.w;
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if (idx == 0)
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d4r_swin_one = (float)(prm.w != 0);
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if (idx < DL::TOTAL)
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expand_tok_weights(w, g_dl_w16, g_dl_tok.d, DL::NDESC, idx);
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if (idx < DL::CTOTAL)
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expand_tok_consts(w, g_dl_c16, g_dl_tok.c, DL::NCONST, idx);
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}
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// in: e4m3 planes of 32 channels (two) over tw / 2 x th / 2 tokens; skip: one such plane over tw x th tokens
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// (pixels). (sx, sy): offset of the block grid against the token grid; (bx, by): this block.
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// Returns the shared-memory address of the result image: register R = 2 (4 m + j) + h of lane L (4 bytes at
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// 4 (32 R + L)) is D register h of NVIDIA's MMA for token tile m (window) and column tile j, i.e. rows
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// 16 m + (L >> 2) + 8 h, pair-order columns 8 j + 2 (L & 3), + 1 of the block's f16 output.
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DEV uint32_t d4r_dec0l_block(uint64_t wp, uint64_t inp, uint64_t skipp, int32_t sx, int32_t sy, int32_t tw, int32_t th,
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int32_t bx, int32_t by)
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{
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using K = DL;
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constexpr int C = DC, NT = DNT, CIN = DCIN;
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const int lane = (int)lane_id(), l16 = lane & 15, hf = lane >> 4;
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(void)wp; // the images were prepared from it
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uintptr_t chv = (uintptr_t)(g_dl_c16 + hf), wlv = (uintptr_t)((const gop*)g_dl_w16 + 2 * l16 + hf);
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asm("" : "+v"(chv));
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asm("" : "+v"(wlv));
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const h8* const ch = (const h8*)chv;
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const gop* const wl = (const gop*)wlv;
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auto wt = [&](int dst, int nt_count, int kc, int st, int nt) { return wl[2 * (dst + ((kc * 2 + st) * nt_count + nt) * 16)]; };
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__shared__ __attribute__((aligned(16))) uint8_t E8[64 * C];
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__shared__ __attribute__((aligned(16))) uint32_t X2[32 * 32];
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// patch expand: lanes = the block's 16 half-resolution tokens, one sub-position (quadrant) after the other;
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// the codes of q8(expand) go to their child tokens' rows of E8 (as swin_tok_block, which uses a wave each)
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{
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const int W2 = tw / 2, H2 = th / 2;
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const int MX = mirror((8 * bx - sx) / 2 + (l16 & 3), W2), MY = mirror((8 * by - sy) / 2 + (l16 >> 2), H2);
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gop pa[CIN / 32][2];
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#pragma unroll
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for (int kc = 0; kc < CIN / 32; ++kc)
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{
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const uint8_t* b = (const uint8_t*)inp + ((size_t)(kc * H2 + MY) * W2 + MX) * 32 + tok_half(hf);
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#pragma unroll
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for (int st = 0; st < 2; ++st)
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pa[kc][st] = (u2v){*(const uint32_t*)(b + tok_word(st, 0)), *(const uint32_t*)(b + tok_word(st, 1))};
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}
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#pragma unroll 1
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for (int q = 0; q < 4; ++q)
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{
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const int tx = 2 * (l16 & 3) + (q & 1), ty = 2 * (l16 >> 2) + (q >> 1);
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const int Tc = (tx & 3) + 4 * (ty & 3) + 16 * (tx >> 2) + 32 * (ty >> 2);
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const int pew = K::pe(0) + q * (CIN * C / 16);
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#pragma unroll
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for (int ct = 0; ct < NT; ++ct)
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{
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T16 e = tok_t16(ch[K::CPEB + 2 * (NT * q + ct)]);
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#pragma unroll
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for (int kc = 0; kc < CIN / 32; ++kc)
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k32(e, wt(pew, NT, kc, 0, ct), pa[kc][0], wt(pew, NT, kc, 1, ct), pa[kc][1]);
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*(u2v*)(E8 + Tc * C + 16 * ct + 8 * hf) = tok_codes(e);
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}
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}
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}
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wave_sync();
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#pragma unroll 1
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for (int wv = 0; wv < 4; ++wv)
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{
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const int T = 16 * wv + l16;
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const int Xm = mirror(8 * bx - sx + tok_x(T), tw), Ym = mirror(8 * by - sy + tok_y(T), th);
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const uint8_t* const sb = (const uint8_t*)skipp + ((size_t)Ym * (size_t)tw + (size_t)Xm) * 32 + tok_half(hf);
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hv2 v[NT][4];
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#pragma unroll
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for (int t = 0; t < NT; ++t)
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#pragma unroll
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for (int g = 0; g < 2; ++g)
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{
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const uint32_t ew = *(const uint32_t*)(E8 + T * C + tok_word(t, g) + tok_half(hf));
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const uint32_t sw = *(const uint32_t*)(sb + tok_word(t, g));
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v[t][2 * g] = tok_dec2<false>(ew) + tok_dec2<false>(sw);
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v[t][2 * g + 1] = tok_dec2<true>(ew) + tok_dec2<true>(sw);
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}
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uint32_t co[NT][2];
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hv2 x2[NT][4];
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swin_tok_core<DC, DNH, 0, DCIN>(ch, wl, l16, v, co, x2);
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(void)co;
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// pair k of tile t holds natural channels 16 t + 8 half + 2 k, + 1: pair-order columns 8 j + 2 u, + 1 with
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// j = t + 2 (k & 1), u = 2 half + (k >> 1); token row l16 of tile wv
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#pragma unroll
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for (int t = 0; t < NT; ++t)
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#pragma unroll
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for (int k = 0; k < 4; ++k)
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{
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const int R = 2 * (4 * wv + t + 2 * (k & 1)) + (l16 >> 3), L = 4 * (l16 & 7) + 2 * hf + (k >> 1);
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X2[32 * R + L] = __builtin_bit_cast(uint32_t, x2[t][k]);
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}
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}
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wave_sync();
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return (uint32_t)(uintptr_t)(__attribute__((address_space(3))) void*)X2;
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}
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