kernels/tex: native token-lane parts for preset L's enc0 and dec0

L's unfolded enc0 and dec0 are still ZLUDA's compile of NVIDIA's PTX and cost
2.95 ms of the preset's 5.86 ms per frame (RX 9070 XT, 1280x720 -> 4K). The
embedding, the patch expand, the Swin block (32 channels, 2 heads, at pixel
resolution) and the patch merge are now native token-lane code; the texture
work around them stays ZLUDA's compile.

enc0l_tail.hip cuts in at the barrier after the feature staging and dec0l_block.hip
before the output code that reads the block's f16 result out of the last MMAs; make_ptx.py
splices either in when D4R_TEX_SRC names it and build.sh selects both for the gfx12
native-FP8 builds. swin_tex.h carries the indexing the two tails share; swin_tok.h gains
the pixel-order token layout (SWIN_TOK_NATURAL), ZLUDA's attention key order
(SWIN_PV_ZLUDA_ORDER) and swin_tok_core, which the encoded tests reuse. swin_common.h
takes the block weight layout (moved out of swin_block.h) and the exact and approximate
reciprocal / mix forms the tails need without the HIP headers (D4R_NO_HIP_RUNTIME).

The f32 sums stay in ZLUDA's order (K slots of the FP8 WMMAs, key order of the f16
attention product) and rsqrt/rcp use the hardware approximations ZLUDA lowers to, so the
harness's final frame is byte-identical to the translated kernels: all four enc0 flag
variants, 720p and 1080p render, 1440p and 4K output, static and moving scenes, 100
frames, and the accuracy set. With M's own sum order about one token in 20,000 differed.
M's layers compile to the same instructions and its frame is byte-identical.

enc0 1.69 -> 0.63 ms and dec0 1.26 -> 0.54 ms at 720p->4K, 2.73 -> 1.16 and 2.28 -> 1.01
at 1080p->4K; the preset 5.83 -> 4.06 and 8.63 -> 5.69 ms. -DD4R_SWIN_K32_MIX rounds the
f16 products earlier for 0.56 and 0.49 ms and is not byte-identical, so it is not built by
default. The repo's tests pass (36, 3 skipped).

kernels/m/swin_block.h

@@ -9,32 +9,6 @@
 #define SWIN_PRAGMA_IMPL(x) _Pragma(#x)
 #define SWIN_PRAGMA(x) SWIN_PRAGMA_IMPL(x)
 
-template <int C, int NW, int NPM, int CIN = 0> struct SwinLayout
-{
-    static constexpr int PREB = CIN ? 4 * C * CIN + 8 * C : 0; // patch-expand weights + bias first
-    static constexpr int NTE = CIN ? 4 * C / NW / 16 : 0;
-    static constexpr int NPL = C / 32, NT = C / 16, NT8 = C / 8, INNER = 32 * NW, NC = C / 8;
-    static constexpr int HS = 96 * C + 512;
-    static constexpr int G1 = PREB, E = PREB + 2 * C + NW * HS, BO = E, G2 = E + 2 * C, M0 = E + 4 * C;
-    static constexpr int B2 = M0 + 64 * C + 64;
-    __host__ __device__ static constexpr int head(int h) { return PREB + 2 * C + HS * h; }
-    __host__ __device__ static constexpr int b1(int c) { return c == 0 ? M0 : M0 + 66 * C + 64 + (64 * C + 64) * (c - 1); }
-    static constexpr int PM0 = M0 + 66 * C + 64 + (64 * C + 64) * (NC - 1);
-    static constexpr int PMB = PM0 + 4 * C * NPM;
-    // weight image (slots of 16 K values, see expand_weights)
-    __host__ __device__ static constexpr int qv(int h, int q) { return (2 * h + q) * 2 * C; }
-    static constexpr int WO = 4 * C * NW;
-    static constexpr int W1 = WO + 2 * NW * C;
-    __host__ __device__ static constexpr int w1(int c) { return W1 + 4 * C * c; }
-    __host__ __device__ static constexpr int w2(int c) { return W1 + 4 * C * c + 2 * C; }
-    static constexpr int PM = W1 + 4 * C * NC;
-    __host__ __device__ static constexpr int pm(int g) { return PM + 8 * C * g; }
-    static constexpr int PE = PM + (NPM / 32) * 8 * C;
-    __host__ __device__ static constexpr int pe(int w) { return PE + w * (CIN / 32) * 2 * NTE * 16; }
-    static constexpr int TOTAL = PE + (CIN ? NW * (CIN / 32) * 2 * NTE * 16 : 0);
-    static constexpr int NDESC = 2 * NW + 1 + 2 * NC + NPM / 32 + (CIN ? NW : 0);
-};
-
 // Start (in halves) of token T's row in the output staging buffer: stride C + 4 plus a shift by bits 4 and 5
 // of T. The patch merge's lanes read 8 bytes each from 16 tokens that differ in bits 1, 3, 4 and 5 (plus a
 // constant); this placement puts those 16 reads on 16 distinct 8-byte bank pairs for C = 64, 96 and 128.