feat: add d4r inference engines and Windows parity tooling
Add native K/M/RR inference engines, HIP kernels, replay and validation harnesses, and Windows DLSS setup and runtime support. Include GPU profiling tools, build and packaging scripts, platform integration patches, and implementation documentation.
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// Native kernels (gfx11 / gfx12 wave32 WMMA) for the DLSS 4 (preset K) DltssPaddedWinLayer blocks.
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// Semantics: kernels/tools/pwin_model.py (verified against the PTX interpreter, kernels/tools/ptxsim.py).
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//
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// Layout conventions (transposed WMMA, as in the preset M kernels): a GEMM Y = X W is computed as
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// Y^T = W^T X^T with the weights as the WMMA A operand (lane l: output channel l & 15) and the activations
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// as the B operand (lane l: token l & 15). The f32 result then has lane l = token l & 15 and VGPR i =
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// output channel wm_acc_row(i) of the 16-channel tile ("D^T"); ../common/wmma_layout.h has the per-target
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// register layouts (gfx11: channel 2i + (l >> 4); gfx12: channel i + 8 (l >> 4)).
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#pragma once
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#ifdef D4R_DEVICE_ONLY_MINIMAL
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#include "../common/hip_device_minimal.h"
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#else
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#include <hip/hip_runtime.h>
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#endif
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#include <stdint.h>
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#include "../common/wmma_layout.h"
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#if defined(D4R_ACCURACY) && defined(PWIN_F32ACC)
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#undef PWIN_F32ACC
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#endif
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#pragma clang fp contract(off)
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// LDS row padding in halves (port of the K-race research): activation rows of N halves are stored N + PWIN_PAD
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// apart so the 16 token rows a WMMA operand load touches start on distinct banks. Layout only; values unchanged.
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#ifndef PWIN_PAD
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#define PWIN_PAD 8
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#endif
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#define LDSR(N) ((N) + PWIN_PAD)
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typedef _Float16 half_t;
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typedef _Float16 hv2 __attribute__((ext_vector_type(2)));
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typedef _Float16 h16 __attribute__((ext_vector_type(16)));
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typedef float f8v __attribute__((ext_vector_type(8)));
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#ifdef D4R_K_PACKED_ACC
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#if !defined(__GFX12__) || !defined(D4R_K_FP16_BASELINE) || defined(D4R_K_F16_WMMA)
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#error "packed accumulator storage requires gfx12 strict F32 WMMA baseline"
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#endif
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// Keep already-rounded values packed between steps. Every matrix instruction
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// still uses F32 C/D and rounds once to half afterwards, like the baseline.
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typedef _Float16 acc8v __attribute__((ext_vector_type(8)));
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#else
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typedef f8v acc8v;
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#endif
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typedef uint32_t u8v __attribute__((ext_vector_type(8)));
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typedef uint32_t u4v __attribute__((ext_vector_type(4)));
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__device__ __forceinline__ uint32_t lane_id()
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{
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return __builtin_amdgcn_mbcnt_lo(~0u, 0u);
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}
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typedef wm_op op_t; // WMMA operand: u8v (gfx11) or u4v (gfx12)
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// The CUDA fragment reduction rounds products and every tree node to f16.
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// A float sum of the squared halves changes rsqrt and can amplify differences
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// through attention. The strict baseline preserves its channel grouping.
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template <int C>
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__device__ __forceinline__ half_t l2_sum(const half_t* row)
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{
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#ifdef D4R_K_FP16_BASELINE
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static_assert(C % 32 == 0 && C <= 160, "audited K channel counts");
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hv2 partial[4];
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#pragma unroll
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for (int t = 0; t < 4; ++t)
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{
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hv2 halves[2];
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#pragma unroll
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for (int parity = 0; parity < 2; ++parity)
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{
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hv2 pairs[C / 32];
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#pragma unroll
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for (int group = 0; group < C / 32; ++group)
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{
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const hv2 a = *(const hv2*)(row + 2 * t + 8 * parity + 32 * group);
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const hv2 b = *(const hv2*)(row + 2 * t + 8 * parity + 32 * group + 16);
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pairs[group] = (a * a) + (b * b);
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}
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hv2 value = pairs[0];
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if constexpr (C >= 64) value = value + pairs[1];
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if constexpr (C == 96) value = value + pairs[2];
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if constexpr (C >= 128) value = value + (pairs[2] + pairs[3]);
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if constexpr (C == 160) value = value + pairs[4];
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halves[parity] = value;
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}
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partial[t] = halves[0] + halves[1];
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}
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const hv2 sum = (partial[0] + partial[1]) + (partial[2] + partial[3]);
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return sum[0] + sum[1];
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#else
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float sum = 0;
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#pragma unroll
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for (int c = 0; c < C; ++c) sum += (float)(half_t)(row[c] * row[c]);
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return (half_t)sum;
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#endif
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}
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// one k16 step with the f16 accumulator of NVIDIA's f16 wmma (rounded after the step)
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// PWIN_F32ACC: keep the accumulator in f32 through the chain (rounded to f16 where the values are used)
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__device__ __forceinline__ acc8v mma16(const op_t& a, const op_t& b, acc8v c)
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{
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#ifdef D4R_K_PACKED_ACC
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const f8v fc = __builtin_convertvector(c, f8v);
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const f8v d = wm_mma(a, b, fc);
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return __builtin_convertvector(d, acc8v);
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#elif defined(D4R_K_F16_WMMA)
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#if !defined(__GFX12__) || D4R_WMMA_LAYOUT != 12 || !defined(D4R_K_FP16_BASELINE)
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#error "experimental packed F16 WMMA requires gfx12 native layout and strict K baseline"
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#endif
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return wm_mma_f16_step(a, b, c);
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#else
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f8v d = wm_mma(a, b, c);
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#if !defined(PWIN_F32ACC) || defined(D4R_K_FP16_BASELINE)
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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d[i] = (float)(half_t)d[i];
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#endif
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return d;
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#endif
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}
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__device__ __forceinline__ acc8v splat8(float v)
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{
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#ifdef D4R_K_PACKED_ACC
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const half_t h = (half_t)v;
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return (acc8v){h, h, h, h, h, h, h, h};
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#else
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return (acc8v){v, v, v, v, v, v, v, v};
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#endif
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}
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__device__ __forceinline__ uint32_t other_half(uint32_t v)
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{
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return wm_other_half(v);
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}
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__device__ __forceinline__ uint32_t pack2(half_t lo, half_t hi)
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{
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return __builtin_bit_cast(uint32_t, (hv2){lo, hi});
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}
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__device__ __forceinline__ half_t lo16(uint32_t v)
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{
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return __builtin_bit_cast(hv2, v)[0];
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}
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__device__ __forceinline__ half_t hi16(uint32_t v)
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{
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return __builtin_bit_cast(hv2, v)[1];
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}
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// D^T f16 values (own[i] = channel wm_acc_row(i) of token l & 15) -> operand of the same token (the
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// channels become K)
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__device__ __forceinline__ op_t operand_from_dt(const half_t own[8])
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{
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return wm_op_from_acc(own);
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}
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__device__ __forceinline__ op_t operand_from_f8(acc8v d)
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{
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#ifdef D4R_K_PACKED_ACC
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const half_t h[8] = {d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7]};
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return wm_op_from_acc(h);
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#else
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return wm_op_from_f8(d);
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#endif
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}
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// element c (0..15) of a row of 16 halves (VALU code; not a WMMA operand)
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__device__ __forceinline__ half_t op_get(const u8v& v, int c)
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{
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return (c & 1) ? hi16(v[c >> 1]) : lo16(v[c >> 1]);
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}
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__device__ __forceinline__ u8v lds_row16(const half_t* p)
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{
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const u4v a = *(const u4v*)p, b = *(const u4v*)(p + 8);
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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}
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// Global activation traffic (tokens in, rows out): PWIN_NT_LOAD / PWIN_NT_STORE mark it non-temporal so
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// it does not evict the weight images from the caches. Same data either way.
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__device__ __forceinline__ u8v gload_row16(const half_t* p)
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{
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#ifdef PWIN_NT_LOAD
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const u4v a = __builtin_nontemporal_load((const u4v*)p), b = __builtin_nontemporal_load((const u4v*)(p + 8));
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#else
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const u4v a = *(const u4v*)p, b = *(const u4v*)(p + 8);
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#endif
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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}
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__device__ __forceinline__ void gstore16(half_t* p, u4v v)
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{
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#ifdef PWIN_NT_STORE
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__builtin_nontemporal_store(v, (u4v*)p);
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#else
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*(u4v*)p = v;
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#endif
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}
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__device__ __forceinline__ void gstore_row16(half_t* dst, const u8v& v)
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{
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gstore16(dst, (u4v){v[0], v[1], v[2], v[3]});
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gstore16(dst + 8, (u4v){v[4], v[5], v[6], v[7]});
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}
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// WMMA operands from rows of 16 channels: LDS, global (PWIN_NT_LOAD as above), prep images (32-byte slots)
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__device__ __forceinline__ op_t op_lds(const half_t* p)
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{
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return wm_op_load(p);
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}
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__device__ __forceinline__ op_t op_gload(const half_t* p)
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{
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#if D4R_WMMA_LAYOUT == 12
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#ifdef PWIN_NT_LOAD
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return __builtin_nontemporal_load((const u4v*)(p + 8 * wm_half()));
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#else
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return *(const u4v*)(p + 8 * wm_half());
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#endif
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#else
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return gload_row16(p);
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#endif
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}
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__device__ __forceinline__ op_t op_img(const u8v* __restrict__ img, int idx)
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{
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return wm_op_image(img, idx);
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}
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// wave index (threadIdx.z) as a wave-uniform scalar, so op_imgt's tile stays in SGPRs. PWIN_PLAIN_WV: the old
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// per-lane read (with PWIN_NO_IMGT the layer compiles as before the port; enc0/enc4 are faster that way)
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#ifdef PWIN_PLAIN_WV
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#define PWIN_WAVE_INDEX threadIdx.z
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#else
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#define PWIN_WAVE_INDEX __builtin_amdgcn_readfirstlane(threadIdx.z)
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#endif
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// slot (tile, lane l & 15) of an operand image in global memory (port of K-race E14 step 1): the tile is
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// wave-uniform, so the row address stays a scalar base and only the lane indexes it. Reads exactly the slot
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// op_img(img, tile * 16 + m) reads; only the address arithmetic differs. PWIN_NO_IMGT: the old form.
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__device__ __forceinline__ op_t op_imgt(const u8v* __restrict__ img, int tile)
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{
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#ifdef PWIN_NO_IMGT
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return wm_op_image(img, tile * 16 + (lane_id() & 15)); // unsigned sum, exactly the old index expression
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#else
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return wm_op_image(img + 16 * tile, (int)(lane_id() & 15));
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#endif
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}
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// operand -> slot idx of an operand image in LDS (read back with op_img)
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__device__ __forceinline__ void op_img_store(u8v* img, int idx, const op_t& v)
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{
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#if D4R_WMMA_LAYOUT == 12
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((u4v*)img)[2 * idx + wm_half()] = v;
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#else
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if (!wm_half())
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img[idx] = v;
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#endif
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}
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// operand (16 channels of this lane's token) -> row of `count` (8 or 16) channels in global memory, if ok
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__device__ __forceinline__ void op_gstore(half_t* dst, const op_t& v, bool ok, int count = 16)
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{
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#if D4R_WMMA_LAYOUT == 12
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if (ok && (wm_half() == 0 || count >= 16))
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gstore16(dst + 8 * wm_half(), v);
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#else
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if (!wm_half() && ok)
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{
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gstore16(dst, (u4v){v[0], v[1], v[2], v[3]});
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if (count >= 16)
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gstore16(dst + 8, (u4v){v[4], v[5], v[6], v[7]});
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}
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#endif
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}
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// operand -> row of 16 channels in LDS
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__device__ __forceinline__ void op_store(half_t* dst, const op_t& v)
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{
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wm_op_store(dst, v);
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}
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__device__ __forceinline__ void block_sync()
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{
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__syncthreads();
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}
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__device__ __forceinline__ int mirror(int v, int n)
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{
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v = v < 0 ? -v : v;
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return v < 2 * n - 2 - v ? v : 2 * n - 2 - v;
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}
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// ------------------------------------------------ pre-swizzled f16 weight fragments (NVIDIA)
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// logical B[k][n] of one 16x16 fragment (512 bytes)
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__device__ __forceinline__ int frag_offset(int k, int n)
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{
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return 64 * (n & 7) + 16 * ((k & 7) >> 1) + 8 * (n >> 3) + 4 * (k >> 3) + 2 * (k & 1);
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}
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