Add RDNA4 (gfx12) support and a 0.1.2 optimization round

RDNA4 (experimental; untested on RDNA4 hardware)
- kernels/common/wmma_layout.h picks the WMMA operand/accumulator layout
  per target; K (pwin_*) and M (swin_*) index through it, so the same
  sources build for gfx11 and gfx12. D4R_WMMA_LAYOUT=12 on gfx11 is a test
  shim that runs the gfx12 indexing on gfx11 WMMA.

- M can use native e4m3 FP8 WMMA on gfx12 (D4R_NATIVE_FP8=1). Texture
  tails (enc0_tail, dec0_head) get gfx12 f16 and FP8 paths that match
  ZLUDA's gfx12 lowering.

- ZLUDA patch 0007: gfx12 WMMA helpers, optional native FP8 MMA
  (D4R_ZLUDA_WMMA_FP8_NATIVE), a layout override for testing, and an
  architecture argument for d4r_emit. Texture kernels are now compiled
  offline per target through d4r_emit (D4R_ZLUDA_EMIT) instead of on the
  local GPU.

- New d4r.ini option [Kernels] NativeFp8 (default on), wired through the
  shim and d4r_config.py. On gfx12 the bridge serves kernels/<arch>-fp8
  when it is on.

- The bridge picks the KFD GPU with the most SIMDs (so an iGPU is not
  chosen over a discrete GPU); D4R_GPU_ARCH overrides it.

- kernels/build.sh and package_release.sh build gfx1100-gfx1103 and
  gfx1200/gfx1201 (plus -fp8 variants), and D4R_BUNDLE_TEX takes
  per-target folders.

Performance (RDNA3; harness byte-identical unless noted)
- ZLUDA patch 0006: m16n8k8 f16 MMAs on WMMA (E; not bit-exact, 52-55 dB
  per layer, D4R_ZLUDA_WMMA_K8=0 disables it), per-key weight-image slots
  for native prep kernels (d4r_prep_key_at, d4r_prep_key_slots), and
  wave64 builds of MMA-free kernels (D4R_ZLUDA_WAVE64).

- M: packed FP8 encoding, conflict-free patch-merge reads, scalar weight
  loads in enc1, and weight prep once per weight set for the six enc3
  tube blocks.

- K: CU mode for the six non-wide pwin layers.

- Texture kernels: every DLSS flag variant is built natively (24 K output,
  8 M post, 4 M downsample, 4 M enc0), not only Townfall's; post and K
  output run as wave64.

- M direct output: rrlite_downsample_kernel writes the shim's output
  buffer; the shim's default direct-output presets are now 11,13.

Tools
- dump_runner takes the prep grid from d4r_prep_blocks and refuses
  texture/surface dumps.

- New pwin_check.py, swin_check.py, model_enc3.py and tail_check.hip.

Docs: README GPU table and RDNA4 notes, building (patches 0002-0007,
d4r_emit), native-kernels (RDNA4 section), performance (new numbers),
packaging README. Version 0.1.2.

kernels/tex/dec0_head.hip

@@ -6,8 +6,14 @@
 
 // weights as WMMA A images: index ((p * 2 + c) * 2 + h) * 16 + n16 for channel pair p (16p..16p+15),
 // k32 chunk c (input plane), k16 half h
+#if D4R_WMMA_LAYOUT == 12
+__attribute__((device)) kslot g_dec0_w16[8 * 2 * 2 * 16];
+#else
 __attribute__((device)) u8v g_dec0_w16[8 * 2 * 2 * 16];
+#endif
 DEV __attribute__((used)) uint32_t d4r_prep_blocks = 4;
+// the prep reads only prm.w (offset 0): the hook skips it while that pointer repeats
+DEV __attribute__((used)) uint32_t d4r_prep_key_at = 0 + 1;
 
 struct Dec0Params
 {
@@ -27,7 +33,11 @@ KERNEL __attribute__((amdgpu_flat_work_group_size(128, 128))) void rrlite_dec0_4
 #pragma unroll
     for (int j = 0; j < 4; ++j)
         d[j] = *(const uint32_t*)(w + 512 * (2 * p + c) + 16 * (4 * g + j) + 4 * (2 * second + h));
+#if D4R_WMMA_LAYOUT == 12
+    g_dec0_w16[idx] = kslot_from16(d);
+#else
     g_dec0_w16[idx] = operand16(d);
+#endif
 }
 
 __attribute__((device)) static inline uint32_t mirror_clamp(int32_t v, uint32_t full, uint32_t half)
@@ -47,6 +57,58 @@ DEV void d4r_dec0_head(uint32_t smem, uint64_t wp, uint64_t inp, uint32_t dimx,
     const uint32_t Y = mirror_clamp(oy / 2 + (int32_t)(m >> 2), dimy, H2);
     const uint32_t Xc = mirror_clamp(ox / 2 + (int32_t)(m & 3), dimx, W2);
     const uint32_t* in = (const uint32_t*)inp + rowstride * Y + 8 * Xc;
+#if D4R_WMMA_LAYOUT == 12
+    kop X[2][2];
+#pragma unroll
+    for (int c = 0; c < 2; ++c)
+#pragma unroll
+        for (int h = 0; h < 2; ++h)
+            X[c][h] = kop_from8(*(const uint2_t*)(in + plane * c + 4 * h + 2 * hf));
+
+    // E[p]: e4m3 codes of channels 16p + 8hf .. 16p + 8hf + 7
+    uint32_t E[8][2];
+#pragma unroll
+    for (int p = 0; p < 8; ++p)
+    {
+        f8v cf;
+#pragma unroll
+        for (int i = 0; i < 8; ++i)
+            cf[i] = (float)*(const half_t*)(w + 8192 + 2 * (16 * p + i + 8 * hf));
+        half_t acc[8];
+#pragma unroll
+        for (int c = 0; c < 2; ++c)
+        {
+            const int slot = ((p * 2 + c) * 2) * 16 + m;
+            cf = k32_e4m3(cf, kop_image(g_dec0_w16, slot), X[c][0], kop_image(g_dec0_w16, slot + 16), X[c][1]);
+#pragma unroll
+            for (int i = 0; i < 8; ++i)
+                acc[i] = (half_t)cf[i];
+#pragma unroll
+            for (int i = 0; i < 8; ++i)
+                cf[i] = (float)acc[i];
+        }
+        uint32_t codes[4];
+#pragma unroll
+        for (int k = 0; k < 4; ++k)
+            codes[k] = e4m3x2(pack2(acc[2 * k], acc[2 * k + 1]));
+        E[p][0] = codes[0] | (codes[1] << 16);
+        E[p][1] = codes[2] | (codes[3] << 16);
+    }
+
+    // staging (layout as below): this lane holds tiles 4G + hf and 4G + 2 + hf (channels 16p + 8hf ..), so it
+    // writes H = hf itself
+    const uint32_t base = 1024 * hf + 32 * (m & 3) + 256 * (m >> 2);
+    const uint32_t goff[4] = {0, 16, 128, 144};
+#pragma unroll
+    for (int G = 0; G < 4; ++G)
+    {
+        const uint32_t* p0 = E[2 * G];
+        const uint32_t* p1 = E[2 * G + 1];
+        u4v words = {__builtin_amdgcn_perm(p1[0], p0[0], 0x05040100u), __builtin_amdgcn_perm(p1[0], p0[0], 0x07060302u),
+                     __builtin_amdgcn_perm(p1[1], p0[1], 0x05040100u), __builtin_amdgcn_perm(p1[1], p0[1], 0x07060302u)};
+        *(__attribute__((address_space(3))) u4v*)(s + base + goff[G]) = words;
+    }
+#else
     u8v X[2][2];
 #pragma unroll
     for (int c = 0; c < 2; ++c)
@@ -109,4 +171,5 @@ DEV void d4r_dec0_head(uint32_t smem, uint64_t wp, uint64_t inp, uint32_t dimx,
                      __builtin_amdgcn_perm(b23, a23, 0x05040100u), __builtin_amdgcn_perm(b23, a23, 0x07060302u)};
         *(__attribute__((address_space(3))) u4v*)(s + base + goff[G]) = words;
     }
+#endif
 }