zluda: renumber the RR patches to 0009-0013

0008 was already taken by 0008-native-post-phase-kernels.patch, so the five
patches that follow it in the build order shift up by one: ray-reconstruction
PTX support, native-FP8 conversion, packed FP8 operands, shadow-store
coalescing and signed FP8 conversion. The patches themselves are unchanged;
only their numbers and the references in README.md, docs/building.md,
docs/native-kernels.md, docs/rr-engine.md, packaging/SOURCES.txt and
scripts/build_release_glibc241.sh move.

README.md

@@ -138,7 +138,7 @@ ROCm does not need to be installed: the zip includes its runtime (from AMD's Ubu
 
 The full sequence is in [docs/building.md](docs/building.md). In short:
 
-1. Build ZLUDA `ee2f25a` with `patches/zluda/0002`–`0012` applied, including its `d4r_emit` example for offline texture builds.
+1. Build ZLUDA `ee2f25a` with `patches/zluda/0002`–`0013` applied, including its `d4r_emit` example for offline texture builds.
 2. Build the patched vkd3d-proton: `scripts/build_vkd3d_proton_d4r.sh OUT_DIR`.
 3. Build the shim and bridge: `scripts/build_d4r_nvngx_shim.sh`, `scripts/build_wine_nvcuda_bridge.sh`.
 4. Stage the runtime with your NVIDIA files: `scripts/install_d4r_runtime.sh _nvngx.dll nvngx_dlss.dll`.

docs/building.md

@@ -5,7 +5,7 @@ These steps produce the pieces the launcher needs: a patched ZLUDA, a patched vk
 
 | Component | Tested version |
 |---|---|
-| ZLUDA | `ee2f25a` (upstream), plus `patches/zluda/0002` through `0012` in order |
+| ZLUDA | `ee2f25a` (upstream), plus `patches/zluda/0002` through `0013` in order |
 | vkd3d-proton | `3dfc6f07` (the base GE-Proton11-3 ships), plus `patches/vkd3d-proton/0001` through `0003` in order |
 | ROCm | 7.2 (HIP runtime, clang, device libraries) |
 | Proton | GE-Proton11-3 (with its OptiScaler integration) |
@@ -18,7 +18,7 @@ git clone https://github.com/vosen/ZLUDA zluda && cd zluda
 git checkout ee2f25a
 git submodule update --init --recursive
 git lfs pull
-for p in 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012; do git apply /path/to/d4r/patches/zluda/$p-*.patch; done
+for p in 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013; do git apply /path/to/d4r/patches/zluda/$p-*.patch; done
 # rebuild the device helpers the patches changed (ptx/lib/zluda_ptx_impl*.bc)
 ZLUDA_SOURCE_ROOT=$PWD ROCM_ROOT=/opt/rocm /path/to/d4r/scripts/build_zluda_ptx_helpers.sh
 LIBRARY_PATH=/opt/rocm/lib cargo build --release -p zluda
@@ -46,11 +46,11 @@ What the patches add:
 - **0006**: `m16n8k8` f16 MMAs (DLSS 3 CNN, presets E/F) on RDNA3 WMMA like the k16 ones (`D4R_ZLUDA_WMMA_K8=0` disables it); weight-image slots for native prep kernels (`d4r_prep_key_at`, `d4r_prep_key_slots`); and wave64 compilation for offline texture-kernel builds (`D4R_ZLUDA_WAVE64=1`, with wave64 builds of the helper bitcode). `scripts/build_zluda_ptx_helpers.sh` now writes the `_w64` helper variants too.
 - **0007**: gfx12 WMMA layout lowering, optional native e4m3 FP8 WMMA (`D4R_ZLUDA_WMMA_FP8_NATIVE=1`), and an architecture argument for `d4r_emit`. `D4R_ZLUDA_WMMA_LAYOUT=12` on gfx11 is a validation shim, not a release setting.
 - **0008**: post-phase kernels for native overrides (`NAME_post1` … `NAME_post8`, see [native-kernels.md](native-kernels.md)). Preset K's dec5 layer runs as four phase kernels, so the K set needs this patch: an older `libnvcuda.so` would skip the phases.
-- **0008**: CUDA denoiser PTX support: four-half surface stores, floating-coordinate half texture sampling, streaming-cache store spellings, byte-vector trapping stores (including low-byte truncation from wider registers), finite-saturating half conversion, correctly typed half exponentiation, half unordered comparisons, and atomic reductions. CUDA block barriers use a workgroup release fence before the hardware barrier and an acquire fence afterward. It also fixes strict floating-point division operand selection in the LLVM AMDGPU backend and Cargo build-profile detection. Two LLVM sinking fixes remove repeated instruction-order rebuilding and avoid alias scans when no sink target exists; write tracking and memory-dependency checks remain intact. Initialize the LLVM submodule before applying this patch; rebuild device helpers and ZLUDA afterward.
+- **0009**: CUDA denoiser PTX support: four-half surface stores, floating-coordinate half texture sampling, streaming-cache store spellings, byte-vector trapping stores (including low-byte truncation from wider registers), finite-saturating half conversion, correctly typed half exponentiation, half unordered comparisons, and atomic reductions. CUDA block barriers use a workgroup release fence before the hardware barrier and an acquire fence afterward. It also fixes strict floating-point division operand selection in the LLVM AMDGPU backend and Cargo build-profile detection. Two LLVM sinking fixes remove repeated instruction-order rebuilding and avoid alias scans when no sink target exists; write tracking and memory-dependency checks remain intact. Initialize the LLVM submodule before applying this patch; rebuild device helpers and ZLUDA afterward.
-- **0009**: gfx12 native-FP8 half-to-e4m3 requantization, including the ReLU variant. Hardware packed FP8 conversion replaces the software rounding path only when `D4R_ZLUDA_WMMA_FP8_NATIVE=1` selects gfx12 native FP8. Explicit saturation and sign restoration preserve finite overflow, infinities, signed zero and NaNs. Rebuild both the device helpers and ZLUDA.
+- **0010**: gfx12 native-FP8 half-to-e4m3 requantization, including the ReLU variant. Hardware packed FP8 conversion replaces the software rounding path only when `D4R_ZLUDA_WMMA_FP8_NATIVE=1` selects gfx12 native FP8. Explicit saturation and sign restoration preserve finite overflow, infinities, signed zero and NaNs. Rebuild both the device helpers and ZLUDA.
-- **0010**: gfx12 native FP8 operands stay packed through the NVIDIA-to-WMMA lane gathers, removing fake-half splitting and repacking. Paired and unpaired operations preserve the previous K permutation, accumulation order and FP32-shadow scaling. Unpaired gathers execute in every source lane before zero-padding; masking EXEC around them loses valid source values. Rebuild both the device helpers and ZLUDA.
+- **0011**: gfx12 native FP8 operands stay packed through the NVIDIA-to-WMMA lane gathers, removing fake-half splitting and repacking. Paired and unpaired operations preserve the previous K permutation, accumulation order and FP32-shadow scaling. Unpaired gathers execute in every source lane before zero-padding; masking EXEC around them loses valid source values. Rebuild both the device helpers and ZLUDA.
-- **0011**: coalesce complete accumulator-register overwrites into one shadow-layout conversion. Intervening reads, rewritten shadow accesses and basic-block boundaries prevent coalescing; partial writes retain read/modify/write behavior. Gfx12 native-FP8 functions request eight waves per SIMD to limit register pressure. Rebuild ZLUDA and `d4r_emit`.
+- **0012**: coalesce complete accumulator-register overwrites into one shadow-layout conversion. Intervening reads, rewritten shadow accesses and basic-block boundaries prevent coalescing; partial writes retain read/modify/write behavior. Gfx12 native-FP8 functions request eight waves per SIMD to limit register pressure. Rebuild ZLUDA and `d4r_emit`.
-- **0012**: preserve signs through the native FP8 conversion instead of reconstructing them afterward. Explicitly clamp finite overflow and infinities, and map NaNs to signed infinity before conversion: native infinity produces the required `0x7f`/`0xff`, whereas native NaN always produces `0xff`. Plain and ReLU paths remain exhaustive-table identical to software. Rebuild device helpers and ZLUDA.
+- **0013**: preserve signs through the native FP8 conversion instead of reconstructing them afterward. Explicitly clamp finite overflow and infinities, and map NaNs to signed infinity before conversion: native infinity produces the required `0x7f`/`0xff`, whereas native NaN always produces `0xff`. Plain and ReLU paths remain exhaustive-table identical to software. Rebuild device helpers and ZLUDA.
 
 When linking on a system with ROCm libraries outside the default search path, include their library directory in `LIBRARY_PATH`. The build also needs the appropriate ROCm link libraries. `CARGO_BUILD_JOBS=8` caps parallel Rust compilation if memory is limited.
 
@@ -164,7 +164,7 @@ Mount the repository at `/work`, ROCm's compiler/headers/device libraries at `/o
 | Variable | Input |
 |---|---|
 | `D4R_RELEASE_BUILD_ROOT` | writable directory under `/work/build/` |
-| `D4R_ZLUDA_SRC` | isolated checkout inside that directory, with both pinned LLVM and HiGHS submodules, the real OCKL LFS payload, and patches `0002`–`0012` applied |
+| `D4R_ZLUDA_SRC` | isolated checkout inside that directory, with both pinned LLVM and HiGHS submodules, the real OCKL LFS payload, and patches `0002`–`0013` applied |
 | `D4R_VKD3D_SRC` | isolated vkd3d-proton checkout inside that directory, with its submodules and patches `0001`–`0003` applied |
 | `CARGO_HOME` | writable build-local Cargo cache; prefetch the locked dependencies for an offline build |
 | `D4R_ROCM_DIR` | `/opt/rocm` |

docs/native-kernels.md

@@ -81,21 +81,21 @@ Measured on the RX 9070 XT (gfx1201, RDNA4), Ray Reconstruction preset E,
 1280×720 → 3840×2160, with `D4R_CUDA_KERNEL_PROFILE` in the D3D12 harness:
 The earlier 20-frame run excluded the first 6 frames, with native hkpn output
 and gfx12 native FP8 enabled.
-The first implementation of patch `0009` replaced software half-to-e4m3
+The first implementation of patch `0010` replaced software half-to-e4m3
 requantization with hardware packed FP8 conversion: **33.90 ms** for the
 same-runtime software control, **26.28 ms** with native conversion, and
 **26.65 ms** without the diagnostic A/B gate. The compact integer saturation
-in `0009` plus `0010`'s packed FP8 operand gathers measured **25.33 ms**.
+in `0010` plus `0011`'s packed FP8 operand gathers measured **25.33 ms**.
 All four final RGBA16F frames are byte-identical.
 
-An 80-frame run, excluding the first 20, measures **24.764 ms** with `0009` +
+An 80-frame run, excluding the first 20, measures **24.764 ms** with `0010` +
-`0010`. Patch `0011`'s complete-pair shadow-store coalescing reduces that to
+`0011`. Patch `0012`'s complete-pair shadow-store coalescing reduces that to
 **23.340 ms**. Eight-wave register budgeting alone measures **20.135 ms**;
 both changes together measure **19.146 ms**. All 80 saved
 frames from each variant are byte-identical to the matching 80-frame control.
 Do not compare final images from different frame counts: the 20- and 80-frame
 captures differ even with the unchanged control.
-With `0012`'s signed native conversion, the same 80-frame configuration measures
+With `0013`'s signed native conversion, the same 80-frame configuration measures
 **16.234 ms**, with a byte-identical final frame. Signs stay in the half inputs;
 clamped finite values convert directly, and NaNs become signed infinity before
 conversion to obtain PTX's signed NaN bytes without post-conversion sign masks.
@@ -129,11 +129,11 @@ against 512 independently calculated, exactly representable half values.
 A gfx12 register-permutation replacement for the LDS gathers was correct but
 slower (27.44 ms), and was reverted.
 A twelve-wave register budget preserved the final image but increased time to
-25.560 ms; it is not selected by `0011`.
+25.560 ms; it is not selected by `0012`.
 An isolated-cache fast-math run measured 18.920 ms versus 19.146 ms without
 relaxed math, but changed the image; relaxed math is not selected.
 
-Cyberpunk 2077 with `0009` + `0010` rendered a loaded save at 1280×720→3840×2160 with CUDA feature 13,
+Cyberpunk 2077 with `0010` + `0011` rendered a loaded save at 1280×720→3840×2160 with CUDA feature 13,
 preset E, DLSSD 310.7.0 and split-frame VRAM interop. Moving views showed coherent
 geometry and reflections; the overlay's average upscaler time was about 26.0 ms.
 This is a functional visual check, not RTX image-quality parity. Native-Wayland
@@ -176,7 +176,7 @@ enc0 and dec0 read their input from CUDA textures rather than the plane arena, a
 
 `kernels/rr/rr_layer_spec.py` recovers a layer's structure from the corpus PTX alone: `rr_layer_spec.py enc0` prints the phase table (each maximal run of adjacent `mma`, with M/N/K derived from the fragment counts and the accumulator dataflow, the weight and bias byte offsets it reads, and the size of the epilogue between phases) and the stage classification; `--geometry` does the same for all eleven layers and prints each one's weight image extent. It is how enc0's layout above was established, and it is the reference the native layers are written against.
 
-Before native FP8 conversion, enc0's translated shader contained 83,373 instructions for 536 FP8 WMMAs. Operand gathering and software requantization dominated that static stream; those counts are not measurements of the patch `0009` shader. Hardware conversion removes the software codec but leaves operand-layout conversion and the surrounding neural computation. A global 128-thread bound is invalid for the 256-thread layers; the captured E launches use 32 threads for enc0, enc1 and dec0, 64 for dec1, 128 for enc2/enc3/dec2/dec3, and 256 for enc4/enc5/dec4. The remaining network must be optimized and measured rather than treating the codec gain as meeting the target.
+Before native FP8 conversion, enc0's translated shader contained 83,373 instructions for 536 FP8 WMMAs. Operand gathering and software requantization dominated that static stream; those counts are not measurements of the patch `0010` shader. Hardware conversion removes the software codec but leaves operand-layout conversion and the surrounding neural computation. A global 128-thread bound is invalid for the 256-thread layers; the captured E launches use 32 threads for enc0, enc1 and dec0, 64 for dec1, 128 for enc2/enc3/dec2/dec3, and 256 for enc4/enc5/dec4. The remaining network must be optimized and measured rather than treating the codec gain as meeting the target.
 
 ## RDNA4
 

docs/rr-engine.md

@@ -92,23 +92,23 @@ An isolated native phase-8 splice preserves the other NVIDIA phases and produces
 a byte-identical final 3840×2160 RGBA16F frame with matching denormal settings.
 The initial splice is slower: enc0 measures 14.90 ms versus a 6.59 ms translated
 baseline. It is a correctness experiment, not a shipping performance improvement.
-The first implementation of patch `0009`'s native FP8 requantization measured
+The first implementation of patch `0010`'s native FP8 requantization measured
 26.65 ms of GPU kernel time at 720p→4K after six warm-up frames. Its same-runtime
 software-codec control measured 33.90 ms. Compact integer saturation plus
-`0010`'s packed FP8 operand gathers measure 25.33 ms in that 20-frame run;
+`0011`'s packed FP8 operand gathers measure 25.33 ms in that 20-frame run;
 the complete RGBA16F output remains byte-identical. The matching 80-frame
-control measures 24.764 ms after excluding the first 20 frames. Patch `0011`'s
+control measures 24.764 ms after excluding the first 20 frames. Patch `0012`'s
 complete-pair shadow-store coalescing and eight-wave register budgeting together
 measure 19.146 ms, with all 80 saved frames byte-identical to that control.
-Patch `0012`'s signed native conversion reduces the same configuration to
+Patch `0013`'s signed native conversion reduces the same configuration to
 16.234 ms with a byte-identical final frame; its plain and ReLU conversions
 match software for every half encoding in both packed positions. Removing
 the harness's 200 ms inter-frame idle gap measures 15.144 ms in steady state,
 also with the identical final image.
 The older installed-runtime FTZ output differs and is not a valid arithmetic
-control. Cyberpunk with `0009` + `0010` rendered a loaded 4K save with
+control. Cyberpunk with `0010` + `0011` rendered a loaded 4K save with
 720p RR input, coherent moving views and approximately 26.0 ms overlay upscaler
-time. With `0011` + `0012` the harness measures 16.234 ms (200 ms idle gap
+time. With `0012` + `0013` the harness measures 16.234 ms (200 ms idle gap
 between frames) and 15.144 ms continuous, with byte-identical final frames.
 
 ## Next direct-converter win: B operands from transposed accumulators

packaging/SOURCES.txt

@@ -13,7 +13,7 @@ Built from source by d4r (GPL-3.0-only, d4r/licenses/d4r-LICENSE.txt):
 
 Third-party software, unmodified or patched by d4r:
   d4r/zluda/libcuda.so   ZLUDA (Apache License 2.0 or MIT), https://github.com/vosen/ZLUDA
-                         commit @ZLUDA_COMMIT@ with d4r/source/patches/zluda/0002 to 0012 applied.
+                         commit @ZLUDA_COMMIT@ with d4r/source/patches/zluda/0002 to 0013 applied.
                          It contains LLVM (Apache License 2.0 with LLVM exceptions).
                          Licenses: d4r/licenses/ZLUDA-LICENSE-*.txt, d4r/licenses/LLVM-LICENSE.txt
   d3d12.dll, d3d12core.dll

scripts/build_release_glibc241.sh

@@ -5,7 +5,7 @@
 set -euo pipefail
 ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
 : "${D4R_RELEASE_BUILD_ROOT:?set the build output directory}"
-: "${D4R_ZLUDA_SRC:?set a build-local ZLUDA checkout with patches 0002-0012 applied}"
+: "${D4R_ZLUDA_SRC:?set a build-local ZLUDA checkout with patches 0002-0013 applied}"
 : "${D4R_VKD3D_SRC:?set a build-local vkd3d-proton checkout with patches 0001-0003 applied}"
 : "${D4R_ROCM_DIR:?set ROCm with clang and device libraries}"
 BUILD="$(realpath -m "$D4R_RELEASE_BUILD_ROOT")"