Improve GPU compatibility, RDNA2 kernels and startup diagnostics

- Match render/compute adapters and gate RR models by GPU capabilities
- Add RDNA2 native texture kernels and fix FP16 rounding
- Harden model builds, cache validation and packaging
- Add startup tracing, timeouts, documentation and regression tests

kernels/native/build_native.sh

@@ -1,5 +1,6 @@
 #!/usr/bin/env bash
 # build_native.sh SRC.hip OUT.hsaco [extra clang flags]: natively compiled DLSS texture kernel (gfx1101, wave64 default)
+# WAVE=32|64 (default 64); CUMODE=1|0 (default 1): CU mode, or WGP mode (a workgroup's waves on all four SIMDs)
 set -euo pipefail
 ND=$(cd "$(dirname "$0")" && pwd)
 SRC=$(realpath "$1") OUT=$(realpath -m "$2"); shift 2
@@ -8,9 +9,10 @@ R=${D4R_ROCM_DIR:-/opt/rocm}
 ARCH=${D4R_GPU_ARCH:-gfx1101}
 W=${WAVE:-64}
 WF=$([[ $W == 64 ]] && echo -mwavefrontsize64 || echo -mno-wavefrontsize64)
+CU=$([[ ${CUMODE:-1} == 1 ]] && echo -mcumode || echo -mno-cumode)
 D=$(cd "$(dirname "$SRC")" && pwd)
 T=$(mktemp -d); trap 'rm -rf "$T"' EXIT
-(cd "$T" && "$R/lib/llvm/bin/clang++" -x hip -std=c++20 --offload-arch=$ARCH --offload-device-only -O3 $WF -mcumode \
+(cd "$T" && "$R/lib/llvm/bin/clang++" -x hip -std=c++20 --offload-arch=$ARCH --offload-device-only -O3 $WF $CU \
   -ffp-contract=off -fgpu-flush-denormals-to-zero -fno-fast-math -I"$D" -I"$ND" -I"$R/include" --rocm-path="$R" \
   --rocm-device-lib-path="$R/amdgcn/bitcode" "$@" -o "$OUT" "$SRC" -save-temps=cwd --no-gpu-bundle-output)
 S=$(ls "$T"/*.s | head -1)

kernels/native/output_tile.h

@@ -24,8 +24,9 @@ RT void output_color_pack(f4 color, float exposure, uint32_t* a, uint32_t* b)
         const float q = div_a(ln, 9.0f) + asf(0xBC4FAE29u);
         weight = rcp_a(y) * q;
     }
-    *a = pack16(ashu((h1)(y * weight)), ashu((h1)((exposure * co) * weight)));
-    *b = pack16(ashu((h1)((exposure * cg) * weight)), ashu((h1)color[3]));
+    // f2h_rn: rounded to f32 and then to f16, as ZLUDA's compile does (no v_fma_mixlo of the product)
+    *a = pack16(ashu(f2h_rn(y * weight)), ashu(f2h_rn((exposure * co) * weight)));
+    *b = pack16(ashu(f2h_rn((exposure * cg) * weight)), ashu(f2h_rn(color[3])));
 }
 
 RT int output_tile_coord(int relative, int lo, int hi)

kernels/native/ptx2hip.py

@@ -593,10 +593,10 @@ class Translator:
         if dt == 'f16' and stp == 'f32':
             if 'rn' not in mods:
                 raise Err(op)
-            A(a[0], f'(h1){V(a[1], "f32")}', 'f16'); return
+            A(a[0], f'f2h_rn({V(a[1], "f32")})', 'f16'); return
         if dt == 'f16x2' and stp == 'f32':
             # d = {cvt(a) in the high half, cvt(b) in the low half}
-            A(a[0], f'pack16(ashu((h1){V(a[2], "f32")}), ashu((h1){V(a[1], "f32")}))', 'u32'); return
+            A(a[0], f'pack16(ashu(f2h_rn({V(a[2], "f32")})), ashu(f2h_rn({V(a[1], "f32")})))', 'u32'); return
         if dt == 'f16' and stp == 'f16':
             x = V(a[1], 'f16')
             if 'rni' in mods:

kernels/native/ptx_rt.h

@@ -77,6 +77,16 @@ RT uint32_t f2u_rz(float x)
 }
 
 // ---------------------------------------------------------------- f16 (denormals kept)
+// cvt.rn.f16.f32: the f32 value rounded to f16. The empty asm keeps LLVM from folding the conversion into the
+// f32 operation that produced the value (fptrunc(fma(fpext ...)) -> v_fma_mixlo/mixhi_f16), which rounds the exact
+// result to f16 once instead of to f32 and then to f16: on an RX 7700 XT that differed from the two-step result for
+// 1 in ~29,000 random f16 operand triples, and in the hiluma output kernel it left single 1-ulp seeds that the
+// temporal history then spread (ZLUDA keeps both roundings).
+RT h1 f2h_rn(float x)
+{
+    __asm__ volatile("" : "+v"(x));
+    return (h1)x;
+}
 RT h1 hfma(h1 a, h1 b, h1 c) { return __builtin_fmaf16(a, b, c); }
 RT h2 h2fma(h2 a, h2 b, h2 c) { return __builtin_elementwise_fma(a, b, c); }
 RT h1 hmaxn(h1 a, h1 b) { return __builtin_fmaximum_numf16(a, b); }