Port K kernel tuning and M gfx1101 flags

Preset K, byte-identical to the previous output in all captured buffers
and the harness image, measured on an RX 7700 XT:

- LDS row padding so WMMA operand loads hit distinct banks

- WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for
  enc0/dec0/dec3, more waves per window in enc4/dec4/dec5

- cheaper operand plumbing in common/wmma_layout.h (packed f16
  conversions, no dynamic vector indexing), raw buffer weight loads,
  accumulator-init vectors prepared once

- enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split

- dec5 as four dependent phase kernels

kernels/m/rrlite_dec1_4x4.hip

@@ -1,7 +1,16 @@
 // fast numerics: intermediate activations f16 (no FP8 re-quantisation), f32 accumulation through GEMM chains
+// RX 7700 XT: VGPR cap 160 removes the scratch use; byte-identical to the default build, gfx1101 only
+// d4r-build-flags-gfx1101: -DSWIN_MAX_VGPR=160
 #define SWIN_NO_Q8
 #define SWIN_F32ACC
+#ifndef SWIN_MAX_VGPR
 #define SWIN_MAX_VGPR 128
+#endif
+#ifndef SWIN_MLP_R
 #define SWIN_MLP_R(NW) 2
+#endif
 #include "swin_block.h"
-SWIN_MODULE_W(rrlite_dec1_4x4, 64, 2, 8, 0, false, CommonParams, 96)
+#ifndef SWIN_NW
+#define SWIN_NW 8
+#endif
+SWIN_MODULE_W(rrlite_dec1_4x4, 64, 2, SWIN_NW, 0, false, CommonParams, 96)