Port K kernel tuning and M gfx1101 flags
Preset K, byte-identical to the previous output in all captured buffers and the harness image, measured on an RX 7700 XT: - LDS row padding so WMMA operand loads hit distinct banks - WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for enc0/dec0/dec3, more waves per window in enc4/dec4/dec5 - cheaper operand plumbing in common/wmma_layout.h (packed f16 conversions, no dynamic vector indexing), raw buffer weight loads, accumulator-init vectors prepared once - enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split - dec5 as four dependent phase kernels
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@@ -13,7 +13,10 @@
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#if defined(D4R_ACCURACY) && defined(PWIN_F32ACC)
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#undef PWIN_F32ACC
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#endif
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// D4R_FAST_MATH: the opt-in approximate variant (FMA contraction allowed; not bit-identical to NVIDIA's rounding)
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#ifndef D4R_FAST_MATH
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#pragma clang fp contract(off)
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#endif
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typedef _Float16 half_t;
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typedef _Float16 hv2 __attribute__((ext_vector_type(2)));
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@@ -22,6 +25,32 @@ typedef float f8v __attribute__((ext_vector_type(8)));
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typedef uint32_t u8v __attribute__((ext_vector_type(8)));
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typedef uint32_t u4v __attribute__((ext_vector_type(4)));
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__device__ __forceinline__ half_t half_reciprocal(half_t h)
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{
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#ifdef PWIN_NATIVE_HRECIP
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return __builtin_amdgcn_rcph(h);
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#else
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return (half_t)__builtin_amdgcn_rcpf((float)h);
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#endif
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}
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__device__ __forceinline__ half_t half_rsqrt(half_t h)
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{
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#ifdef PWIN_NATIVE_HRECIP
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return __builtin_amdgcn_rsqh(h);
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#else
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return (half_t)__builtin_amdgcn_rsqf((float)h);
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#endif
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}
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// LDS row padding in halves: activation rows of N halves are stored N + PWIN_PAD apart, so the 16 token rows a
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// WMMA operand load (op_lds / lds_row16) touches start on distinct banks (row stride = 16 mod 32 bytes). With
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// unpadded 128- or 256-byte rows every lane hits the same banks (measured: 6x slower WMMA feed). 0 = old layout.
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#ifndef PWIN_PAD
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#define PWIN_PAD 8
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#endif
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#define LDSR(N) ((N) + PWIN_PAD)
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__device__ __forceinline__ uint32_t lane_id()
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{
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return __builtin_amdgcn_mbcnt_lo(~0u, 0u);
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@@ -33,11 +62,24 @@ typedef wm_op op_t; // WMMA operand: u8v (gfx11) or u4v (gfx12)
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// PWIN_F32ACC: keep the accumulator in f32 through the chain (rounded to f16 where the values are used)
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__device__ __forceinline__ f8v mma16(const op_t& a, const op_t& b, f8v c)
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{
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#if defined(PWIN_NATIVE_F16ACC) && !defined(PWIN_F32ACC) && D4R_WMMA_LAYOUT == 11
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h16 hc = {};
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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hc[2 * i] = (half_t)c[i];
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const h16 hd = __builtin_amdgcn_wmma_f16_16x16x16_f16_w32(
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__builtin_bit_cast(h16, a), __builtin_bit_cast(h16, b), hc, false);
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f8v d;
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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d[i] = (float)hd[2 * i];
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#else
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f8v d = wm_mma(a, b, c);
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#ifndef PWIN_F32ACC
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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d[i] = (float)(half_t)d[i];
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#endif
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#endif
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return d;
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}
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@@ -136,6 +178,46 @@ __device__ __forceinline__ op_t op_img(const u8v* __restrict__ img, int idx)
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{
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return wm_op_image(img, idx);
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}
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// 8 floats of image slot `slot` + this lane's half (f32 accumulator-init vectors the prep kernel stores after the
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// operand tiles: slot pair (2 v, 2 v + 1) = rows wm_acc_row_h(., h) of vector v), slot uniform
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__device__ __forceinline__ f8v img_vec(const u8v* __restrict__ img, int slot)
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{
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const uint32_t h = lane_id() >> 4;
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#if defined(PWIN_VEC_SCALAR) // both layouts: slot pair (2 v, 2 v + 1) = the two halves' rows
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// both halves' slots with wave-uniform (scalar) loads, then one select per value (instead of a per-lane
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// vector load, or 8 shifts + 8 f16 -> f32 conversions from the weights); the same f32 values
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const u8v x0 = img[slot], x1 = img[slot + 1];
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u8v x;
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#pragma unroll
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for (int i = 0; i < 8; ++i)
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x[i] = h ? x1[i] : x0[i];
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return __builtin_bit_cast(f8v, x);
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#elif D4R_WMMA_LAYOUT == 12 || defined(PWIN_NO_BUFFER_IMG)
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const u8v x = img[slot + (int)h];
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return __builtin_bit_cast(f8v, x);
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#else
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const __amdgpu_buffer_rsrc_t r = __builtin_amdgcn_make_buffer_rsrc((void*)img, (short)0, 0x7fffffff, 0x31004000);
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const uint32_t vo = h * 32u, so = 32u * (uint32_t)slot;
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const u4v a = __builtin_amdgcn_raw_buffer_load_b128(r, vo, so, 0), b = __builtin_amdgcn_raw_buffer_load_b128(r, vo + 16, so, 0);
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return __builtin_bit_cast(f8v, (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]});
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#endif
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}
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// slot (tile, lane l & 15) of an operand image in global memory: tile is wave-uniform, so the row address stays a
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// scalar base and only the lane indexes it (global loads with an SGPR base and a VGPR offset; written as one
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// index tile * 16 + m every load paid 64-bit VALU address arithmetic)
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__device__ __forceinline__ op_t op_imgt(const u8v* __restrict__ img, int tile)
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{
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#if D4R_WMMA_LAYOUT == 12 || defined(PWIN_NO_BUFFER_IMG)
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return wm_op_image(img + 16 * tile, (int)(lane_id() & 15));
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#else
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// gfx11: a raw buffer load (resource from img: base in SGPRs, 0x31004000 = gfx11 raw dword3, validated), the
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// tile offset as the scalar offset and the lane's 32-byte slot as the vector offset: no VALU address math
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const __amdgpu_buffer_rsrc_t r = __builtin_amdgcn_make_buffer_rsrc((void*)img, (short)0, 0x7fffffff, 0x31004000);
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const uint32_t vo = (lane_id() & 15) * 32u, so = 512u * (uint32_t)tile;
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const u4v a = __builtin_amdgcn_raw_buffer_load_b128(r, vo, so, 0), b = __builtin_amdgcn_raw_buffer_load_b128(r, vo + 16, so, 0);
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return (u8v){a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3]};
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#endif
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}
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// operand -> slot idx of an operand image in LDS (read back with op_img)
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__device__ __forceinline__ void op_img_store(u8v* img, int idx, const op_t& v)
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{
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@@ -184,3 +266,25 @@ __device__ __forceinline__ int frag_offset(int k, int n)
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{
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return 64 * (n & 7) + 16 * ((k & 7) >> 1) + 8 * (n >> 3) + 4 * (k >> 3) + 2 * (k & 1);
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}
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// Diagnostic phase stamps (-DPWIN_PROF): per-wave SHADER_CYCLES deltas summed into d4r_dbg[k], wave counts into
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// d4r_dbg[32 + k] (read back by bench/native/pwbench). Region k ends at PROF(k). Off: no code.
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#ifdef PWIN_PROF
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__device__ unsigned long long d4r_dbg[64];
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#define PROF_INIT uint32_t prof_last_ = (uint32_t)__builtin_readcyclecounter()
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#define PROF(k) \
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do \
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{ \
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const uint32_t n_ = (uint32_t)__builtin_readcyclecounter(); \
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if (lane_id() == 0) \
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{ \
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__hip_atomic_fetch_add(&d4r_dbg[k], (unsigned long long)((n_ - prof_last_) & 0xfffffu), __ATOMIC_RELAXED, \
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__HIP_MEMORY_SCOPE_AGENT); \
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__hip_atomic_fetch_add(&d4r_dbg[32 + (k)], 1ull, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); \
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} \
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prof_last_ = n_; \
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} while (0)
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#else
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#define PROF_INIT do {} while (0)
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#define PROF(k) do {} while (0)
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#endif
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