Port K kernel tuning and M gfx1101 flags

Preset K, byte-identical to the previous output in all captured buffers
and the harness image, measured on an RX 7700 XT:

- LDS row padding so WMMA operand loads hit distinct banks

- WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for
  enc0/dec0/dec3, more waves per window in enc4/dec4/dec5

- cheaper operand plumbing in common/wmma_layout.h (packed f16
  conversions, no dynamic vector indexing), raw buffer weight loads,
  accumulator-init vectors prepared once

- enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split

- dec5 as four dependent phase kernels

kernels/k/dltss_pwin_dec1_layer.hip

@@ -1,5 +1,8 @@
-// CU mode: the waves of a window share one L0 cache (1-6% faster here; slower in the wide layers)
-// d4r-build-flags: -mcumode
+// WGP mode: with the padded LDS rows (PWIN_PAD) this layer is 2-5% faster in WGP mode than in CU mode
+// (CU mode was 1-6% faster before the padding)
+// accumulator init vectors from the weights (the prepared f32 table is 2-4% slower here)
+// Q, K, V chains two at a time (fewer live accumulators, spills 164 -> 68 B; -2 %)
+// d4r-build-flags: -DPWIN_VEC_FROM_WEIGHTS -DPWIN_QKV_SPLIT
 #define PWIN_F32ACC
 #include "pwin_layer.h"
 PWIN_DECODER(dltss_pwin_dec1_layer, 2, 64, 64)