Port K kernel tuning and M gfx1101 flags

Preset K, byte-identical to the previous output in all captured buffers
and the harness image, measured on an RX 7700 XT:

- LDS row padding so WMMA operand loads hit distinct banks

- WGP mode for enc1/enc2/dec1/dec2, ds_bpermute half-wave exchange for
  enc0/dec0/dec3, more waves per window in enc4/dec4/dec5

- cheaper operand plumbing in common/wmma_layout.h (packed f16
  conversions, no dynamic vector indexing), raw buffer weight loads,
  accumulator-init vectors prepared once

- enc1 as a single-buffer recompute layer, dec1 Q/K/V chains split

- dec5 as four dependent phase kernels

kernels/k/dltss_pwin_dec0_layer.hip

@@ -1,5 +1,11 @@
-// CU mode: the waves of a window share one L0 cache (1-6% faster here; slower in the wide layers)
-// d4r-build-flags: -mcumode
+// CU mode: the waves of a window share one L0 cache (1-6% faster here; slower in the wide layers). The WMMA half
+// exchange goes through ds_bpermute (VALU-bound layer: -1..-3%)
+// f32 -> f16 pairs converted straight into one register (WM_CVT_ASM: no v_pack copies; -1..-3 %)
+// norm / residual / embedding ReLU on packed f16 pairs (PWIN_PK_ELEM with the packed g2/b2 table; same ops, -1 %)
+// d4r-build-flags: -mcumode -DWM_HALF_BPERMUTE -DWM_CVT_ASM -DPWIN_PK_ELEM -DPWIN_PACKED_RESIDUAL
+// RDNA4: no WM_CVT_ASM (its inline asm needs the compiler's real-true16 mode on gfx12; the plain conversion
+// costs one pack per pair and gfx12 operands need no lane exchange anyway)
+// d4r-build-flags-gfx12: -mcumode -DWM_HALF_BPERMUTE -DPWIN_PK_ELEM -DPWIN_PACKED_RESIDUAL
 #define PWIN_F32ACC
 #include "pwin_pos.h"
 POS_DECODER(dltss_pwin_dec0_layer, 2, 32, 64, 40, 48, 2)