diff --git a/docs/rr-engine.md b/docs/rr-engine.md new file mode 100644 index 0000000..937cbf7 --- /dev/null +++ b/docs/rr-engine.md @@ -0,0 +1,188 @@ +# The swin-layer engine: design + +Why this exists: a per-phase port of NVIDIA's `cuda_dldn_engine_swin_*` keeps the cost that +makes those kernels slow. Disassembled, the translated `swin_enc0` kernel is 83,373 +instructions for 536 FP8 WMMAs. The top of the mix is operand assembly, not arithmetic: + +| instruction | count | +| --- | --- | +| `v_cndmask_b32_e64` | 9,124 | +| `ds_bpermute_b32` | 7,976 | +| `v_lshrrev_b32_e32` / `v_pk_lshrrev_b16` | 9,695 | +| `v_and_b32` / `v_perm_b32` / `v_pk_add_u16` / `v_pk_min_u16` | 13,750 | +| `v_cvt_f16_f32` / `v_cvt_f32_f16` (all forms) | 3,568 | +| `v_wmma_f32_16x16x16_fp8_fp8` | 536 | + +Those bit operations and cross-lane permutes exist only to reassemble NVIDIA's register +fragments into WMMA operands. A kernel that keeps its activations in a staged e4m3 image and +reads its operands directly from it does not pay them. + +## The primitives, already in the tree and already bit-identical to the translated path + +`kernels/tex/tex_common.h` (with `kernels/common/wmma_layout.h`), used today by the working +natives `kernels/tex/enc0_tail.hip` and `kernels/tex/dec0_head.hip`: + +- `kop_from16(u4v d)` — this half's WMMA operand (8 e4m3 bytes) from 16 e4m3 bytes, in + NVIDIA's k order. It is a half selection, not a shuffle. +- `kop_image(const kslot* img, int idx)` — the same from a prepared weight image, where a + `kslot` is the 16 e4m3 bytes of one k16 operand row. +- `kslot_from16(u4v d)` — the weight image's own conversion, done once in a `_prep` kernel, + so the main kernel never touches the weight layout. +- `k32_e4m3(f8v c, kop a0, kop b0, kop a1, kop b1)` — one m16n8k32 e4m3 step as two gfx12 + FP8 WMMAs. With `D4R_TEX_FP8` it is the native FP8 instruction with no scaling; the + comment records that its result is bit-identical to ZLUDA's gfx12 lowering of NVIDIA's + mma, which is what our reference runs through. + +The one structural fact that makes this cheap: on gfx12 the accumulator layout *is* the +next GEMM's operand layout (`wmma_layout.h`: "D VGPR i is row i + 8h, which is the gfx12 +B-operand layout of the next GEMM (no exchange)"). So an epilogue requantising its +accumulator to e4m3 and staging it as a row-major image in shared memory gives the next +phase its operands with no cross-lane movement at all. + +## Shape of a layer + +1. `_prep` kernel (once per launch, like `enc0_tail`'s): read the layer's weight image at + `arg040` and write each phase's B operands as `kslot`s into a global buffer. +2. Main kernel, per token patch: + - load the layer's input (texture/surface args) and compute the first operand image; + - for each phase in the descriptor: build A (`kop_from16` from a staged image, or from + the previous phase's requantised accumulator), run `k32_e4m3` per (m, n) tile with the + prepared B, apply the epilogue (e4m3 requantise into the next image, clamped cubic + activation, f16 column-table add, RMS/LayerNorm, softmax, patch expand, plane scatter, + lane merge, surface scatter); + - write the layer's output. + +## Descriptor + +Each layer is a `kernels/rr/descriptor_.py` with `phases()` (a list of dicts, one per +phase: shapes, A source, B offset, C source, K tiling, epilogue kind and its operands) and +`layer()` (launch geometry, argument offsets, token/tile geometry). Every offset must be a +number with evidence behind it; anything unverified must say so. + +## Validation + +By output surface against the translated reference: run the layer's native kernel alone +(`D4R_RRSWIN_ONLY=` in its own native dir) and compare the layer's own output +surfaces with `kernels/tools/compare_launch_dump.py`. Per-phase oracle comparison is a +debugging aid for a phase that is already failing, not the acceptance gate. Note two traps +that cost the agents hours: the debug payload is written into a *window* of a larger block +(the containing argument and the window offset differ per layer, so read the argument the +arena actually lives in, at `arena_offset + base`), and the harness reads its dump after a +context synchronise, so a payload can be masked by later kernels in the frame. + +### Current gfx1201 evidence + +The checked shared-memory primitive probe (`rrswin_engine_k16_test.cpp`) passes its +GEMM, f16 accumulation rounding, requantization, weight preparation and phase-chain +comparisons. These checks do not establish a complete RR implementation. + +The phase-8 pilot now compares all 196,608 f16 results in 64 captured blocks +without a mismatch. Its previous comparison was invalid: a six-token-tile phase +overflowed a four-tile accumulator array, device output had no block stride, and +the host block stride omitted the 32 lanes. Weight preparation now uses per-block +shared memory rather than concurrent writes into one global buffer. + +The host phase-8 model also needed all 32 lanes to assemble the activation image, +an 80-register stride for the combined operand/result payload, and f16 output +rounding. With those corrections, the documented fragment and weight maps match +the captured oracle; the previous apparent operand-layout contradiction was not +evidence of a wrong map. + +An isolated native phase-8 splice preserves the other NVIDIA phases and produces +a byte-identical final 3840×2160 RGBA16F frame with matching denormal settings. +The initial splice is slower: enc0 measures 14.90 ms versus a 6.59 ms translated +baseline. It is a correctness experiment, not a shipping performance improvement. +The first implementation of patch `0009`'s native FP8 requantization measured +26.65 ms of GPU kernel time at 720p→4K after six warm-up frames. Its same-runtime +software-codec control measured 33.90 ms. Compact integer saturation plus +`0010`'s packed FP8 operand gathers measure 25.33 ms in that 20-frame run; +the complete RGBA16F output remains byte-identical. The matching 80-frame +control measures 24.764 ms after excluding the first 20 frames. Patch `0011`'s +complete-pair shadow-store coalescing and eight-wave register budgeting together +measure 19.146 ms, with all 80 saved frames byte-identical to that control. +Patch `0012`'s signed native conversion reduces the same configuration to +16.234 ms with a byte-identical final frame; its plain and ReLU conversions +match software for every half encoding in both packed positions. Removing +the harness's 200 ms inter-frame idle gap measures 15.144 ms in steady state, +also with the identical final image. +The older installed-runtime FTZ output differs and is not a valid arithmetic +control. Cyberpunk with `0009` + `0010` rendered a loaded 4K save with +720p RR input, coherent moving views and approximately 26.0 ms overlay upscaler +time. With `0011` + `0012` the harness measures 16.234 ms (200 ms idle gap +between frames) and 15.144 ms continuous, with byte-identical final frames. + +## Next direct-converter win: B operands from transposed accumulators + +Validated mapping (read-only IR investigation, not yet implemented) for gfx12 +native-FP8 MMAs whose A operand is a requantization of an earlier accumulator +pair — the encoder's relu and plain chains in +`/tmp/d4r-packed-enc0-analysis/linked.ll`: + +* Producer: an MMA pair produces four `<2 x i32>` transposed accumulators + `(q=0/1, p=1/2)`; today each is converted with `d4r_wmma_t_to_nv` (4 bpermutes), + stored to registers, requantized by `d4r_cvt_rn_satfinite[_relu]_e4m3x2_f16x2`, + repacked into four words (`%11374..%11377` for the relu chain), loaded again by + every consumer and converted by `d4r_wmma12f8_b_from_a` (8 bpermutes per + consumer). ≥60 consumer sites in enc0, ≥3 fragment groups. +* The composition `t_to_nv → cvt → pack → b_from_a` collapses algebraically: with + `h = lane/16`, `r = lane&7`, `t = 2h`, the WMMA B word `j` of a lane is + `pack(cvt(f16x2{lo16(gather(A0, T_j)), lo16(gather(A1, T_j))}), ...)`, where + `A0/A1 = (r, r+8)` and register `.x` for lanes < 16, `(r+8, l)` and `.y` + otherwise. One helper per producer fragment — + `d4r_wmma12f8_b_from_t(uint2 d00, uint2 d01, uint2 d10, uint2 d11)` — replaces + 32 producer bpermutes + the alloca round trip + 8 bpermutes per consumer with + 8 bpermutes total, all consumers CSE to one call. +* Slot order is chain-specific (out0/out1 ← q=0; out2/out3 ← q=1; low/high 16-bit + half ← p=1/p=2); a matcher must read it off the actual insertelement/bitcast + structure, and reject fragments with mixed cvt variants or partial updates + (F32-shadow path needs its own derivation and is not covered). +* The same investigation found no sites where packed-f16 arithmetic could + commute across `toNv` (the inserted values come from global loads, not shadow + conversions), so that rewrite is not worth building. + +Full derivation with anchors is in the session transcript +(`agent://Fp8ShadowOperandFusion`); the probe extension to gate it (producer → +requantize → consumer chain in `rrswin_fp8_unpaired.ptx`) is described there. + + +## How a layer feeds the engine (design finding, not yet implemented) + +The engine's phases read their activations from a *staged image* — rows of consecutive e4m3 k — +not from NVIDIA's mma fragments. Two ways to get that image exist, and the cheap one is not the +obvious one: + +1. Rewrite the layer's prologue natively (load the input planes, the norm, the patch geometry) + and have it stage the image directly. Correct, but it means re-deriving the layer's whole + input path, which is where most of the per-layer reverse engineering sits. +2. Cut NVIDIA's PTX *after* its own loading and norming, exactly as the working bodies do today, + and convert the fragments it hands over into the image **once per phase boundary** instead of + per mma. Each lane's fragment bytes are documented (row and k per byte, in the body's header); + writing them to shared memory at their (row, k) positions is a shared-memory scatter, which is + cheap, whereas ZLUDA's per-mma reassembly is what the 7,976 `ds_bpermute_b32` and 9,124 + `v_cndmask_b32_e64` in the translated kernel are paying for. + +Route 2 reuses the cut machinery and the ABI the existing bodies already have, and it is +the reason the engine does not need a prologue rewrite to be useful. What it does need, per layer, +is: the fragment-to-image staging at the cut boundary, the descriptor (offset/layout per phase), +the epilogue vocabulary (the engine has the clamped cubic activation; norm, softmax, column-table +add, patch expand, plane scatter, lane merge and surface scatter are still to come), and the +image-to-fragment conversion back at the exit, where the surviving PTX expects specific registers. + +## Rejected direct-converter route + +The removed `swin_gemm_zluda` experiment passed widened NVIDIA A/B fragments +straight into ZLUDA's native MMA helpers. Those types matched the helper ABI, +but the data did not: ZLUDA first forms the WMMA A operand from NVIDIA B through +`t_a_from_b`, and the WMMA B operand from NVIDIA A through `t_b_from_a`. +Skipping those cross-lane gathers is not bit-exact by construction. + +The staged-image route uses independently checked fragment maps and the existing +`kop_image` / `swin_operand` / `k32_e4m3` primitives instead. The isolated phase-8 +recipe in `swin_enc0_recipe.py` preserves the surrounding NVIDIA code. It stages +one token tile and the already-prefetched B fragments in shared memory, computes +the two weight tiles, and hands the rounded result back through lane-major shared +slots. Enc0's 3200-byte `input_tensor` is dead after prologue line 3938 and can be +reused; the final surface epilogue still needs the separate `input_noise` array. + +The generic helper model and phase-8 oracle comparison establish these mappings, +not the unvalidated full-layer descriptors or the scalar full-body experiments. diff --git a/kernels/build.sh b/kernels/build.sh index b61bcb2..7d41998 100755 --- a/kernels/build.sh +++ b/kernels/build.sh @@ -2,7 +2,7 @@ # Builds the native replacements for DLSS kernels into one directory that ZLUDA serves them from # (D4R_ZLUDA_NATIVE_DIR, or NativeKernelDirFast in d4r.ini). See docs/native-kernels.md. # -# usage: kernels/build.sh [all|k|l|m|tex|rr] [OUT_DIR] (default: all, kernels/out/native) +# usage: kernels/build.sh [all|k|l|m|tex|rr|rrswin] [OUT_DIR] (default: all, kernels/out/native) # # D4R_ROCM_DIR ROCm installation with clang and the HIP device libraries (default /opt/rocm) # D4R_GPU_ARCH target GPU (default gfx1101): an RDNA3 (gfx110x) or RDNA4 (gfx120x) target; the kernels @@ -40,7 +40,7 @@ esac CLANG="$ROCM/lib/llvm/bin/clang++" [[ -x "$CLANG" ]] || { echo "clang++ not found in $ROCM/lib/llvm/bin (set D4R_ROCM_DIR)" >&2; exit 2; } mkdir -p "$OUT" -case "$WHAT" in all|k|l|m|tex|rr) ;; *) echo "unknown kernel family: $WHAT" >&2; exit 2 ;; esac +case "$WHAT" in all|k|l|m|tex|rr|rrswin) ;; *) echo "unknown kernel family: $WHAT" >&2; exit 2 ;; esac # Never certify a directory containing older fast binaries as an accuracy set. if [[ "$ACCURACY" == 1 ]] && compgen -G "$OUT/*.hsaco" >/dev/null && { [[ ! -f "$OUT/d4r-accuracy.txt" ]] || [[ "$(cat "$OUT/d4r-accuracy.txt")" != 1 ]]; }; then @@ -204,5 +204,25 @@ if [[ "$WHAT" == rr || ( "$WHAT" == all && -n "${D4R_DLSSD_DLL:-}" ) ]]; then D4R_DLSS_PTX_DIR="$RR_PTX_DIR" "$HERE/tex/build_tex.sh" "$kernel" sust_only "$OUT" done fi +if [[ "$WHAT" == rrswin ]]; then + echo "== Ray Reconstruction Swin layers" + : "${D4R_DLSSD_DLL:?set D4R_DLSSD_DLL to the CUDA-capable nvngx_dlssd.dll}" + : "${D4R_ZLUDA_EMIT:?set D4R_ZLUDA_EMIT to d4r_emit from a patched ZLUDA build}" + RR_PTX_DIR="${D4R_DLSSD_PTX_DIR:-$HERE/extracted/rr}" + if [[ -z "${D4R_DLSSD_PTX_DIR:-}" ]]; then + python3 "$HERE/tools/extract_dlss_ptx.py" "$D4R_DLSSD_DLL" "$RR_PTX_DIR" + elif [[ ! -d "$RR_PTX_DIR" ]]; then + echo "missing extracted RR PTX directory: $RR_PTX_DIR" >&2; exit 2 + fi + # one entry per denoiser layer; a layer whose body is not written yet is skipped so the family + # can be built while the ten bodies land independently + for layer in ${D4R_RRSWIN_ONLY:-enc0 enc1 enc2 enc3 enc4 enc5 dec0 dec1 dec2 dec3 dec4}; do + [[ -f "$HERE/rr/rrswin_$layer.hip" ]] || { echo "skipping $layer (kernels/rr/rrswin_$layer.hip is absent)"; continue; } + D4R_PREFER_ACCURACY="$ACCURACY" D4R_ROCM_DIR="$ROCM" D4R_GPU_ARCH="$ARCH" \ + D4R_ZLUDA_WAVE64=0 D4R_TEX_FP8="$FP8" \ + D4R_DLSS_PTX_DIR="$RR_PTX_DIR" "$HERE/tex/build_tex.sh" \ + "cuda_dldn_engine_swin_${layer}_kernel" "../rr/rrswin_$layer" "$OUT" + done +fi [[ "$ACCURACY" == 1 ]] && printf '1\n' > "$OUT/d4r-accuracy.txt" echo "native kernels in $OUT" diff --git a/kernels/rr/descriptor_dec0.py b/kernels/rr/descriptor_dec0.py new file mode 100644 index 0000000..57ee69d --- /dev/null +++ b/kernels/rr/descriptor_dec0.py @@ -0,0 +1,702 @@ +"""Machine-readable descriptor for `cuda_dldn_engine_swin_dec0_kernel`. + +The WMMA engine's per-layer input. Every number here is read out of +`~/.cache/d4r-rr-corpus/0023-PREPASS_ENTRYPOINT_NAME.ptx` (entry lines 1018-47791) +with `kernels/rr/rr_layer_spec.py`'s parser, or measured on the GPU; the source of +each family of numbers is named in the comments and anything not established that +way carries an `"unverified"` key. + +Conventions used throughout: + +* `m_tiles` counts 16-row mma tiles, `n_tiles` counts 8-column n tiles, `k` is the + contraction depth of the phase. `mma` is the shape NVIDIA emits, + `mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e4m3.f16`. +* The engine's unit is `k32_e4m3` (one `wmma_f32_16x16x16_fp8_fp8` pair), so a + phase of depth K is `k // 16` WMMA steps per output tile, two per k32 slice. +* The weight image is arg040, 47376 bytes. A *tile* is 512 bytes: 32 lanes x 16 + bytes, holding two n-tiles' B fragments. For a phase with `k_slices` k32 steps + the tile index of n-tile `nt`, step `ks` is `k_slices * (nt >> 1) + ks`, and + inside a tile the fragment for n-tile `nt` sits at bytes `0..7` when `nt` is + even and `8..15` when it is odd (both read by the same `ld.weak.global.ca.v4` + at `W + 16*laneid + base`). The column a lane owns inside a tile is + `8*(nt & 1) + 2*t + r` for register `r`, and the address bit assignment inside + the tile is + `bit0 = k&1, bit1 = (k>>4)&1, bit2 = column&1, bit3 = column>>3, + bits4-5 = (column>>1)&3, bits6-8 = (k>>1)&7` + for the interleaved byte->k map, or + `bit0-1 = k&3, bit2 = column&1, bit3 = column>>3, bits4-5 = (column>>1)&3, + bits6-8 = k>>2` + for the consecutive one; see `rrswin_dec0.hip` for both and for the A side. + `"unverified"`: which of the two byte maps the mma uses was not settled -- + the first attempt to prove it was invalidated by an ambient-memory comparison + (see the "Validation" section of rrswin_dec0.hip), so both are carried. +* A *column table* (E1's gain, the per-column addends) is read with the table + address `W + ((laneid << 2) & 12) + off`: the four lanes with equal `laneid & 3` + share a 16-byte word, so one load covers 32 columns. +* Register names (`%rNNNN`) are cited so each field can be checked against the + PTX with `sed -n`. +""" + + +def layer(): + """Launch geometry, argument map and token geometry.""" + return dict( + entry="cuda_dldn_engine_swin_dec0_kernel", + corpus="0023-PREPASS_ENTRYPOINT_NAME.ptx", + entry_lines=(1018, 47791), + role="first Swin decoder (encoders' outputs -> feature planes)", + # one warp per 8x8 token patch; blockDim 32x1x1 is a single wave, so no + # %tid.z term appears in any address + grid=(161, 93, 1), + block=(32, 1, 1), + wave=32, + blocks=14973, + token_patch=(8, 8), + param_bytes=152, + # param_0+80 is the block origin as a v2.u16 (s5, L1033); the token + # geometry is 1280x720 -> 161x93 patches of 8x8 + image=(1280, 736), + args=dict( + input=8, # u64, e4m3 input plane; read once, 24 ld.global.u32 + skip=24, # u64, e4m3 skip input; 24 ld.global.v2.u16 + weights=40, # u64, prepared weight image, 47376 bytes + plane=48, # u64, output e4m3 surface (see writes below) + origin=80, # v2.u16 block origin + texture_a=88, # u64, 18 tex.base.2d.v4.f16.f32 samples + texture_b=96, # u64, tex.base.2d.v4.f16.s32 at (x, y) + texture_c=104, # u64, tex.base.2d.v4.f16.s32 at (x, y) + surface_a=112, # u64, sust.b.2d.v4.b16.zero destination + coord_scale=136, # v2.f32, texture coordinate scale/origin + surface_b=144, # u64, sust.p.2d.v4.b32.zero destination + ), + # measured on the GPU: the launch dump files the 65,945,600-byte block + # that holds these pointers as arg008 at base+0x1cc0000, so a pointer at + # `block + N` is dumped at arg008[N + 0x1cc0000] + arena=dict( + dump_arg=8, + dump_offset=0x1CC0000, + dump_bytes=65945600, + input=30146560, # param+8 (Main's measurement, shared) + plane=45219840, # param+48 (measured here: the p1 oracle's + # payload at D4R_RRSWIN_DEBUG_BASE lands at + # arg008 offset 61,997,056, i.e. 45,219,840 + + # 16,777,216, and shifting the base by 8192 + # shifts the first differing byte by 8192) + param56=60293120, # param+56 (Main's measurement, shared) + ), + writes=( + # (statement, instruction, argument, address) + (18502, "st.global.v4.u16", 48, "4*(ex*y + x)"), # e4m3 planes + (18603, "sust.p.2d.v4.b32.zero", 144, "(x, y)"), # four f32 + (18813, "sust.b.2d.v4.b16.zero", 112, "(8*x, y)"), # texture fuse + ), + unverified="param_0+32, +56, +72, +120 and +128 are never read by the " + "entry; the 4-byte value of param+0 is the (ex, ey) extents " + "pair (s13), and the offset of param+48 inside its block is " + "the only arena figure measured for this layer.", + ) + + +def phases(): + """The 19 GEMM phases in program order, each with its epilogue.""" + return [p1(), p2(), p3(), p4(), p5(), p6(), p7(), p8(), p9(), p10(), + p11(), p12(), p13(), p14(), p15(), p16(), p17(), p18(), p19()] + + +# --------------------------------------------------------------------------- +# shared pieces +# --------------------------------------------------------------------------- + +def _e1(): + """E1: patch expand, skip residual, RMS norm. Returns the normalised tile.""" + return dict( + name="E1", + stmts=(422, 5936), + steps=[ + dict(op="requantise", detail="D1 (96 f16x2 registers, %r464..%r775 " + "written by the 96 mma) -> 37 `mov.b32` of two " + "cvt.rn.satfinite.e4m3x2.f16x2 each plus 3 v2 pairs; 4 e4m3 " + "codes per b32, the two codes of two adjacent n-tiles for one " + "row"), + dict(op="stage", detail="st.shared into the entry's 3200-byte smem as " + "two 400-cell planes of a 10x10 grid of 4-byte cells, cell = " + "row*40 + col*4 + t, plane stride 1600 bytes; 25 cells per lane " + "are written and all 800 cells are covered exactly once"), + dict(op="gather", detail="24 ld.shared.v2.u16 per lane at " + "cell = plane*400 + row*40 + col*4 + t with " + "col = (laneid>>2) + 1, for row = 1..8, 0, 9 in both planes, " + "then (row = col, col = 0) and (row = col, col = 9) in both " + "planes -- 24 v2 loads = 48 f16x2, one b16 per e4m3x2"), + dict(op="dequantise_skip", detail="24 ld.global.v2.u16 from param+24 " + "(s1613-s4384) then 96 cvt.rn.f16x2.e4m3x2"), + dict(op="add", detail="204 add.f16: staged patch + dequantised skip"), + dict(op="rms_norm", detail="mul.f16 squares, 60 add.f16x2 in-lane " + "sums, 24 shfl.sync.bfly.b32, + 2^-13 (mov.f64 0x3F20000000000000, " + "s5030), rsqrt.approx.ftz.f32, times the column gain read at " + "W + ((laneid<<2)&12) + {8448, 8464, 8480, 8496} (4 x " + "ld.global.v2.u16 = 8 f16 per lane = 32 columns). No mean " + "subtraction and no 1/N"), + dict(op="requantise", detail="48 cvt.rn.satfinite.e4m3x2.f16x2 " + "(s5860-s5928) -> 24 b32 = phases 2 and 3's A operand"), + ], + # the two registers E5 still reads after the softmax: the skip residual + # sums %rs425 / %rs428 (s4484/s4485), defined once here and read again at + # s10118 as phase 6's C seed + residual_registers=("%rs425", "%rs428"), + unverified="the lane -> (row, col) map of the staging and of the " + "gather was derived by executing the region s539-s1457 as " + "integer PTX for all 32 lanes; the resulting map is " + "self-consistent (exactly 800 distinct cells, one writer " + "each, every read cell written) but has not been checked " + "against NVIDIA's own values.", + ) + + +def _softmax(scale=0.017181396484375): + """The cubic-exponent softmax E4 and E9 use (identical code, shifted regs).""" + return dict( + clamp=(-0.55615234375, 0.55615234375), + scale=scale, + cube=dict(c0=0.92724609375, note="u = f16(1.375 + m*(c0 - m*m))"), + trick="expval = f16 from bits ((u_bits << 5) & 0x7FE07FE0), i.e. " + "2^(32*frac(u) - 47)", + row_sum="8 row sums (one per row g, g+8 of the four m-tiles) from 12 " + "add.f16x2 partials and 16 shfl.sync.bfly.b32; there is NO row " + "maximum in this epilogue, the max/min f16x2 are the clamp", + normalise="192 rcp.approx.ftz.f32 -> 96 reciprocals, then 192 mul.f16", + ) + + +def _activation(): + """The clamped cubic activation of E12, E14, E16 and E18.""" + return dict( + clamp=(-2.0, 2.0), + gain="g = f16(0.5 + y*(0.412109375 - 0.0810546875*|y|)) with " + "y = clamp(x, -2, 2), all in f16", + out="x * g, computed in f32 and rounded to f16", + note="a cubic ramp, not sigmoid/GELU: g(+2) = 1 so out = x above 2, " + "g(-2) = 0 so out = 0 below -2", + requantise="32 cvt.rn.satfinite.e4m3x2.f16x2 -> 16 b32 = the next " + "phase's A", + ) + + +# --------------------------------------------------------------------------- +# the phases +# --------------------------------------------------------------------------- + +def p1(): + return dict( + index=1, + stmts=(326, 421), lines=(1393, 2061), + gemm=dict(m_tiles=3, n_tiles=16, k=64, k_slices=2, mma=96, + mma_shape="m16n8k32", wmma_steps=4, + note="the tool prints 96x256 K=64; the 48 chains of two steps " + "reproduce 3*16*2 = 96, so N is 128 and the 32 B " + "fragments are 16 n-tiles x 2 k slices"), + mma_order="for mi in 0..2, for p in 0..7, for ks in 0..1, for j in 0..1: " + "a_fragment = 2*mi + ks, n_tile = 2*p + j, b_fragment = " + "4*p + 2*ks + j", + a=dict(source="arg+8 input plane, staged by NVIDIA's prologue into 24 " + "registers (%r756..%r759, %r776..%r779, %r1076..%r1079, " + "%r1096..%r1099, %r1396..%r1399, %r1416..%r1419) in mma first-use " + "order", fragments=6, registers=24, requantise="none: already e4m3"), + b=dict(source="weight image", base=0, + tile="k_slices*(nt>>1) + ks = 2*(nt>>1) + ks", + fragments=32, note="16 n-tiles x 2 k slices; the largest word " + "offset is 7688, so the phase reads [0, 7692)"), + c=dict(kind="per-n-tile f16x2 bias word", count=16, base=8192, stride=16, + addr="W + ((laneid<<2)&12) + 8192 + 16*nt", + regs=["%r1113", "%r1123", "%r1153", "%r1163", "%r1193", "%r1203", + "%r1233", "%r1243", "%r1273", "%r1283", "%r1313", "%r1323", + "%r1353", "%r1363", "%r1393", "%r1403"], + note="the first k step of each chain; the second reads the first " + "step's f16 result"), + d_registers=96, + epilogue=_e1(), + ) + + +def _proj(index, stmts, lines, a_source, a_registers, b_base, c, m_tiles, + n_tiles, epilogue, note=""): + """One K=32 projection: the shape of phases 2, 3, 6, 7, 8 and 11..19.""" + return dict( + index=index, stmts=stmts, lines=lines, + gemm=dict(m_tiles=m_tiles, n_tiles=n_tiles, k=32, k_slices=1, + mma=m_tiles * n_tiles, mma_shape="m16n8k32", wmma_steps=2, + note=note), + mma_order="for mi in 0..%d, for nt in 0..%d: a_fragment = mi, " + "n_tile = nt" % (m_tiles - 1, n_tiles - 1), + a=a_source, + b=dict(source="weight image", base=b_base, tile="(nt>>1)", + fragments=n_tiles, + span="[%d, %d)" % (b_base, b_base + 512 * ((n_tiles + 1) // 2))), + c=c, + d_registers=2 * m_tiles * n_tiles, + epilogue=epilogue, + ) + + +def _zero_c(): + return dict(kind="constant zero", regs=["%r13609"], + note="mov.u32 %r13609, 0 at L6552; the mma's C field is " + "{%r13609, %r13609}") + + +def _norm_tile_a(regs): + return dict(source="E1's normalised tile (the 24 packed b32 E1's last " + "requantise writes)", fragments=6, registers=24, regs=regs, + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E1") + + +def _bias_c(base, count, stride=16): + return dict(kind="per-n-tile f16x2 bias word", count=count, base=base, + stride=stride, + addr="W + ((laneid<<2)&12) + %d + %d*nt" % (base, stride)) + + +def _acc_c(src, regs, n_tiles, m_tiles): + return dict(kind="the previous phase's f16x2 accumulators", + count=2 * m_tiles * n_tiles, regs=regs, note=src) + + +def p2(): + return _proj(2, (5937, 5960), (10458, 10622), + _norm_tile_a(["%r9539", "%r9579", "%r9619", "%r9659", "%r9699", + "%r9739"]), + None, 8512, _zero_c(), 6, 4, + dict(name="E2", stmts=(5961, 5967), + steps=[dict(op="load", detail="phase 3's B, two " + "ld.weak.global.ca.v4 at W + 16*laneid + " + "{9536, 10048}")])) + + +def p3(): + return _proj(3, (5968, 5991), (10639, 10803), + _norm_tile_a(["%r9539", "%r9579", "%r9619", "%r9659", "%r9699", + "%r9739"]), + None, 9536, _zero_c(), 6, 4, + dict(name="E3", stmts=(5992, 6162), + steps=[ + dict(op="load", detail="phase 4's C bias: 24 " + "ld.weak.global.ca.v4 at " + "W + 16*laneid + 10560 + 512*i, i = 0..23 " + "= [10560, 22348)"), + dict(op="requantise", detail="phase 3's D (%r4904.." + "%r5135) -> 80 cvt.rn.satfinite.e4m3x2 in 40 " + "b32 = phase 4's A (16 b32) and B (24 b32)"), + ])) + + +def p4(): + return dict( + index=4, stmts=(6163, 6210), lines=(11188, 11520), + gemm=dict(m_tiles=4, n_tiles=12, k=32, k_slices=1, mma=48, + mma_shape="m16n8k32", wmma_steps=2, + note="the 64x96 score block of the first attention window"), + mma_order="for mi in 0..3, for nt in 0..11: a_fragment = mi, " + "n_tile = nt", + a=dict(source="E3's pack of phase 3's D", fragments=4, registers=16, + regs=["%r5433", "%r5553", "%r5673", "%r5793"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E3"), + b=dict(source="E3's pack of phase 2's D (the V of the first window)", + fragments=12, registers=24, + regs=["%r5687", "%r5697", "%r5707", "%r5717", "%r5727", "%r5737", + "%r5747", "%r5757", "%r5767", "%r5777", "%r5787", "%r5797"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E3"), + c=dict(kind="per-(m-tile, n-tile) f16x2 seed pair", count=48, + base=10560, span=(10560, 22348), + word_offset="base + 2048*(i >> 1) + 8*(i & 1) for mma index i, " + "the pair at +0 and +4", + addr="W + ((laneid<<2)&12) + word_offset", + note="the 12288-byte position bias of the first window; four " + "consecutive mma share a 512-byte stride"), + d_registers=96, + epilogue=dict( + name="E4", stmts=(6211, 10053), softmax=_softmax(), + steps=[ + dict(op="exponent", detail="96 element groups: " + "m = clamp(f16(x * 0.017181396484375), -0.55615234375, " + "+0.55615234375); u = f16(1.375 + m*(0.92724609375 - m*m)); " + "expval = f16 from bits ((u_bits << 5) & 0x7FE07FE0)"), + dict(op="row_sum", detail="12 add.f16x2 partials per lane, 16 " + "shfl.sync.bfly.b32, 8 row sums; no row maximum"), + dict(op="normalise", detail="192 rcp.approx.ftz.f32 -> 96 " + "reciprocals; 192 mul.f16 -> the 96 probabilities"), + dict(op="transpose", detail="48 movmatrix.sync.trans.aligned." + "m8n8.b16 over phase 2's D (the V matrix)"), + dict(op="requantise", detail="144 cvt.rn.satfinite.e4m3x2 in 48 " + "b32 = phase 5's A (48 b32, 4 m-tiles x 3 k slices) and B " + "(24 b32, 4 n-tiles x 3 k slices)"), + ]), + ) + + +def p5(): + return dict( + index=5, stmts=(10054, 10101), lines=(21667, 21999), + gemm=dict(m_tiles=4, n_tiles=4, k=96, k_slices=3, mma=48, + mma_shape="m16n8k32", wmma_steps=6, + note="16 chains of three steps; the tool prints 192x96 " + "because it attributes the k slices to M and N"), + mma_order="for mi in 0..3, for nt in 0..3, for ks in 0..2: " + "a_fragment = 3*mi + ks, b_fragment = 3*nt + ks", + a=dict(source="E4's pack of the softmax probabilities (P of the first " + "window)", fragments=12, registers=48, + regs=["%r8639", "%r8659", "%r8679", "%r8759", "%r8779", "%r8799", + "%r8879", "%r8899", "%r8919", "%r8999", "%r9019", "%r9039"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E4"), + b=dict(source="E4's pack of the transposed phase 2's D (the V matrix)", + fragments=12, registers=24, + regs=["%r8933", "%r8943", "%r8953", "%r8963", "%r8973", "%r8983", + "%r8993", "%r9003", "%r9013", "%r9023", "%r9033", "%r9043"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E4"), + c=dict(kind="zero then the chain's own accumulator", count=1, + regs=["%r13609"], + note="ks = 0 reads {%r13609, %r13609}; ks > 0 reads the previous " + "step's D pair"), + d_registers=96, + epilogue=dict( + name="E5", stmts=(10102, 10261), + steps=[ + dict(op="load", detail="phase 6's B, two v4 at " + "W + 16*laneid + {22848, 23360}"), + dict(op="table", detail="phase 6's column table: four " + "ld.global.v2.u16 at W + ((laneid<<2)&12) + " + "{39232, 39248, 39264, 39280} = 8 f16 = 32 columns"), + dict(op="add", detail="64 add.f16: table[column] + the E1 " + "residual %rs425 / %rs428 (defined at s4484/s4485, the only " + "definition in the entry), giving phase 6's C operand"), + dict(op="requantise", detail="32 cvt.rn.satfinite.e4m3x2 of " + "phase 5's D -> 16 b32 = phase 6's A"), + ]), + ) + + +def p6(): + return _proj( + 6, (10262, 10277), (22427, 22535), + dict(source="E5's pack of phase 5's D (P*V of the first window)", + fragments=4, registers=16, regs=["%r9121", "%r9161", "%r9201", + "%r9241"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E5"), + None, 22848, + _acc_c("E1's skip residual plus the per-column table at W + 39232", + ["%r9097", "%r9107", "%r9117", "%r9127", "%r9137", "%r9147", + "%r9157", "%r9167", "%r9177", "%r9187", "%r9197", "%r9207", + "%r9217", "%r9227", "%r9237", "%r9247"], 4, 4), + 4, 4, + dict(name="E6", stmts=(10278, 10284), + steps=[dict(op="load", detail="phase 7's B at " + "W + 16*laneid + {23872, 24384}")])) + + +def p7(): + return _proj( + 7, (10285, 10308), (22552, 22716), + _norm_tile_a(["%r9539", "%r9579", "%r9619", "%r9659", "%r9699", "%r9739"]), + None, 23872, _zero_c(), 6, 4, + dict(name="E7", stmts=(10309, 10315), + steps=[dict(op="load", detail="phase 8's B at " + "W + 16*laneid + {24896, 25408}")])) + + +def p8(): + return _proj( + 8, (10316, 10339), (22733, 22897), + _norm_tile_a(["%r9539", "%r9579", "%r9619", "%r9659", "%r9699", "%r9739"]), + None, 24896, _zero_c(), 6, 4, + dict(name="E8", stmts=(10340, 10510), + steps=[ + dict(op="load", detail="phase 9's C bias: 24 v4 at " + "W + 16*laneid + 25920 + 512*i, i = 0..23 = [25920, 37708)"), + dict(op="requantise", detail="phase 8's D (%r9507..%r9737) -> " + "80 cvt.rn.satfinite.e4m3x2 in 40 b32 = phase 9's A (16) " + "and B (24)"), + ])) + + +def p9(): + out = dict(p4()) + out.update(index=9, stmts=(10511, 10558), lines=(23282, 23614)) + out["gemm"] = dict(p4()["gemm"], note="the 64x96 score block of the second " + "attention window") + out["a"] = dict(p4()["a"], source="E8's pack of phase 8's D", + regs=["%r10036", "%r10156", "%r11036", "%r11156"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E8") + out["b"] = dict(p4()["b"], source="E8's pack of phase 7's D (the V of the " + "second window)", + regs=["%r11287", "%r11397", "%r11507", "%r11617", "%r11727", + "%r11837", "%r11947", "%r12057", "%r12167", "%r12277", + "%r12387", "%r12497"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E8") + out["c"] = dict(p4()["c"], base=25920, span=(25920, 37708), + note="the second window's 12288-byte position bias") + out["epilogue"] = dict(name="E9", stmts=(10559, 14396), softmax=_softmax(), + steps=[ + dict(op="exponent", detail="identical code to " + "E4's, registers shifted; 96 element groups"), + dict(op="row_sum", detail="12 add.f16x2 partials, " + "16 shfl.sync.bfly.b32, 8 row sums"), + dict(op="normalise", detail="192 rcp.approx." + "ftz.f32 then 192 mul.f16"), + dict(op="transpose", detail="48 movmatrix.sync." + "trans.aligned.m8n8.b16 over phase 7's D"), + dict(op="requantise", detail="144 " + "cvt.rn.satfinite.e4m3x2 in 48 b32 = " + "phase 10's A (48) and B (24)"), + ]) + return out + + +def p10(): + out = dict(p5()) + out.update(index=10, stmts=(14397, 14444), lines=(33756, 34088)) + out["gemm"] = dict(p5()["gemm"], note="P*V of the second attention window") + out["a"] = dict(p5()["a"], source="E9's pack of the second window's " + "probabilities", + regs=["%r13242", "%r13262", "%r13282", "%r13302", "%r13322", + "%r13342", "%r13362", "%r13382", "%r13402", "%r13422", + "%r13442", "%r13462"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E9") + out["b"] = dict(p5()["b"], source="E9's pack of the transposed phase 7's D", + regs=["%r13933", "%r13943", "%r13953", "%r13963", "%r13973", + "%r13983", "%r13993", "%r14003", "%r14013", "%r14023", + "%r14033", "%r14043"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E9") + out["epilogue"] = dict(name="E10", stmts=(14445, 14499), steps=[ + dict(op="load", detail="phase 11's B at W + 16*laneid + {38208, 38720}"), + dict(op="requantise", detail="32 cvt.rn.satfinite.e4m3x2 of phase 10's " + "D -> 16 b32 = phase 11's A; no column table"), + ], note="phase 11's C is phase 6's accumulator (the residual), so phase 11 " + "computes D11 = A11*B11 + D6") + return out + + +def p11(): + return _proj( + 11, (14500, 14515), (34217, 34325), + dict(source="E10's pack of phase 10's D", fragments=4, registers=16, + regs=["%r13723", "%r13763", "%r13803", "%r13843"], + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in E10"), + None, 38208, + _acc_c("phase 6's accumulators (the running residual)", + ["%r9089", "%r9099", "%r9109", "%r9119", "%r9129", "%r9139", + "%r9149", "%r9159", "%r9169", "%r9179", "%r9189", "%r9199", + "%r9209", "%r9219", "%r9229", "%r9239"], 4, 4), + 4, 4, + dict(name="E11", stmts=(14516, 15402), op="rms_norm", + steps=[ + dict(op="squares", detail="192 mul.f16 of phase 11's D"), + dict(op="sum", detail="16 add.f16x2 in-lane, 16 " + "shfl.sync.bfly.b32 + add.f16 across the four lanes"), + dict(op="scale", detail="+ 2^-13 then rsqrt.approx.ftz.f32, 64 " + "cvt.f32.f16 / rsqrt / cvt.rn.f16.f32, rounded to f16"), + dict(op="gain", detail="times the column gain at " + "W + ((laneid<<2)&12) + {39296, 39312, 39328, 39344}; " + "192 mul.f16 (inv*gain, then x*(inv*gain))"), + dict(op="load", detail="phase 12's B at W + 16*laneid + " + "{39360, 39872} and its C bias at " + "W + ((laneid<<2)&12) + {40384, 40400, 40416, 40432}"), + dict(op="requantise", detail="32 cvt.rn.satfinite.e4m3x2 -> " + "16 b32 = phase 12's A"), + ], + note="no mean subtraction and no 1/N; the normalised tile N (32 " + "f16x2) is also what E13, E15 and E17 repack, so phases 12, " + "14, 16 and 18 all take the same A operand")) + + +def _mlp_a(source, regs, note=""): + return dict(source=source, fragments=4, registers=16, regs=regs, + requantise="cvt.rn.satfinite.e4m3x2.f16x2 in the preceding " + "epilogue", note=note) + + +N_REGS = ["%r15544", "%r15584", "%r15624", "%r15664"] # E13's pack of N +ACT14 = ["%r16674", "%r16714", "%r16754", "%r16794"] # E14's pack +ACT16 = ["%r16876", "%r16916", "%r16956", "%r16996"] # E15's pack of N +ACT17 = ["%r18006", "%r18046", "%r18086", "%r18126"] # E16's pack +ACT18 = ["%r18208", "%r18248", "%r18288", "%r18328"] # E17's pack of N +ACT19 = ["%r19338", "%r19378", "%r19418", "%r19458"] # E18's pack + + +def p12(): + return _proj( + 12, (15403, 15418), (36471, 36579), + _mlp_a("E11's pack of the RMS-normed tile N", + ["%r14211", "%r14251", "%r14291", "%r14331"]), + None, 39360, _bias_c(40384, 4), 4, 4, + dict(name="E12", stmts=(15419, 16127), activation=_activation(), + steps=[ + dict(op="activate", detail="over each of phase 12's 32 f16x2 D " + "registers: y = clamp(x, -2, 2), " + "g = 0.5 + y*(0.412109375 - 0.0810546875*|y|), out = x*g, " + "with 128 cvt.rn.f16.f32, 32 each neg/max/min/abs.f16x2, " + "96 mul.f16x2, 32 sub.f16x2, 32 add.f16x2"), + dict(op="table", detail="64 add.f16 of the column table read at " + "W + ((laneid<<2)&12) + {41472, 41488, 41504, 41520}, " + "written over the *activation inputs*, so phase 13's " + "activation input is D12 + table[column]"), + dict(op="load", detail="phase 13's B at W + 16*laneid + " + "{40448, 40960}"), + dict(op="requantise", detail="32 packs of the activation " + "outputs -> 16 b32 = phase 13's A"), + ], + note="the only one of the four branches with a per-column table")) + + +def p13(): + return _proj( + 13, (16128, 16143), (38934, 39042), + _mlp_a("E12's pack of the activated (and table-added) tile", + ["%r15342", "%r15382", "%r15422", "%r15462"]), + None, 40448, + _acc_c("phase 12's accumulators plus the per-column table at W + 41472, " + "i.e. the values E12 wrote over the activation inputs", + ["%r15269", "%r15329", "%r15389", "%r15449", "%r15509", "%r15569", + "%r15629", "%r15689", "%r15749", "%r15809", "%r15869", "%r15929", + "%r15989", "%r16049", "%r16109", "%r16169"], 4, 4), + 4, 4, + dict(name="E13", stmts=(16144, 16207), steps=[ + dict(op="load", detail="phase 14's B at W + 16*laneid + {41536, " + "42048} and its C bias at W + ((laneid<<2)&12) + " + "{42560, 42576, 42592, 42608}"), + dict(op="requantise", detail="32 packs of the *normed tile* N (not " + "of phase 13's D) -> 16 b32 = phase 14's A"), + ])) + + +def p14(): + return _proj( + 14, (16208, 16223), (39182, 39290), + _mlp_a("E13's pack of the RMS-normed tile N", N_REGS, + note="the same 16 registers as phase 16's A"), + None, 41536, _bias_c(42560, 4), 4, 4, + dict(name="E14", stmts=(16224, 16823), activation=_activation(), + steps=[ + dict(op="activate", detail="the same clamped cubic as E12, over " + "phase 14's own D; no ld.global and no table add"), + dict(op="load", detail="phase 15's B at W + 16*laneid + " + "{42624, 43136}"), + dict(op="requantise", detail="32 packs of the activation " + "outputs -> 16 b32 = phase 15's A"), + ])) + + +def p15(): + return _proj( + 15, (16824, 16839), (41342, 41450), + _mlp_a("E14's pack of the activated tile", ACT14), None, 42624, + _bias_c(44672, 4), 4, 4, + dict(name="E15", stmts=(16840, 16903), steps=[ + dict(op="load", detail="phase 16's B at W + 16*laneid + {43648, " + "44160} and its C bias at W + ((laneid<<2)&12) + " + "{44672, 44688, 44704, 44720}"), + dict(op="requantise", detail="32 packs of the normed tile N -> " + "16 b32 = phase 16's A"), + ])) + + +def p16(): + return _proj( + 16, (16904, 16919), (41590, 41698), + _mlp_a("E15's pack of the RMS-normed tile N", ACT16), None, 43648, + _bias_c(46784, 4), 4, 4, + dict(name="E16", stmts=(16920, 17519), activation=_activation(), + steps=[ + dict(op="activate", detail="the same clamped cubic as E12, over " + "phase 16's own D"), + dict(op="load", detail="phase 17's B at W + 16*laneid + " + "{44736, 45248}"), + dict(op="requantise", detail="32 packs of the activation " + "outputs -> 16 b32 = phase 17's A"), + ])) + + +def p17(): + return _proj( + 17, (17520, 17535), (43750, 43858), + _mlp_a("E16's pack of the activated tile", ACT17), None, 44736, + _bias_c(42560, 4) if False else dict( + kind="per-n-tile f16x2 bias word", count=4, base=46784, stride=16, + addr="W + ((laneid<<2)&12) + 46784 + 16*nt", + note="phase 17's C is read in E17 as " + "W + ((laneid<<2)&12) + {46784, 46800, 46816, 46832}"), + 4, 4, + dict(name="E17", stmts=(17536, 17599), steps=[ + dict(op="load", detail="phase 18's B at W + 16*laneid + {45760, " + "46272} and its C bias at W + ((laneid<<2)&12) + " + "{46784, 46800, 46816, 46832}"), + dict(op="requantise", detail="32 packs of the normed tile N -> " + "16 b32 = phase 18's A"), + ])) + + +def p18(): + return _proj( + 18, (17600, 17615), (43998, 44106), + _mlp_a("E17's pack of the RMS-normed tile N", ACT18), None, 45760, + _bias_c(46784, 4), 4, 4, + dict(name="E18", stmts=(17616, 18215), activation=_activation(), + steps=[ + dict(op="activate", detail="the same clamped cubic as E12, over " + "phase 18's own D; this is the last requantisation in " + "the entry"), + dict(op="load", detail="phase 19's B at W + 16*laneid + " + "{46848, 46960}"), + dict(op="requantise", detail="32 packs of the activation " + "outputs -> 16 b32 = phase 19's A"), + ])) + + +def p19(): + return _proj( + 19, (18216, 18231), (46158, 46266), + _mlp_a("E18's pack of the activated tile", ACT19), None, 46848, + _acc_c("phase 18's accumulators", + ["%r19089", "%r19149", "%r19209", "%r19269", "%r19329", "%r19389", + "%r19449", "%r19509"], 4, 2), + 4, 4, + dict(name="E19", stmts=(18232, 19160), + note="the final epilogue stays NVIDIA's in the mirror cut; it is " + "described here because the engine's output feeds it", + steps=[ + dict(op="row_max", detail="a real row maximum (unlike E4's): a " + "selp chain over laneid&3 picks one of the four D pairs " + "per lane, then four shfl.sync.idx.b32 with " + "srcLane = (laneid&7) | ((((laneid>>3)+d)&3)<<2) for " + "d = 0,1,2,-1, then a selp chain over laneid>>3; max.f16x2 " + "/ max.f16 and sub.f16x2 subtract it"), + dict(op="bounds", detail="ld.param.v2.u32 at param+0 gives " + "(ex, ey); out-of-range lanes branch to $L__BB1_367 and " + "skip the rest"), + dict(op="surface1", detail="4 cvt.rn.satfinite.e4m3x2 and one " + "st.global.v4.u16 at 4*(ex*y + x) into param+48"), + dict(op="surface2", detail="per element v: a " + "1 - 2/(1 + 2^(|v|*log2e)) branch (with a hard 1.0 above " + "9.0109...) and an fma polynomial over v^2 selected by " + "|v| >= 0.6, then sust.p.2d.v4.b32.zero at (x, y) into " + "param+144"), + dict(op="softmax", detail="x - max in f16, 2^((x-max)*log2e) " + "in f32, an f32 row sum, div.approx.ftz.f32 by 1.0, five " + "mul.f16x2"), + dict(op="texture_fuse", detail="18 tex.base.2d.v4.f16.f32 of " + "param+88 at f32 coordinates built from param+136, plus " + "tex.base.2d.v4.f16.s32 of param+96 and param+104 at " + "integer (x, y); folded with fma.rn.f16, guarded by " + "set.nan.f16.f16 / setp.ne.s16 so a NaN sample is " + "skipped, written by sust.b.2d.v4.b16.zero at (8*x, y) " + "into param+112 with a constant 0 fourth channel"), + ], + unverified="E19's two evaluation branches are exact in the PTX " + "(every instruction is cited) but which model function " + "they implement is not determinable from it."), + ) + + + + + + +def _final(): + return None diff --git a/kernels/rr/descriptor_dec1.py b/kernels/rr/descriptor_dec1.py new file mode 100755 index 0000000..76b866d --- /dev/null +++ b/kernels/rr/descriptor_dec1.py @@ -0,0 +1,432 @@ +#!/usr/bin/env python3 +"""Per-layer descriptor for cuda_dldn_engine_swin_dec1_kernel (nvngx_dlssd 310.7). + +The parameterised-engine deliverable: every number here is either (a) read out of +~/.cache/d4r-rr-corpus/0022-PREPASS_ENTRYPOINT_NAME.ptx, entry +`cuda_dldn_engine_swin_dec1_kernel`, and reproducible with + + python3 kernels/rr/rr_layer_spec.py dec1 + +or (b) marked `"unverified"` with the reason. Phase boundaries, mma operand +register lists and the weight-image offsets were extracted mechanically from the +linearised statement list; the epilogue operations are named from +kernels/rr/rrswin_dec1_epilogues.md, which cites the statement ranges. + +Geometry recovered by interpreting NVIDIA's own index arithmetic (not guessed) +is recorded in `e1_patch_grid`. + + python3 -c "import descriptor_dec1 as d; print(d.layer())" +""" + +# --------------------------------------------------------------------------- +# launch geometry, from the entry's prologue (s1-s325) and rr_layer_spec.py +# --------------------------------------------------------------------------- + +def layer(): + """Launch geometry, parameter-block layout and tile shape. + + `param_offsets` are byte offsets into the 144-byte parameter block; the entry + declares it as one `.param .align 8 .b8 ..._param_0[144]`, so every offset below + is a plain byte read (`rr_layer_spec.py dec1`: "param block 144 bytes (5 + ld.param over 3 distinct offsets)", "param offsets [8, 40, 80]"). + """ + return { + "kernel": "cuda_dldn_engine_swin_dec1_kernel", + "corpus": "0022-PREPASS_ENTRYPOINT_NAME.ptx", + "grid": (81, 47, 1), + "block": (32, 1, 2), # two waves per block; %tid.z is the window index + "waves": 2, + "laneid": 32, + "param_block_bytes": 144, + "param_offsets": { + 0: {"kind": "u32x2", "name": "extents", "meaning": "ex, ey"}, + 8: {"kind": "ptr", "name": "in_plane", + "meaning": "input feature plane arena, 52 ld.global.u32 in the prologue"}, + 24: {"kind": "ptr", "name": "patch_gather", + "meaning": "the +24 skip input E1 gathers the patch from; reached as " + "[param_0+80 - 56], not as its own ld.param"}, + 40: {"kind": "ptr", "name": "weights", + "meaning": "NVIDIA's prepared weight image (arg040, 96,800 bytes)"}, + 48: {"kind": "ptr", "name": "out_plane", + "meaning": "output plane arena; E25's 16 guarded st.global.u32 write here"}, + 80: {"kind": "v2u16", "name": "block_origin", + "meaning": "the per-block origin table; %rd1 = param_0+80 and " + "param_0+24 is [rd1-56]"}, + 88: {"kind": "tex", "name": "colour_tex"}, + 96: {"kind": "tex", "name": "tex_int_0"}, + 104: {"kind": "tex", "name": "tex_int_1"}, + 112: {"kind": "surface", "name": "surface_0"}, + 120: {"kind": "surface", "name": "surface_1"}, + 136: {"kind": "f32x2", "name": "tex_coord_scale"}, + }, + "tid_z_strides": { + # two per-tid.z strides exist and are used by different groups + # (rrswin_dec1_epilogues.md §1.1, read off the load chains). + "phase1_B": {"bytes": 12288, "phase": 1}, + "phase1_bias": {"bytes": 256, "phase": 1}, + "phase2_5_B_and_phase6_bias": {"bytes": 18432, "phases": [2, 3, 4, 5, 6]}, + }, + "tid_z_range": [0, 1], + "shared_bytes": 6400, + "token_geometry": { + "patch": "8x8 tokens per warp; a 10x10 halo grid of 4-word cells", + "unverified": "the 10x10 grid's mapping to image coordinates was not " + "reduced to a closed form; see e1_patch_grid for what the " + "interpreter measured and rrswin_dec1_epilogues.md U4 for " + "what remains open.", + }, + "constants_f16": { + # §1.2: value after the cvt to f16, i.e. what the arithmetic actually uses + "softsign_scale": 0x2466, # 0.017181396484375 + "clamp_lo": 0xB873, # -0.55615234375 + "clamp_hi": 0x3873, # +0.55615234375 + "cubic_a": 0x3B6B, # 0.92724609375 + "cubic_b": 0x3D80, # 1.375 + "rms_eps": 0x0800, # 2^-13 + "act_a": 0x3698, # 0.412109375 + "act_b": 0x2D30, # 0.0810546875 + "act_half": 0x3800, # 0.5 + "act_two": 0x4000, # 2.0 + }, + } + + +# --------------------------------------------------------------------------- +# E1's patch grid, recovered by interpreting the PTX +# --------------------------------------------------------------------------- + +def e1_patch_grid(): + """The 6400-byte shared tile E1 builds and reads, as measured. + + `/tmp/d4r-dec1/interp.py` evaluates NVIDIA's own index arithmetic for all 32 + lanes x tid.z in {0,1} over s689-s1367 (the 48 guarded `st.shared`) and + s1370-s2214 (the 24 `ld.shared.v2.u16`). The layout below is that output, + not an inference. + """ + return { + "sub_arrays": 4, + "sub_array_bytes": 1600, + "word_index": "sub*400 + row*40 + col*4 + t (row 0..9, col 0..9, t = laneid&3)", + "grid": "10 rows x 10 cols x 4 words", + "pack_index": "p = 16*mgrp + 4*(gp>>1) + 2*h + row; " + "pk[p] = e4m3x2(D[mgrp][2q][j=2][h][row]) " + "| e4m3x2(D[mgrp][2q+1][j=2][h][row])<<16, q = gp>>1", + "live_packs": [p for p in range(48) if p not in + (33, 35, 37, 39, 41, 43, 45, 47)], + "row_parity": {"tid_z_0": [1, 3, 5, 7, 9], "tid_z_1": [0, 2, 4, 6, 8]}, + "coverage": "the 48 stores tile all 400 cells exactly once, zero duplicates", + "cells_per_g_tid_z_0": [28, 28, 28, 24, 20, 20, 24, 28], + "cells_per_g_tid_z_1": [24, 28, 28, 28, 28, 24, 20, 20], + "readback_positions": { + "count": 24, + "note": "6 grid positions x 4 sub-arrays", + "tid_z_0": "rows {1,2,3,4,0,9} at column g+1", + "tid_z_1": "rows {5,6,7,8} at column g+1, plus column halos " + "(g+1,0) and (g+1,9)", + }, + "unverified": "the gather source arithmetic (param_0+24, index " + "clamp_row*(8*ex) + clamp_col*8 + clamp(t,0,7)), the " + "sum-of-squares trees and the restage were not decoded; the " + "epilogue cites them at s2215-s7095.", + } + + +# --------------------------------------------------------------------------- +# the 26 phases +# --------------------------------------------------------------------------- + +def _gemm(mt, nt, k, mma, a, b, c, ksplit=None): + d = { + "m_tiles": mt, "n_tiles": nt, "k": k, "mma": mma, + "a": a, "b": b, "c": c, + "k_tiling": ksplit or "one 32-wide k step; the engine emits two 16-wide " + "gfx12 WMMA steps in NVIDIA's slot order", + } + return d + + +# Weight-image byte offsets are relative to W (param_0+40). `tid_z` says whether +# the offset carries a per-tid.z stride and which one. +_PATCH = "E1's restaged patch grid (shared), m-tile index selects the A fragment" +_NORMT = "the RMS-normalised tile N of E9 (32 f16x2), requantised to e4m3" + + +def phases(): + """One dict per phase, in execution order. + + `m_tiles`, `n_tiles`, `k` and `mma` are exact: `mma` is the statement count and + the tiles come from counting the distinct A quads and B pairs the phase's mma + read (rr_layer_spec.py's phase table). `a`, `b`, `c` name the operand's source; + where the source is a weight-image read the byte offset and the per-tid.z + stride are given. + """ + out = [] + P = out.append + + P(dict( + index=1, stmts=(403, 546), epilogue="E1", epilogue_stmts=(547, 7095), + gemm=_gemm(9, 48, 96, 144, + {"source": "the staged 8x8 block patch (param_0+8)", + "operands": "9 .f16.e4m3 fragments of four b32, 36 registers, " + "passed across the cut", + "requantise": "already e4m3"}, + {"source": "weight image", + "byte_offset": 0, "byte_span": 11788, "stride": "12288 * tid.z", + "note": "48 B fragments = 24 blocks x 16 columns; banded, the " + "three m-groups are a running sum along j, not a " + "k-accumulation"}, + {"source": "per-chain bias seed", + "byte_offset": 24576, "byte_span": 240, "stride": "256 * tid.z", + "kind": "per-(chain, n-tile) seed pair broadcast into both C registers"}, + ))) + + # ---- the four 96x32 projections ------------------------------------------------- + for idx, a_mt, b_off, c_src in ( + (2, [0, 2, 4, 6, 8, 10], 0, "zero"), + (3, [0, 2, 4, 6, 8, 10], 2048, "zero"), + (4, [1, 3, 5, 7, 9, 11], 1024, "phase 2"), + (5, [1, 3, 5, 7, 9, 11], 3072, "phase 3")): + st = {2: (7096, 7119), 3: (7127, 7150), 4: (7158, 7181), 5: (7189, 7212)}[idx] + P(dict( + index=idx, stmts=st, epilogue="E%d" % (idx + 1 if idx in (2, 3) else idx), + gemm=_gemm(6, 4, 32, 24, + {"source": _PATCH, "m_tiles_used": a_mt, + "requantise": "already e4m3 (read back from shared by E1)"}, + {"source": "weight image", + "byte_offset": 25216 + b_off, "byte_span": 1024, + "stride": "18432 * tid.z"}, + {"source": c_src, + "kind": "per-(m,n) seed pair" if c_src != "zero" else "zero register"}, + ))) + + P(dict( + index=6, stmts=(7384, 7431), epilogue="E6", epilogue_stmts=(7432, 11274), + gemm=_gemm(4, 12, 32, 48, + {"source": "E5's pack of phase 2's and phase 3's accumulators", + "requantise": "cvt.rn.satfinite.e4m3x2.f16x2 then mov.b32"}, + {"source": "E5's second pack stream of the same two accumulators", + "weight_bytes": None, + "note": "phase 6 reads no weight image at all (phase table: " + "weight column `-` for every mma)"}, + {"source": "the score bias", + "byte_offset": 29312, "byte_span": 12288, "stride": "18432 * tid.z", + "kind": "per-(m,n) seed pair, 24 tiles x 512 bytes"}, + ))) + + P(dict( + index=7, stmts=(11275, 11322), epilogue="E7", epilogue_stmts=(11323, 11505), + gemm=_gemm(12, 12, 96, 48, + {"source": "E6's pack of the softmax probabilities", + "requantise": "cvt.rn.satfinite.e4m3x2.f16x2"}, + {"source": "E6's movmatrix.trans of phase 5's D", + "weight_bytes": None, + "note": "48 movmatrix.sync.trans.aligned.m8n8.b16 at s11011-s11058, " + "inputs are exactly phase 5's 48 D registers (%r6715..%r6946)"}, + {"source": "zero"}, + ), + )) + + P(dict( + index=8, stmts=(11506, 11521), epilogue="E8", epilogue_stmts=(11522, 11537), + gemm=_gemm(2, 8, 32, 16, + {"source": "shared, E7's pack of phase 7's D at offsets 0/512/1024/1536"}, + {"source": "weight image", "byte_offset": 41600, "byte_span": 1548}, + {"source": "phase 7's D plus the per-column table", + "byte_offset": 62080, "byte_span": 112, + "kind": "per-column f16 pair, 8 words per lane"}, + ))) + + P(dict( + index=9, stmts=(11538, 11553), epilogue="E9", epilogue_stmts=(11554, 12396), + gemm=_gemm(2, 8, 32, 16, + {"source": "shared, offsets +2048 and +2560"}, + {"source": "weight image", "byte_offset": 60032, "byte_span": 1548}, + {"source": "zero"}, + ))) + + # ---- the MLP band, phases 10..25 ------------------------------------------------ + # Odd phases are the 32x64 projections whose C is zero; even phases are the + # 64x64 ones whose C is a bias. Every odd phase's A is the same normalised tile N. + band = [ + # (index, m_tiles, n_tiles, k, mma, weight_off, c_off, c_kind) + (10, 4, 8, 64, 16, 62336, 64384, "per-(m,n) seed pair"), + (11, 2, 8, 32, 16, 64448, None, "zero"), + (12, 4, 8, 64, 16, 66624, 68672, "per-(m,n) seed pair"), + (13, 2, 8, 32, 16, 68736, None, "zero"), + (14, 4, 8, 64, 16, 70784, 72832, "per-(m,n) seed pair"), + (15, 2, 8, 32, 16, 72896, None, "zero"), + (16, 4, 8, 64, 16, 74944, 76992, "per-(m,n) seed pair"), + (17, 2, 8, 32, 16, 77056, None, "zero"), + (18, 4, 8, 64, 16, 79104, 81152, "per-(m,n) seed pair"), + (19, 2, 8, 32, 16, 81216, None, "zero"), + (20, 4, 8, 64, 16, 83264, 85312, "per-(m,n) seed pair"), + (21, 2, 8, 32, 16, 85376, None, "zero"), + (22, 4, 8, 64, 16, 87424, 89472, "per-(m,n) seed pair"), + (23, 2, 8, 32, 16, 89536, None, "zero"), + (24, 4, 8, 64, 16, 91584, 93632, "per-(m,n) seed pair"), + (25, 2, 8, 32, 16, 93696, None, "zero"), + ] + stmts = {10: (12397, 12412), 11: (12834, 12849), 12: (12918, 12933), + 13: (13242, 13257), 14: (13326, 13341), 15: (13650, 13665), + 16: (13734, 13749), 17: (14058, 14073), 18: (14142, 14157), + 19: (14466, 14481), 20: (14550, 14565), 21: (14874, 14889), + 22: (14958, 14973), 23: (15282, 15297), 24: (15366, 15381), + 25: (15690, 15705)} + epi = {10: "E10", 11: "E11", 12: "E12", 13: "E13", 14: "E14", 15: "E15", + 16: "E16", 17: "E17", 18: "E18", 19: "E19", 20: "E20", 21: "E21", + 22: "E22", 23: "E23", 24: "E24", 25: "E25"} + for idx, mt, nt, k, mma, w, c, ckind in band: + even = idx % 2 == 0 + P(dict( + index=idx, stmts=stmts[idx], epilogue=epi[idx], + gemm=_gemm(mt, nt, k, mma, + {"source": _NORMT, + "note": "every odd phase packs the same 32 f16x2 tile N; " + "E11/E13/E15/E17/E19/E21/E23 re-pack the identical " + "registers %r17567..%r17598", + "requantise": "cvt.rn.satfinite.e4m3x2.f16x2"}, + {"source": "weight image", "byte_offset": w, "byte_span": 1548, + "stride": None}, + {"source": "bias" if even else "zero", + "byte_offset": c, "kind": ckind} if even else + {"source": "zero"}, + ), + )) + + P(dict( + index=26, stmts=(15981, 15988), epilogue="E26", epilogue_stmts=(15989, 16304), + gemm=_gemm(4, 4, 64, 8, + {"source": "E25's requantised words %r489..%r504, scattered to " + "param_0+48 and read back as P26's A", + "requantise": "24 groups of 2 cvt + 1 mov.b32 at s15706-s15753"}, + {"source": "weight image", "byte_offset": 95744, "byte_span": 524}, + {"source": "bias", "byte_offset": 96768, "byte_span": 16, + "kind": "per-(m,n) seed pair"}, + ), + )) + + return out + + +# --------------------------------------------------------------------------- +# the epilogues, as an operation list the engine can dispatch on +# --------------------------------------------------------------------------- + +def epilogues(): + """name -> the operations it performs, with the offsets that carry them. + + Operation names are the engine's vocabulary: e4m3_requantise, pack_next_A, + clamped_cubic_activation, add_column_table, rms_norm, softmax, patch_expand, + plane_scatter, lane_merge, surface_scatter. + """ + return { + "E1": {"after": 1, "stmts": (547, 7095), "ops": [ + {"op": "e4m3_requantise", "src": "phase 1's D", "count": 144, + "dst": "shared, 10x10x4 grid (see e1_patch_grid)"}, + {"op": "patch_expand", "grid": [10, 10], "words_per_cell": 4}, + {"op": "gather", "arg": 24, "index": "clamp_row*(8*ex) + clamp_col*8 + clamp(t,0,7)", + "stride_bytes": 4, "count": 24}, + {"op": "e4m3_unpack", "count": 96}, + {"op": "rms_norm", "eps": "2^-13", "reduction": "4-lane butterfly over laneid&3", + "gain_byte_offset": 25088, "gain_span": 112, + "note": "raw sum of squares + eps, no mean subtraction and no 1/N; " + "applied per column"}, + {"op": "pack_next_A", "dst": "shared", "tiles": [0, 512, 1024, 1536, 4096, 4608], + "base": "tid.z*2048 + laneid*16", "guarded_by": "tid.z*16 < 32"}, + {"op": "lane_merge", "note": "tid.z*2048 splits the two waves' A tiles; " + "each wave reads the other's"}, + {"op": "load_B", "byte_offset": 25216, "stride": "18432 * tid.z"}, + ]}, + "E2": {"after": 2, "ops": [{"op": "load_B", "byte_offset": 25216 + 2048, + "span": 1024, "stride": "18432 * tid.z"}]}, + "E3": {"after": 3, "ops": [{"op": "load_B", "byte_offset": 25216 + 1024, + "span": 1024, "stride": "18432 * tid.z"}]}, + "E4": {"after": 4, "ops": [{"op": "load_B", "byte_offset": 25216 + 3072, + "span": 1024, "stride": "18432 * tid.z"}]}, + "E5": {"after": 5, "stmts": (7213, 7383), "ops": [ + {"op": "load_bias", "byte_offset": 29312, "span": 12288, + "stride": "18432 * tid.z", "dst": "phase 6's C"}, + {"op": "e4m3_requantise", "src": "phase 2's and phase 3's D", "count": 80, + "dst": "phase 6's A (80 regs) and B (80 regs)"}, + ]}, + "E6": {"after": 6, "stmts": (7432, 11274), "ops": [ + {"op": "softmax", "form": "cubic exponent, no row maximum, no bias add", + "scale": 0.017181396484375, "clamp": [-0.55615234375, 0.55615234375], + "cubic": [0.92724609375, 1.375], + "note": "expval = f16 from bits ((u<<5) & 0x7FE07FE0); the 8 row sums come " + "from two shfl.sync.bfly steps"}, + {"op": "lane_merge", "note": "48 movmatrix.sync.trans.aligned.m8n8.b16 of " + "phase 5's D"}, + {"op": "e4m3_requantise", "src": "the probabilities and the transposed V", + "count": 144, "dst": "phase 7's A and B"}, + ]}, + "E7": {"after": 7, "ops": [ + {"op": "e4m3_requantise", "count": 32, "dst": "shared"}, + {"op": "lane_merge", "note": "pack D7 to shared, bar.sync, read back as phase 8's A"}, + {"op": "add_column_table", "byte_offset": 62080, "span": 112, + "dst": "phase 8's C = phase 7's D + the table"}, + {"op": "load_B", "byte_offset": 41600, "span": 1548}, + ]}, + "E8": {"after": 8, "ops": [ + {"op": "load_A", "from": "shared", "offsets": [2048, 2560]}, + {"op": "load_B", "byte_offset": 60032, "span": 1548}, + ]}, + "E9": {"after": 9, "stmts": (11554, 12396), "ops": [ + {"op": "rms_norm", "eps": "2^-13", "reduction": "4-lane butterfly", + "gain_byte_offset": 62208, "gain_span": 112, + "note": "produces the normalised tile N, 32 f16x2, re-packed by E11, " + "E13, E15, E17, E19, E21 and E23"}, + {"op": "e4m3_requantise", "count": 32, "dst": "phase 10's A"}, + {"op": "load_B", "byte_offset": 62336, "span": 1548}, + {"op": "load_bias", "byte_offset": 64384, "span": 48, "dst": "phase 10's C"}, + ]}, + "E10": {"after": 10, "stmts": (12413, 12833), "ops": [ + {"op": "clamped_cubic_activation", + "clamp": [-2.0, 2.0], + "form": "g = 0.5 + y*(0.412109375 - 0.0810546875*|y|); out = x*g", + "note": "a cubic ramp, not SiLU or GELU; g(+2)=1 and g(-2)=0"}, + {"op": "add_column_table", "byte_offset": 66496, "span": 112, + "dst": "phase 11's C = phase 9's D + the table"}, + {"op": "e4m3_requantise", "count": 16, "dst": "phase 12's A"}, + {"op": "load_B", "byte_offset": 64448, "span": 1548}, + ]}, + "E25": {"after": 25, "stmts": (15706, 15980), "ops": [ + {"op": "e4m3_requantise", "count": 24, "kept": 16, + "dst": "phase 26's A"}, + {"op": "plane_scatter", "arg": 48, + "index": "8*ex*y + 8*x + d, d = t or t|4", + "bases": ["%r488 + (laneid>>5)", "%r488 + ((g+8)>>3)", + "%r488 + ((g+16)>>3)", "%r488 + ((g+24)>>3)"], + "stores": 16, "guarded": "(y<0)|(y>=ey)|(slice>31)|(x<0)|(x>=ex)"}, + {"op": "load_B", "byte_offset": 95744, "span": 524}, + {"op": "load_bias", "byte_offset": 96768, "span": 16, "dst": "phase 26's C"}, + ]}, + "E26": {"after": 26, "stmts": (15989, 16304), "ops": [ + {"op": "lane_merge", "note": "12 guarded st.shared of the eight phase-26 D " + "registers, then a register-only row max over " + "5 u32 (10 f16) with no warp shuffle"}, + {"op": "softmax", "form": "f32 exp2 with the row maximum subtracted", + "log2e": 0x3FB8AA3B}, + {"op": "surface_scatter", "arg": 112, + "stencil": "3x3 colour tex at param_0+88 with the param_0+136 scales, " + "plus param_0+96 and param_0+104 at integer (x, y)", + "combine": "acc*sigmoid(v) + tex96*(1-sigmoid(v)) + tex104 (unless NaN)", + "channels": 3, "channel_pitch_bytes": 8, "fourth_channel": 0x0000}, + ]}, + "_shared_band": { + "note": "E11/E13/E15/E17/E19/E21/E23 are 68-statement twins: 32 packs of " + "the same normalised tile, four v4 B loads and four per-(m,n) C " + "seed words. E12/E14/E16/E18/E20/E22/E24 are 308-statement twins " + "of E10's activation with no table add and no residual.", + "unverified": "the per-phase B and C byte offsets of phases 11-24 are " + "taken from rr_layer_spec.py's phase table (weight and bias " + "columns), which reads them off the load chains; they were " + "not re-derived from the ld.weak immediates here.", + }, + } + + +if __name__ == "__main__": + import json + print(json.dumps({"layer": layer(), "patch_grid": e1_patch_grid(), + "phases": phases(), "epilogues": epilogues()}, indent=2)) \ No newline at end of file diff --git a/kernels/rr/descriptor_enc0.py b/kernels/rr/descriptor_enc0.py new file mode 100755 index 0000000..0c22c5f --- /dev/null +++ b/kernels/rr/descriptor_enc0.py @@ -0,0 +1,147 @@ +#!/usr/bin/env python3 +"""Descriptor of cuda_dldn_engine_swin_enc0_kernel for the WMMA engine. + +Source of every number below: kernels/rr/rrswin_enc0.hip's own comments and call sites (the +weight-image ranges are listed there, and each phase's `gemm(...)` call gives its operand +sources and its tile counts), plus kernels/rr/rrswin_enc0_epilogues.md for the epilogue kinds. +The card's M/N/K columns in that document are known to be wrong wherever K > 32 (its own note), +so the shapes here come from the body's call sites instead. + +Two orientations are recorded per phase. NVIDIA's mma has the *activation* as its A operand +(16-row tiles of the token patch) and the weights as B; the engine uses the weights as its A +operand and the activations as its B (kernels/tex/enc0_tail.hip's convention), so the engine's +m_tiles is NVIDIA's N/16 and its n_tiles is NVIDIA's M/16. + +Nothing here is verified against the oracle yet: this is a transcription of the body, and the +engine pilot is what will test it. +""" + +# Weight-image byte ranges, from the body's "Weight image layout of the 22 phases" comment. +WEIGHTS = { + 1: (4096, 5120), 2: (5184, 6208), 3: (6336, 7360), 4: (7360, 8384), + 5: (8384, 20672), 6: (None, None), 7: (20672, 21696), 8: (21696, 22720), 9: (22720, 23744), + 10: (23744, 36032), 11: (None, None), 12: (36032, 37056), 13: (37184, 38208), + 14: (38272, 39296), 15: (39360, 40384), 16: (40448, 41472), 17: (41472, 42496), + 18: (42560, 43584), 19: (43584, 44608), 20: (44672, 45696), 21: (45696, 53888), + 22: (54016, 54544), +} +BIAS = { + 1: (5120, 5184), 2: (6208, 6272), 5: (8384, 20672), 10: (23744, 36032), + 13: (38208, 38272), 15: (40384, 40448), 17: (42496, 42560), 19: (44608, 44672), + 21: (53888, 54016), 22: (54528, 54560), +} + +# Per phase: (NVIDIA M, NVIDIA N, K, A source, B source, C source). M and N are the mma's +# extents; the mma count is (M/16)*(N/8)*(K/32), which the self-check verifies per phase. +LAYER_PARAMS = 1032 # enc0's kernel argument block, from rr_layer_spec.py +GRID = (161, 93, 1) # ctaid.x, ctaid.y, ctaid.z; block 32x1x1 +BLOCK = (32, 1, 1) +PLANE_ARG = 48 # arg048, the plane arena the layer writes +WEIGHT_ARG = 40 # arg040, the weight image + + +def phases(): + """One dict per phase, in execution order.""" + # mma counts are the corpus's per-phase runs (22 runs, 536 mma, measured with + # kernels/tools/swin_mma.py-style linearisation). M/N/K are the body's own shapes; where + # the count alone is ambiguous the body's comment decides. + return [ + _ph(1, 96, 32, 32, "normed tile as1", "P1", "seeds"), + _ph(2, 96, 32, 32, "normed tile as2", "P2", "bias"), + _ph(3, 96, 32, 32, "normed tile as3", "P3", "zero"), + _ph(4, 96, 32, 32, "normed tile as3", "P4", "zero"), + _ph(5, 64, 96, 32, "phases 3/4 accumulators", "P5", "the 64x96 score bias table"), + _ph(6, 96, 64, 32, "softmax result", "PV of the first window", "zero"), + _ph(7, 64, 32, 32, "as7", "P7", "c7"), + _ph(8, 96, 32, 32, "normed tile as3", "P8", "zero"), + _ph(9, 96, 32, 32, "normed tile as3", "P9", "zero"), + _ph(10, 64, 96, 32, "phases 8/9 accumulators", "P10", "the second 64x96 score bias table"), + _ph(11, 96, 64, 32, "softmax result", "PV of the second window", "zero"), + _ph(12, 64, 32, 32, "as12", "P12", "c12"), + _ph(13, 64, 32, 32, "normed MLP tile asN", "P13", "bias"), + _ph(14, 64, 32, 32, "E13's packs as14", "P14", "E13's table add c14"), + _ph(15, 64, 32, 32, "asN", "P15", "bias"), + _ph(16, 64, 32, 32, "E15's packs as16", "P16", "phase 14's accumulators"), + _ph(17, 64, 32, 32, "asN", "P17", "bias"), + _ph(18, 64, 32, 32, "E17's packs as18", "P18", "phase 16's accumulators"), + _ph(19, 64, 32, 32, "asN", "P19", "bias"), + _ph(20, 64, 32, 32, "E19's packs as20", "P20", "phase 18's accumulators"), + _ph(21, 16, 64, 128, "E20's merge m21", "P21", "bias"), + _ph(22, 64, 16, 32, "E20's packs r20", "P22", "bias"), + ] + + +def _ph(index, m, n, k, a_src, b_src, c_src, epilogue=None): + wlo, whi = WEIGHTS[index] + blo, bhi = BIAS.get(index, (None, None)) + return dict( + index=index, + gemm=dict( + m=m, n=n, k=k, mma=(m // 16) * (n // 8) * (k // 32), + nvidia_m_tiles=m // 16, nvidia_n_tiles=n // 16, + # the engine's convention: weights are A, activations are B + engine_m_tiles=n // 16 if wlo is not None else None, + engine_n_tiles=m // 16 if wlo is not None else None, + a_source=a_src, + b_source=dict(kind="weight image", byte_offset=wlo, byte_span=None if wlo is None else whi - wlo), + c_source=dict(kind=c_src, byte_offset=blo, + byte_span=None if blo is None else bhi - blo), + k_tiling="NVIDIA's k32 step = two gfx12 k16 WMMA steps (swin_gemm_tile)", + ), + epilogue=epilogue, + ) + + +def layer(): + return dict( + kernel="cuda_dldn_engine_swin_enc0_kernel", + corpus="0013-PREPASS_ENTRYPOINT_NAME.ptx", + grid=GRID, block=BLOCK, kernarg_bytes=LAYER_PARAMS, + arg_plane=PLANE_ARG, arg_weights=WEIGHT_ARG, + weight_layout=("addr(n,k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) " + "+ 8*((n>>3)&1) + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) " + "-- kernels/rr/rrswin_enc0.hip, swin_waddr_enc0 in the engine"), + notes=[ + "The engine's m_tiles/n_tiles are swapped relative to NVIDIA's, because the engine " + "uses the prepared weights as its A operand (enc0_tail's convention).", + "Phases 5/10's score and 6/11's P*V take both operands from accumulators; the " + "engine still consumes them through the weight-slot path, so their 'B' is a staged " + "image, not the weight image.", + "Phases 21 and 22 read E20's merge output (an arena scatter) and phase 21 writes a " + "surface; those are the epilogues the engine does not have yet.", + ], + ) + + +def self_check(): + """Compare this descriptor's mma total with the corpus. + + The per-phase mma counts came from the corpus's contiguous runs; this checks that the + M/N/K above still reproduce them, so a shape edit that breaks the arithmetic is caught. + """ + import importlib.util as _i + import os + import sys as _s + _s.path.insert(0, os.path.join(os.path.dirname(os.path.abspath(__file__)))) + import rr_layer_spec as R + path, entry = R.resolve("enc0", None, None) + lines = open(path).read().split("\n") + first, last = next((a, b) for (n, a, b) in R.find_entries(lines) if n == entry) + stmts, _ = R.linearise(lines, first, last) + runs, cur = [], 0 + for s in stmts: + if s.is_mma: + cur += 1 + elif cur: + runs.append(cur) + cur = 0 + if cur: + runs.append(cur) + mine = [p["gemm"]["mma"] for p in phases()] + return dict(corpus_total=sum(runs), descriptor_total=sum(mine), + corpus_runs=runs, descriptor_runs=mine, agrees=runs == mine) + + +if __name__ == "__main__": + import json + print(json.dumps(dict(layer=layer(), phases=phases(), self_check=self_check()), indent=1)) diff --git a/kernels/rr/descriptor_enc2.py b/kernels/rr/descriptor_enc2.py new file mode 100644 index 0000000..5764164 --- /dev/null +++ b/kernels/rr/descriptor_enc2.py @@ -0,0 +1,593 @@ +"""Descriptor for `cuda_dldn_engine_swin_enc2_kernel` (nvngx_dlssd.dll 310.7). + +The parameterised WMMA engine's description of enc2: launch geometry, per-phase +GEMM shape, where each operand comes from, and what each epilogue computes. + +Provenance of every field +------------------------- +* Geometry (m/n/k tiles, mma count, B-operand register sets, C-operand register + sets and their producers) is read out of the corpus module + `~/.cache/d4r-rr-corpus/0015-PREPASS_ENTRYPOINT_NAME.ptx` by + `kernels/rr/rr_layer_spec.py enc2`, whose linearisation is reproducible with + `python3 kernels/rr/rr_layer_spec.py enc2`. The M/N/K columns of that tool's + phase table are 3x/12x too large for every phase with k > 1 (it sets + `M = 16*|A|` and `N = 8*|B|`, counting each k32 step as another m/n-tile); the + values here divide those out by k, which is fixed uniquely by the chain's own + `m*k = |A|`, `n*k = |B|`, `m*n = chains`, and every row then satisfies + `mma = m*n*k`. +* Byte offsets are the `ld.weak.global.ca.v4.u32` / `ld.global.v2.u16` / + `ld.global.u32` immediates read directly from the PTX, and are relative to the + pointer the epilogue builds (see each phase's `weight_pointer`). +* Epilogue arithmetic is read from the op sequences at the statement ranges + `kernels/rr/rrswin_enc2_epilogues.md` names (E1-E38). +* Launch geometry and the arena/parameter-block layout are from a measured + replay manifest, captured with + `D4R_CUDA_REPLAY_DUMP_DIR=... D4R_CUDA_REPLAY_DUMP_FILTER=swin_enc2`. + +Anything not established that way carries `"unverified"` with the reason. +""" + +# --------------------------------------------------------------------------- +# Launch geometry, measured +# --------------------------------------------------------------------------- +_LAUNCH = { + "entry": "cuda_dldn_engine_swin_enc2_kernel", + "corpus_module": "0015-PREPASS_ENTRYPOINT_NAME.ptx", + "grid": [41, 24, 1], + "block": [32, 1, 4], + "wavefront": 32, + "warps_per_block": 4, # one warp per work-item in z + "lanes_per_warp": 32, + "shared_bytes": 9600, + "param_bytes": 144, + "param_ld_offsets": [8, 40, 80], + "work_per_warp": "one 8x8 token patch per warp; four waves deep in z", + # one measurement, tools/wine_nvcuda_bridge.c replay manifest + "measured_launch_line": "launch 41 24 1 32 1 4 0", + # token geometry: ex x ey is read from param+0 at run time; at the harness + # resolution it is 320x184, and the grid is (ex/2 + 1) x (ey/2 + 1) + "extents_arg": 0, + "extents_layout": "v2.u32 (ex, ey)", + "extents_measured": [320, 184], +} + +# --------------------------------------------------------------------------- +# Argument windows. Measured: a single 65,945,600-byte allocation (alloc 0) +# holds three of the buffers, so each parameter is an offset into it; the weight +# image is its own allocation. `offset` is the byte offset of the window inside +# its allocation. +# --------------------------------------------------------------------------- +_ARGS = { + "extents": {"arg": 0, "kind": "u32x2", "window_bytes": 8}, + "input_image": {"arg": 8, "kind": "buffer", "alloc": 0, "offset": 60293120, + "window_bytes": 5652480, "note": "320x184x4 f16, the block input patch source"}, + "weights": {"arg": 40, "kind": "buffer", "alloc": 1, "offset": 0, + "window_bytes": 212256, + "note": "prepared e4m3 weight image, read-only; 212256 bytes is the whole image"}, + "plane_arena": {"arg": 48, "kind": "buffer", "alloc": 0, "offset": 30146560, + "window_bytes": 5652480, + "note": "written by E36's scatter, never read back"}, + "output_O": {"arg": 56, "kind": "buffer", "alloc": 0, "offset": 35799040, + "window_bytes": 2450560, + "note": "phase 37's four guarded stores land here"}, + "origins": {"arg": 80, "kind": "u16x2", "window_bytes": 4, + "note": "(rs126, rs127), the block's x/y patch origin offsets"}, + "texture_in": {"arg": 88, "kind": "texture", "shape": "320x184x4", "fmt": 16}, + "surface_0": {"arg": 112, "kind": "surface", "shape": "320x184x4", "fmt": 16}, + "surface_1": {"arg": 120, "kind": "surface", "shape": "320x184x4", "fmt": 16}, + "surface_2": {"arg": 128, "kind": "surface", "shape": "160x92x4", "fmt": 16}, +} + +# --------------------------------------------------------------------------- +# Operand vocabulary shared by the phases +# --------------------------------------------------------------------------- +# The pointer each phase adds its byte offsets to. Phases 1-7 index a per-plane +# weight slab; phases 9-36 carry no %tid.z term; phase 37 uses a different +# stride. The inconsistency is real and is reproduced verbatim (epilogues.md U5). +_WZ = {"expr": "W + 21504*tid.z + 16*laneid", "phases": "1-7"} +_W = {"expr": "W + 16*laneid", "phases": "9-36, 38"} +_W37 = {"expr": "W + 12288*tid.z + 16*laneid", "phases": "37"} + +# a phase's B operand comes from consecutive 512-byte tiles at the given base +_WTILE = 512 + + +def _band(w_base, bias_base, a_from, act_from): + """One (odd, even) branch of the MLP band, phases 13/14 .. 35/36.""" + return {"odd": w_base, "bias": bias_base, "a": a_from, "act": act_from} + + +# The band is twelve repetitions of the same pair, hanging off one shared +# normalised tile. `odd` is the 48x96x32 banded GEMM, `even` the 16x96x32 one +# whose C is the running residual. +_BAND_BASES = [(86592, 89664), (92992, 96064), (99200, 102272), + (105408, 108480), (111616, 114688), (117824, 120896), + (124032, 127104), (130240, 133312), (136448, 139520), + (142656, 145728), (148864, 151936), (155072, 158144)] +_BAND_EVEN_B = [89728, 96128, 102336, 108544, 114752, 120960, + 127168, 133376, 139584, 145792, 152000, 158208] +_RESIDUAL_TABLE = 92800 # E13(b): added to phase 12's D to seed phase 14's C + + +def phases(): + """The 38 phases in order. Each dict is one mma chain plus its epilogue.""" + out = [] + add = out.append + + # ---- phases 1-6: the 96x96 -> 96x32 residual projection ---------------- + # A is the entry's staged input tile: three K=32 slices of the 96x96 patch, + # RMS-normalised with a per-column gain and requantised to e4m3 by the + # prologue, staged at smem + 512*(3*slice + m-tile) + 16*laneid. + slices = {1: 0, 2: 0, 3: 1, 4: 1, 5: 2, 6: 2} + w_base = {1: 192, 2: 3264, 3: 1216, 4: 4288, 5: 2240, 6: 5312} + c_from = {1: None, 2: None, 3: 1, 4: 2, 5: 3, 6: 4} + for p in range(1, 7): + add({ + "id": p, + "gemm": { + "m_tiles": 6, "n_tiles": 4, "k": 1, + "M": 96, "N": 32, "K": 32, "mma": 24, + "A": { + "source": "staged_input_tile", + "slice": slices[p], + "shared_addr": "smem + 512*(3*slice + m_tile) + 16*laneid", + "dtype": "e4m3", + "note": "18 A quads total, six m-tiles x three K=32 slices; " + "the prologue writes them, requantised from the " + "RMS-normalised f16 patch", + }, + "B": { + "source": "weights", + "weight_pointer": _WZ, + "base": w_base[p], + "stride": _WTILE, + "tiles": 4, + "dtype": "e4m3", + }, + "C": ({"source": "zero", "value": 0} if c_from[p] is None else + {"source": "phase_D", "phase": c_from[p], + "note": "the phase two before that shares this A fragment"}), + }, + "k_tiling": {"k": 32, "wmma_steps": 2, "step_k": 16, + "f16_round_per_k32": True}, + "epilogue": { + "ops": ["load_B_tiles"], + "for_phase": p + 1 if p < 6 else 7, + "offsets": {"next_B_base": {1: 3264, 2: 1216, 3: 4288, + 4: 2240, 5: 5312}.get(p)}, + "note": "E%d: six weight loads for the next phase's B, nothing else" + % p, + }, + }) + + # ---- phase 7: the 64x96 attention score ------------------------------ + add({ + "id": 7, + "gemm": { + "m_tiles": 4, "n_tiles": 12, "k": 1, + "M": 64, "N": 96, "K": 32, "mma": 48, + "A": { + "source": "phase_D_requantised", + "phase": 5, + "m_tiles_used": [0, 1, 2, 3], + "role": "queries: phase 5's D read as a 64-row tile", + "dtype": "e4m3", + "note": "packed by E6(b) from phase 5's D; A frag 0 is bit-identical " + "to B frag 0 (s4853 vs s4925) because both are phase 5's D", + }, + "B": { + "source": "phase_D_requantised", + "phase": 5, + "n_tiles_used": list(range(12)), + "role": "keys: the same 96x32 tile read as rows", + "dtype": "e4m3", + "note": "the score multiplies one projection by its own transpose", + }, + "C": { + "source": "weight_bias_table", + "weight_pointer": _WZ, + "base": 6336, + "bytes": 12288, + "layout": "512*(4*(n>>1) + m) + 16*laneid + 8*(n&1), " + "one f16x2 per score element, 48 distinct pairs", + "dtype": "f16", + "note": "96 C words per lane; an opaque relative-position or " + "learned score bias (epilogues.md U2)", + }, + }, + "k_tiling": {"k": 32, "wmma_steps": 2, "step_k": 16, + "f16_round_per_k32": True}, + "epilogue": { + "ops": ["softmax_no_max", "transpose_movmatrix", "requantise_pack"], + "softmax": { + "kind": "cubic_exp", + "elements": 96, + "scale": 0.017181396484375, # f16 0x2466, from 0f3C8CCB50 + "clamp": [-0.55615234375, 0.55615234375], # 0dBFE1CC0 / 0d3FE1CC0 + "cubic": {"a": 0.92724609375, "b": 1.375}, # 0f3F6D6000, 0f3FB00000 + "extraction": "E = bits(u)[10:5], F = bits(u)[4:0]; " + "expval = f16 from bits (E<<10) | (F<<5)", + "row_sum": { + "in_lane_tree": "A = ((e0+e2)+(e4+e6)) + (e8+e10); " + "B = ((e1+e3)+(e5+e7)) + (e9+e11); sum = A + B", + "butterfly": [1, 2], + "fold": "add.f16 of the two halves, then broadcast to both", + "note": "f16 addition is not associative, so the tree order is " + "part of the result; there is no row maximum anywhere", + }, + "reciprocal": "rcp.approx.ftz.f32 on f32(f16 sum), rounded to f16", + "transpose": {"op": "movmatrix.sync.trans.aligned.m8n8.b16", + "count": 48, "source_phase": 6, + "note": "one per phase 6 D register; 48 x 64 = the whole " + "96x32 tile"}, + "requantise_pack": {"ops": ["e4m3_requantise", "pack"], + "target_phase": 8}, + "for_phase": 8, + }, + }) + + # ---- phase 8: the attention output projection ------------------------- + add({ + "id": 8, + "gemm": { + "m_tiles": 4, "n_tiles": 4, "k": 3, + "M": 64, "N": 32, "K": 96, "mma": 48, + "A": {"source": "phase_D_requantised", "phase": 7, + "role": "the 64x96 softmax probabilities", + "quads": 12, "dtype": "e4m3"}, + "B": {"source": "phase_D_transposed_requantised", "phase": 6, + "role": "movmatrix transposes of phase 6's 96x32 D, i.e. 32x96", + "pairs": 12, "dtype": "e4m3"}, + "C": {"source": "zero", "value": 0, "note": "%r8606, the region's " + "zero accumulator start; four chains of three k-steps"}, + }, + "k_tiling": {"k": 96, "wmma_steps": 6, "step_k": 16, + "k32_chain_length": 3, "f16_round_per_k32": True}, + "epilogue": { + "ops": ["requantise", "shared_stage", "load_B_tiles", + "column_table_add", "residual_from_input"], + "shared_stage": { + "addr": "smem + 2048*tid.z + 16*laneid + {0, 512, 1024, 1536}", + "stores": 4, "bytes_each": 16, "per_lane": 64, + "content": "32 of phase 8's 48 D registers, packed two per word", + "unverified": "E8's slot layout is self-inconsistent: the writes " + "cover slots {0..15} over the four z-planes while the " + "reads are at 512*tid.z + {0,2048,4096,6144}. It is " + "only consistent if blockDim.z = 4 and the four " + "z-planes write the tile cooperatively " + "(epilogues.md U4)", + }, + "column_table_add": { + "weight_pointer": _W, + "base": 86208, "bytes": 192, + "layout": "W + ((laneid<<2)&12) + {86208, 86224, ..., 86384}", + "dtype": "f16", "count": 96, + "note": "one value per column of phase 9's N axis", + }, + "residual_from_input": { + "regs": ["%r2798", "%r2800", "%r2799", "%r2801", "%r2806", + "%r2808", "%r2807", "%r2809", "%r2814", "%r2816", + "%r2815", "%r2817"], + "note": "the residual added into phase 9's C is the prologue's " + "cvt.rn.f16x2.e4m3x2 of the quantised input patch, not " + "phase 8's D (epilogues.md U9). The prologue's addressing " + "for these is not reproduced here.", + "unverified": "the prologue computes %r17771/%r17794 through a " + "five-way select on laneid, the z-plane bias and " + "clamped (x, y); re-deriving it needs the E-prologue " + "index arithmetic, which is outside the mma region", + }, + "for_phase": 9, + }, + }) + + # ---- phases 9-12: four 16x96 projections on phase 8's D --------------- + w9 = {9: 18624, 10: 40128, 11: 61632, 12: 83136} + for p in range(9, 13): + add({ + "id": p, + "gemm": { + "m_tiles": 1, "n_tiles": 12, "k": 1, + "M": 16, "N": 96, "K": 32, "mma": 12, + "A": {"source": "shared", "from_phase": 8, + "addr": "smem + 512*tid.z + 16*laneid + " + + str(2048 * (p - 9)), + "quads": 1, "dtype": "e4m3", + "note": "the e4m3 pack of one m-tile of phase 8's D"}, + "B": {"source": "weights", "weight_pointer": _W, + "base": w9[p], "stride": _WTILE, "tiles": 6, + "dtype": "e4m3"}, + "C": ({"source": "column_table_plus_input_patch", + "table_base": 86208, "input_regs": "%r2798..%r2821", + "pairs": 24, "note": "E8(d): a per-column f16 table added " + "to the prologue's quantised input patch"} + if p == 9 else + {"source": "phase_D", "phase": p - 1, + "note": "the C chain runs 9 -> 10 -> 11 -> 12"}), + }, + "k_tiling": {"k": 32, "wmma_steps": 2, "step_k": 16, + "f16_round_per_k32": True}, + "epilogue": { + "ops": (["shared_stage", "load_B_tiles", "column_table_add", + "residual_from_input"] if p == 9 else + ["shared_read", "load_B_tiles"]), + "load_B_tiles": {"base": w9[p + 1] if p < 12 else None, + "stride": _WTILE, "tiles": 6}, + "for_phase": p + 1 if p < 12 else 13, + }, + }) + + # ---- the MLP band: twelve branches off one normalised tile ----------- + # phase 12's D is RMS-normalised once (E12) into a 16x96 f16 tile; all + # twelve odd phases read that same tile, and the even phases carry the + # residual D12 -> D14 -> ... -> D36. + add({ + "id": "norm12", + "gemm": None, + "k_tiling": None, + "epilogue": { + "ops": ["rms_norm", "gain_multiply", "requantise_pack"], + "after_phase": 12, + "rms_norm": { + "kind": "rms", + "extent": 96, + "eps": 0.0001220703125, # 2^-13, %fd1 = 0d3F20000000000000 + "accumulate": "raw sum of squares, f16 tree then two butterfly " + "steps (delta 1, delta 2) over the four lanes with " + "equal laneid>>2", + "inverse": "rsqrt.approx.ftz.f32(f32(f16(sum + eps))), rounded to f16", + "no_mean": True, + "note": "no mean subtraction and no 1/N; this is an RMS norm, " + "not a mean-subtracting LayerNorm. The prologue's norm " + "(s3812 ff.) has the identical shape", + }, + "gain": {"weight_pointer": _W, "base": 86400, "bytes": 192, + "count": 96, "dtype": "f16", + "layout": "W + ((laneid<<2)&12) + {86400, 86416, ..., 86576}", + "note": "per-column gain, constant across rows"}, + "bias_deferred": "the norm's bias is not added here; it becomes the " + "odd phase's C seeds", + "output": {"shape": [16, 96], "dtype": "f16", "regs": 24, + "register_range": "%r15561..%r15584"}, + }, + }) + + for i, ((odd_w, bias), even_w) in enumerate(zip(_BAND_BASES, _BAND_EVEN_B)): + odd, even = 13 + 2 * i, 14 + 2 * i + add({ + "id": odd, + "gemm": { + "m_tiles": 1, "n_tiles": 4, "k": 3, + "M": 16, "N": 32, "K": 96, "mma": 12, + "A": {"source": "normalised_tile", "from": "norm12", + "quads": 3, "dtype": "e4m3", + "note": "the 16x96 normed tile requantised into three " + "16x32 k-slices; E12 packs it at s9784, and every " + "even epilogue E14, E16, ... repacks the same tile"}, + "B": {"source": "weights", "weight_pointer": _W, + "base": odd_w, "stride": _WTILE, "tiles": 6, + "dtype": "e4m3", + "unverified": "which (n-tile, k-step) each 512-byte tile " + "holds is not derivable from the PTX: the four " + "chains pair the six tiles as {0,2,4} and " + "{3,4,5}, so the image's tile stride is not " + "(n,k)-major (epilogues.md U1). The byte " + "offsets and the six loads are exact."}, + "C": {"source": "weight_bias_table", "weight_pointer": _W, + "base": bias, "stride": 16, "words": 4, "dtype": "f16", + "layout": "W + ((laneid*4)&12) + {%d, +16, +32, +48}, each " + "used as {rX, rX}" % bias, + "note": "per-column bias replicated over the tile's 16 rows; " + "four chains of three k-steps"}, + }, + "k_tiling": {"k": 96, "wmma_steps": 6, "step_k": 16, + "k32_chain_length": 3, "f16_round_per_k32": True}, + "epilogue": { + "ops": ["clamped_cubic", "requantise_pack"], + "activation": { + "kind": "clamped_cubic", + "clamp": [-2.0, 2.0], + "formula": "y = clamp(x, -2, 2); g = 0.5 + y*(0.412109375 - " + "0.0810546875*|y|); out = x*g", + "constants_f32": [0.4121621549129486, 0.0810810774564743, + 0.5, 2.0], + "constants_f16": [0.412109375, 0.0810546875, 0.5, 2.0], + "op_order": "neg, max, min, abs, mul, sub, mul, add, mul", + "dtype": "f16x2 throughout", + "note": "byte-identical to enc0's E13; g(+2) = 1 so out = x " + "for x >= 2, g(-2) = 0 so out = 0 for x <= -2", + }, + "requantise_pack": {"target_phase": even, + "quads": 1, + "note": "8 cvt + 4 mov.b32 -> one A quad"}, + "for_phase": even, + }, + }) + add({ + "id": even, + "gemm": { + "m_tiles": 1, "n_tiles": 12, "k": 1, + "M": 16, "N": 96, "K": 32, "mma": 12, + "A": {"source": "activation_pack", "from_phase": odd, + "quads": 1, "dtype": "e4m3"}, + "B": {"source": "weights", "weight_pointer": _W, + "base": even_w, "stride": _WTILE, "tiles": 6, + "dtype": "e4m3"}, + "C": ({"source": "residual_plus_column_table", + "table_weight_pointer": _W, + "table_base": _RESIDUAL_TABLE, "table_bytes": 192, + "residual_phase": 12, "pairs": 24, + "note": "E13(b): phase 12's D plus a per-column f16 table, " + "added to all 16 rows"} + if even == 14 else + {"source": "phase_D", "phase": even - 2, + "note": "the residual chain D12 -> D14 -> ... -> D36"}), + }, + "k_tiling": {"k": 32, "wmma_steps": 2, "step_k": 16, + "f16_round_per_k32": True}, + "epilogue": { + "ops": (["load_B_tiles", "load_C_bias", "requantise_pack_norm"] + if even < 36 else + ["load_B_tiles", "requantise"]), + "note": "E%d: phase %d's B loads and C seeds, then 24 packs of the " + "shared normed tile into phase %d's three A quads" + % (even, even + 1, even + 1), + "for_phase": even + 1 if even < 36 else 37, + }, + }) + + # ---- the patch merge: phase 37 --------------------------------------- + add({ + "id": 37, + "gemm": { + "m_tiles": 1, "n_tiles": 4, "k": 12, + "M": 16, "N": 32, "K": 384, "mma": 48, + "A": {"source": "shared", "from_phase": 36, + "quads": 12, "dtype": "e4m3", "regs": 48, + "addr": "smem, swizzled", + "loads": "48 ld.shared.u32, the first at word " + "((laneid<<2) & ~63) | ((laneid<<1) & 24) | " + "((laneid>>2)&3), the rest at +4,+8,+12,+16,+20 and a " + "floor-divide-by-24 decomposition for the byte plane", + "note": "the 12 staged words per lane are phase 36's requantised " + "output, one 16x8 n-tile each", + "unverified": "how 12 staged words per lane become a 384-deep k " + "axis is not determined without the swizzle's " + "intent (epilogues.md U8)"}, + "B": {"source": "weights", "weight_pointer": _W37, + "base": 161280, "stride": _WTILE, "tiles": 24, + "pairs": 48, "dtype": "e4m3", + "loop": "inside $L__BB1_244, whose trip count is 1 for " + "tid.z <= 3"}, + "C": {"source": "weight_bias_table", "weight_pointer": _W, + "base": 210432, "stride": 16, "words": 4, "dtype": "f16", + "layout": "W + ((laneid*4)&12) + {%d, +16, +32, +48}" % 210432, + "note": "per-column bias seeding four chains of twelve k-steps"}, + }, + "k_tiling": {"k": 384, "wmma_steps": 24, "step_k": 16, + "k32_chain_length": 12, "f16_round_per_k32": True}, + "epilogue": { + "ops": ["requantise", "surface_scatter", "load_B_tiles", "load_C_bias"], + "requantise": {"source_phase": 37, "words": 12, "target": "stores", + "note": "8 cvt + 3 mov.b32 -> %r287 (2 b32) and " + "%rs4534/%rs4535, %rs4540/%rs4541"}, + "surface_scatter": { + "target": "output_O", "arg": 56, + "stores": 4, + "extents": "halved: ex>>1, ey>>1", + "base": "y = (%r2>>1) + (laneid>>4); x = (%r1>>1) + ((laneid>>2)&3)", + "plane": "plus tid.z * (ey>>1) * 8*(ex>>1)", + "guard": "p6 = (y<0)|(y>=(ey>>1))|(laneid>63)|(x<0)|(x>=(ex>>1))", + "index": "8*(ex>>1)*y + 8*x + (t | 4)", + "note": "the second pair recomputes y', x' from (laneid>>2)+8 at " + "the same base", + }, + "load_B_tiles": {"base": 210688, "stride": _WTILE, "tiles": 3, + "weight_pointer": _W}, + "load_C_bias": {"base": 212224, "stride": 16, "words": 2, + "weight_pointer": _W}, + "for_phase": 38, + }, + }) + + # ---- the attention window: phase 38 ---------------------------------- + add({ + "id": 38, + "gemm": { + "m_tiles": 1, "n_tiles": 2, "k": 3, + "M": 16, "N": 16, "K": 96, "mma": 6, + "A": {"source": "phase_D_requantised", "phase": 36, + "quads": 3, "pairs": 6, "dtype": "e4m3", + "note": "the A quads are %r183,%r185,%r184,%r186 and the two " + "further pairs, i.e. E36's requantised registers read " + "directly, not phase 37's output"}, + "B": {"source": "weights", "weight_pointer": _W, + "base": 210688, "stride": _WTILE, "tiles": 3, + "pairs": 6, "dtype": "e4m3"}, + "C": {"source": "weight_bias_table", "weight_pointer": _W, + "base": 212224, "stride": 16, "words": 2, "dtype": "f16", + "layout": "W + ((laneid*4)&12) + {212224, 212240}", + "note": "two chains of three k-steps"}, + }, + "k_tiling": {"k": 96, "wmma_steps": 6, "step_k": 16, + "k32_chain_length": 3, "f16_round_per_k32": True}, + "epilogue": { + "ops": ["shared_stage", "bounds_gate", "softmax_with_max", + "texture_gather", "sigmoid", "scale", "lane_reduce", + "surface_scatter"], + "shared_stage": { + "addr": "&smem + ((g + 16*tid.z) & 0x40000008 | (laneid>>2)&7)" + " * 6 * 4 + t * 4, and +16 for the second row bank", + "stores": 4, "row_pitch_words": 6, + "content": "phase 38's four chain-final D pairs", + }, + "bounds_gate": "p265 = (tid.z>1) | ((x|y) < 0) | (x >= ex) | (y >= ey)", + "softmax": { + "kind": "softmax_with_max", + "window": 5, "dtype": "f16", + "max": "max.f16x2 twice then max.f16 twice over the low halves of " + "five words, broadcast to both halves", + "exp": "2^((x - max) * log2e) through ex2.approx.ftz.f32", + "sum": "f32 row sum over the five weights", + "invert": "div.approx.ftz.f32", + "note": "a real row maximum, unlike E7", + }, + "texture_gather": { + "surface": "texture_in", "arg": 88, + "reads": 9, "offsets": "(x-1, x, x+1) x (y-1, y, y+1)", + "combine": "fma.rn.f16x2 with the five softmax weights, 2x2 " + "accumulator halves folded with add.f16, then one more " + "shared value with fma.rn.f16", + "clamp": "coordinates selp'd to 1 when out of range", + }, + "post": { + "sigmoid": "1/(1 + 2^(-log2e*v)) on two more shared values", + "difference": "acc - sigmoid*acc", + "scale": 0.25, + "lane_reduce": "shfl.sync.down delta 1 then delta 8, f16x2 path " + "and scalar path, segmask 31, membermask -1", + }, + "surface_scatter": { + "targets": [{"arg": 112, "shape": "320x184x4"}, + {"arg": 120, "shape": "320x184x4"}, + {"arg": 128, "shape": "160x92x4"}], + "op": "sust.b.2d.v4.b16.zero", + "index": "(x<<3, y) for the first two, ((x<<2) & -8, y>>1) for " + "the third", + "guard": "the third is taken only when (x|y) is odd", + "note": "the third store's fourth channel is a literal zero", + }, + "for_phase": None, + }, + }) + + return out + + +def layer(): + """The launch geometry and argument windows, as one record.""" + return { + "name": "enc2", + "entry": _LAUNCH["entry"], + "corpus_module": _LAUNCH["corpus_module"], + "grid": _LAUNCH["grid"], + "block": _LAUNCH["block"], + "wavefront": _LAUNCH["wavefront"], + "warps_per_block": _LAUNCH["warps_per_block"], + "shared_bytes": _LAUNCH["shared_bytes"], + "param_bytes": _LAUNCH["param_bytes"], + "args": _ARGS, + "weight_pointers": {"Wz": _WZ, "W": _W, "W37": _W37}, + "weight_image_bytes": 212256, + "weight_slab_strides": [21504, 12288], + "token_geometry": { + "patch": [8, 8], + "grid_from_extents": "((ex >> 1) + 1, (ey >> 1) + 1, 1)", + "origin_arg": 80, + "note": "the block's x/y patch origin offsets are param+80's u16 pair; " + "the patch origin is x0 = 8*ctaid.x - rs126, " + "y0 = 8*(ctaid.y + tid.y) - rs127", + }, + "measured_launch_line": _LAUNCH["measured_launch_line"], + "phases": phases(), + } diff --git a/kernels/rr/descriptor_enc3.py b/kernels/rr/descriptor_enc3.py new file mode 100644 index 0000000..2b5724d --- /dev/null +++ b/kernels/rr/descriptor_enc3.py @@ -0,0 +1,450 @@ +"""Descriptor for `cuda_dldn_engine_swin_enc3_kernel` (DLSS 310.7). + +Machine-readable geometry for the parameterised WMMA engine: what every one of the +entry's 48 GEMMs consumes and produces, and what each epilogue does in between. +Every number here is either + + * measured at run time (the launch geometry and the parameter-block layout, + from a replay capture -- see `layer()`), or + * derived mechanically from the corpus PTX + (`python3 kernels/rr/rr_layer_spec.py enc3`, which prints the same numbers, + and `kernels/rr/rrswin_enc3_epilogues.md`, which decodes the epilogues), or + * explicitly flagged `"unverified"` with the reason. + +Nothing here is transcribed by hand from a disassembly: the per-phase GEMM table +in `phases()` is checked field by field against rr_layer_spec's `geom()`, +`chains_of()` and per-mma weight/C byte offsets over the `mma.sync` runs. Where +the two disagree this file is wrong and the fix belongs here. + +Vocabulary used in the phase dicts +---------------------------------- +m_tiles 16-row mma tiles the fragment operands span (M = 16 * m_tiles) +n_tiles 8-column nma tiles the fragment operands span (N = 8 * n_tiles) +k32 number of m16n8k32 accumulation steps chained into one output tile; + the engine splits each into `k32 * 2` gfx12 WMMA 16-deep steps +dense every (m_tile, n_tile) of the M x N grid is evaluated. When false the + phase is banded: `band` says which tiles are, and `gemm_real` gives the + true result shape (M/N above are then only the extent spanned) +a where the activation operand comes from and how it reaches e4m3 +b where the weight operand comes from +c what the accumulator is seeded with before the chain runs + +Only the first ten phases have a bit-exact native body today +(kernels/rr/rrswin_enc3.hip); phases 11..48 are specified here but not yet +implemented, which is why that body is a reference for this descriptor and not +the deliverable. +""" + +# --------------------------------------------------------------------------- +# The stem's eight phases are a 2 x 4 shift stencil over one 96-row tile; see +# U6 in rrswin_enc3_epilogues.md for what the shift means at model level. +_STEM_W = {1: 256, 2: 4352, 3: 1280, 4: 5376, 5: 2304, 6: 6400, 7: 3328, 8: 7424} + +# The MLP block is 16 odd/even pairs. Each odd phase is a banded 64x64x128 GEMM +# off the *same* normed tile (E14) with its own weights and per-column bias; each +# even phase is a dense 16x128x32 GEMM whose A is the previous odd phase's +# activation and whose C is the previous even phase's accumulator (plus, for the +# first pair only, a column table -- U5). +_ODD_W = {15: 99072, 17: 107584, 19: 115840, 21: 124096, 23: 132352, 25: 140608, + 27: 148864, 29: 157120, 31: 165376, 33: 173632, 35: 181888, 37: 190144, + 39: 198400, 41: 206656, 43: 214912, 45: 223168} +_ODD_BIAS = {15: 103168, 17: 111680, 19: 119936, 21: 128192, 23: 136448, + 25: 144704, 27: 152960, 29: 161216, 31: 169472, 33: 177728, + 35: 185984, 37: 194240, 39: 202496, 41: 210752, 43: 219008, + 45: 227264} +_EVEN_W = {16: 103232, 18: 111744, 20: 120000, 22: 128256, 24: 136512, + 26: 144768, 28: 153024, 30: 161280, 32: 169536, 34: 177792, + 36: 186048, 38: 194304, 40: 202560, 42: 210816, 44: 219072, + 46: 227328} +_PROJ_W = {11: 20736, 12: 45312, 13: 69888, 14: 94464} + +# Column tables, all read through the `W + ((laneid<<2)&12) + off` pattern, i.e. +# indexed by column (the four lanes with equal laneid&3 read the same record). +_TBL_RESIDUAL = 98560 # E10, feeds phase 11's C +_TBL_GAIN = 98816 # E14, the RMS norm's per-column gain +_TBL_P16 = 107328 # E15, added to phase 14's D into phase 16's C + + +def layer(): + """Launch geometry, parameter block and token geometry.""" + return { + "entry": "cuda_dldn_engine_swin_enc3_kernel", + "corpus": "0016-PREPASS_ENTRYPOINT_NAME.ptx", + "grid": (21, 13, 1), + "block": (32, 1, 4), + "wave_size": 32, + "waves_per_block": 4, + "waves_are_distinct": True, + "waves_note": ( + "wave z reads its own 24576-byte slice of the weight image " + "(line 9765 `mul.lo.s32 %r21780, %r12, 12288`), so the wave index " + "is part of every per-wave offset, not a redundant copy"), + "shared_arena": { + "symbol": "_ZZ33cuda_dldn_engine_swin_enc3_kernel" + "33DldnEngineSwinEncParamsStructBaseE4smem", + "bytes": 12800, + "window_per_wave": 3200, + }, + "param_block_bytes": 144, + "params": { + 0: "u32[2] (ex, ey) output extents", + 8: "input plane pointer", + 40: "prepared weight image pointer", + 48: "plane arena pointer (write-only inside this entry)", + 56: "output buffer pointer", + 80: "u16[2] block-origin offsets", + 88: "texture object", + 112: "surface object", + 120: "surface object", + 128: "surface object", + }, + # Measured from a replay capture of a real launch + # (D4R_CUDA_REPLAY_DUMP_DIR): the three pointers above are windows into + # one 65,945,600-byte allocation, which is what the launch dumper writes + # out under the name `arg008`. + "measured_allocation": { + "bytes": 65945600, + "dumped_as": "arg008", + "param_8": 35799040, + "param_48": 37683200, + "param_56": 39567360, + "arena_bytes": 28262400, + "arena_to_output": 1884160, + }, + "weight_image": { + "bytes": 315732, + "distinct_offsets": 1654, + "prep": ( + "a NAME_prep companion may permute the image once, so the engine " + "is free to consume the operands in its own order"), + }, + "tokens": { + "grid_tokens": (168, 104), + "grid_note": "ctaid.x<<3 / ctaid.y<<3 minus the u16 pair at param+80", + "input_texture": "160x92x4 f16 (param+88)", + "output_surfaces": [ + "160x92x4 f16 (param+112)", + "160x92x4 f16 (param+120)", + "80x46x4 f16 (param+128)", + ], + "patch": "one wave per 8x8 token patch", + }, + } + + +def _gemm(m_tiles, n_tiles, k32, chains, dense, mma, band=None): + """One GEMM. m_tiles/n_tiles are the tiles the fragment operands *span*, + which for a banded phase is more than the result needs -- gemm_real carries + the true shape in that case, and `mma` is the statement count either way.""" + g = {"m_tiles": m_tiles, "n_tiles": n_tiles, "k32": k32, + "M": 16 * m_tiles, "N": 8 * n_tiles, "K": 32 * k32, + "chains": chains, "mma": mma, "dense": dense, + "wmma_k": 2 * k32} + if band is not None: + g["band"] = band + return g + + +def _b(base, n_offsets): + return {"source": "weight_image", "base": base, "fragments": n_offsets, + "tile_stride": 512, "addr": "W + 16*laneid + base + 512*j"} + + +def phases(): + """One dict per GEMM, in the entry's own order.""" + out = [] + + # ---- phases 1..8: the stem ------------------------------------------ + # Two accumulator chains (P1->P3->P5->P7 and P2->P4->P6->P8) over four + # shift groups; phase p uses group (p-1)>>2 and chain (p-1)&1, and its m-tile + # mi reads A fragment 4*mi + group out of the shared arena. E1..E7 are + # identical seven-statement epilogues that only prefetch the next B. + for p in range(1, 9): + group = (p - 1) >> 2 + chain = (p - 1) & 1 + out.append({ + "n": p, + "name": f"stem_g{group}_c{chain}", + "gemm": _gemm(6, 4, 1, 24, True, 24), + "a": {"source": "shared_arena", "fragments": 6, + "addr": f"smem + 16*laneid + 512*(4*mi + {group}), mi = 0..5", + "already_e4m3": True}, + "b": _b(_STEM_W[p], 8), + "b_wave_slice": "w + tid.z*24576", + "c": ({"kind": "zero"} if p in (1, 2) + else {"kind": "accumulator", "from_phase": p - 2}), + "epilogue": { + "name": f"E{p}", + "range": [6148 + 31 * (p - 1), 6154 + 31 * (p - 1)], + "ops": [f"load phase {p + 1}'s B from W + {(_STEM_W.get(p + 1, 0))}"], + }, + }) + + # ---- phase 9: the score GEMM Q.K^T ---------------------------------- + out.append({ + "n": 9, + "name": "score", + "gemm": _gemm(4, 12, 1, 48, True, 48), + "a": {"source": "accumulator", "from_phase": 7, "roles": "query rows", + "rows": "16*mi + g + 8*row, mi = 0..3", + "requant": "e4m3; word 0 packs n-tiles 0 and 2, word 1 packs 1 and 3", + "note": "P7's accumulators serve as both the queries and the keys"}, + "b": {"source": "accumulator", "from_phase": 7, "roles": "key rows", + "rows": "16*(nb>>1) + 8*(nb&1) + n, nb = 0..11", + "requant": "e4m3, same packing as A"}, + "c": {"kind": "bias_table", "base": 8448, "words": 96, + "addr": "W + 8448 + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1) + 4*row", + "note": "24 tiles of 512 bytes; role computable, model name unknown (U1)"}, + "epilogue": { + "name": "E9", + "range": [6584, 10426], + "ops": ["expval cubic-exponent softmax", "no row maximum", + "two butterfly steps over lane bits 0 and 1", + "rcp.approx.ftz.f32", "movmatrix transpose of phase 8's D"], + "scale": "0x2466", "clamp": ["0xb873", "0x3873"], + "exponent": "((u << 5) & 0x7FE07FE0) over the packed pair", + }, + }) + + # ---- phase 10: P.V --------------------------------------------------- + out.append({ + "n": 10, + "name": "pv", + "gemm": _gemm(12, 12, 3, 16, False, 48, + band="4 row tiles x 4 column-pair groups; chain c is " + "(A_{3*(c>>2)+k}, B_{2*(c&3)+k}) for k = 0,1,2"), + "gemm_real": {"M": 64, "N": 32, "K": 96}, + "a": {"source": "softmax", "from_phase": 9, + "requant": "e4m3; k-step ks packs key columns {4ks, 4ks+2} into " + "the fragment's first word and {4ks+1, 4ks+3} into its second"}, + "b": {"source": "accumulator", "from_phase": 8, "roles": "transposed V", + "requant": "e4m3"}, + "c": {"kind": "zero"}, + "epilogue": { + "name": "E10", + "range": [10475, 10673], + "ops": ["e4m3 requantise and pack", + "shared staging at +0/+512/+1024/+1536", + "read back as phase 11's A", + "column table + prologue residual -> phase 11's C"], + "table": _TBL_RESIDUAL, + "table_addr": "W + ((laneid<<2)&12) + 98560 + 16*i", + }, + }) + + # ---- phases 11..14: the dense projection, C chained ------------------- + for p in range(11, 15): + out.append({ + "n": p, + "name": f"proj{p - 10}", + "gemm": _gemm(1, 16, 1, 16, True, 16), + "a": {"source": "shared_arena", "fragments": 1, + "addr": f"smem + (tid.z<<9) + 16*laneid + {2048 * (p - 11)}", + "already_e4m3": True}, + "b": _b(_PROJ_W[p], 32), + "c": ({"kind": "table_plus_residual", "table": _TBL_RESIDUAL, + "residual": "long-lived prologue vector"} if p == 11 + else {"kind": "accumulator", "from_phase": p - 1}), + "epilogue": { + "name": f"E{9 + (p - 10)}" if p < 14 else "E14", + "ops": (["read the next shared slot as the next phase's A", + "load the next phase's B"] if p < 14 + else ["row-RMS norm over all 128 columns", + "tree-sum in lane", "two butterfly steps", + "+ 2^-13", "rsqrt.approx.ftz.f32", + "x * inv * gain", "pack -> the odd phases' A"]), + "gain_table": _TBL_GAIN if p == 14 else None, + "gain_addr": "W + ((laneid<<2)&12) + 98816 + 16*i" if p == 14 else None, + "next_bias": 103168 if p == 14 else None, + "next_w": 99072 if p == 14 else None, + }, + }) + + # ---- phases 15..46: the MLP block, 16 odd/even pairs ------------------ + for i in range(16): + odd = 15 + 2 * i + even = 16 + 2 * i + out.append({ + "n": odd, + "name": f"mlp_up{odd - 14}", + "gemm": _gemm(4, 16, 4, 4, False, 16, + band="4 row tiles x 2 of the 8 column tiles per 8-B " + "group; chain 0 is (A0,B0)(A1,B2)(A2,B4)(A3,B6), " + "chain 1 the B1,B3,B5,B7 partner, chains 2/3 the " + "same over B8..B15"), + "gemm_real": {"M": 64, "N": 64, "K": 128}, + "a": {"source": "normed_tile", "from_phase": 14, + "note": "all sixteen odd phases read the SAME normed tile E14 " + "produced from phase 14's D"}, + "b": _b(_ODD_W[odd], 32), + "c": {"kind": "column_bias", "base": _ODD_BIAS[odd], "words": 4, + "addr": "W + ((laneid<<2)&12) + bias + 16*i", + "used": "both halves of each mma's C operand"}, + "epilogue": { + "name": "E15" if i == 0 else f"E{2 * odd + 1}", + "ops": ["clamped cubic activation", "pack -> the even phase's A", + "load the even phase's B"], + "activation": { + "y": "clamp(x, -2, +2)", + "g": "0.5 + y*(0.412109375 - 0.0810546875*|y|)", + "out": "x * g", + }, + "next_table": _TBL_P16 if i == 0 else None, + "next_table_adds_phase": 14 if i == 0 else None, + "next_w": _EVEN_W[even], + }, + }) + out.append({ + "n": even, + "name": f"mlp_down{even - 15}", + "gemm": _gemm(1, 16, 1, 16, True, 16), + "a": {"source": "activation", "from_phase": odd}, + "b": _b(_EVEN_W[even], 32), + "c": ({"kind": "accumulator_plus_table", "from_phase": 14, + "table": _TBL_P16} if even == 16 + else {"kind": "accumulator", "from_phase": even - 2}), + "epilogue": { + "name": "E16" if even == 16 else f"E{even + 2}", + "ops": ["e4m3 requantise and pack", "load the next odd phase's B", + "load the next odd phase's C bias"], + "next_w": _ODD_W[odd + 2] if even < 46 else None, + "next_bias": _ODD_BIAS[odd + 2] if even < 46 else None, + }, + }) + + # ---- phase 47: the merge --------------------------------------------- + out.append({ + "n": 47, + "name": "merge", + "gemm": _gemm(16, 64, 16, 4, False, 64, + band="chain 0 is (A_j, B_{2j}), chain 1 (A_j, B_{2j+1}), " + "chains 2/3 the same over B32..B63, j = 0..15"), + "gemm_real": {"M": 256, "N": 256, "K": 512}, + "a": {"source": "shared_arena", "fragments": 16, + "addr": "smem + 16*g + t and +128, at byte offsets {0,1024,...,7168}", + "already_e4m3": True}, + "b": _b(231424, 128), + "c": {"kind": "column_bias", "base": 313344, "words": 4, + "addr": "W + ((laneid<<2)&12) + 313344 + 16*i"}, + "epilogue": { + "name": "E47", + "range": [16728, 16852], + "ops": ["e4m3 requantise and pack", "surface scatter to param+56", + "load phase 48's B and C"], + "surface_stores": 4, + "surface_index": "(y<0)|(y>=(ey>>1))|(laneid>63)|(x<0)|(x>=(ex>>1))|" + "(loop counter > 159); y = (origin_y>>1) + (laneid>>4), " + "x = (origin_x>>1) + ((laneid>>2)&3), second base uses g+8", + "loop": {"steps_by": 128, "while": "< 160", + "unverified": "rrswin_enc3_epilogues.md U4: whether the body " + "runs once or twice per tid.z could not be " + "decided from the PTX alone"}, + }, + }) + + # ---- phase 48: the tail ---------------------------------------------- + out.append({ + "n": 48, + "name": "tail", + "gemm": _gemm(4, 8, 4, 2, False, 8, + band="(A_j, B_{2j}) and (A_j, B_{2j+1}) for j = 0..3"), + "gemm_real": {"M": 64, "N": 32, "K": 128}, + "a": {"source": "phase47_surface_pack", "from_phase": 47}, + "b": _b(313664, 16), + "c": {"kind": "column_bias", "base": 315712, "words": 2, + "addr": "W + ((laneid<<2)&12) + 315712 / +315728"}, + "returns": ["%r23106", "%r23107", "%r23116", "%r23117"], + "returns_note": "the four accumulators the surviving epilogue reads", + "epilogue": { + "name": "E48", + "range": [16861, 17183], + "ops": ["shared staging of phase 48's D", "bar.sync", + "row maximum (unlike E9)", + "exp2 via mul.ftz by 0f3FB8AA3B", + "1/rowsum via div.approx.ftz.f32", + "3x3 texture gather from param+88 with clamped coordinates", + "fma.rn.f16x2 weighted sum", + "second sigmoid", "(acc - sigmoid(acc)) * 0.25", + "two-step cross-lane sum (shfl.down delta 1 then 8, twice)", + "three sust.b.2d.v4.b16.zero"], + "surfaces": [112, 120, 128], + "third_surface_note": "taken only when %r398 & 1; fourth channel 0", + "meaning": {"unverified": "rrswin_enc3_epilogues.md U8: the logical " + "meaning of (acc - sigmoid(acc)) * 0.25 " + "over the 3x3 stencil is not derivable " + "from the PTX"}, + }, + }) + + return out + + +def epilogue_index(): + """Statement ranges of every distinct epilogue, for the engine's scheduler. + + The odd/even MLP epilogues repeat, so only the first of each family is listed + with its own range; `repeats` says how many times the body runs unchanged.""" + return { + "E1..E7": {"ranges": [[6148, 6154], [6179, 6185], [6210, 6216], + [6241, 6247], [6272, 6278], [6303, 6309], + [6334, 6340]], + "ops": ["load the next phase's B"]}, + "E9": {"range": [6584, 10426], "ops": ["score softmax", "V transpose"]}, + "E10": {"range": [10475, 10673], + "ops": ["pack", "shared staging", "table + residual"]}, + "E11..E13": {"ranges": [[10690, 10712], [10729, 10751], [10768, 10790]], + "ops": ["shared re-read as the next A", "load the next B"]}, + "E14": {"range": [10807, 11638], "ops": ["row-RMS norm", "pack"]}, + "E15": {"range": [11655, 11943], + "ops": ["clamped cubic", "column table + residual", "pack"]}, + "E16": {"range": [11960, 12035], "repeats": 15, + "ops": ["pack the normed tile", "load the next B and C"]}, + "E17": {"range": [12052, 12219], "repeats": 16, + "ops": ["clamped cubic", "pack", "load the next B"]}, + "E46": {"range": [16100, 16663], + "ops": ["pack", "plane-arena scatter", "shared staging", + "load the next B and C"], + "scatter_unverified": "rrswin_enc3_epilogues.md U4: the store " + "index splits as t + 4*(g&7) + 32*y with " + "y = (tid.z<<1) + (laneid>>5) for the first " + "group and (tid.z<<1) + ((g+8)>>3) for the " + "second, but the store-to-load permutation " + "was not provable from the PTX alone"}, + "E47": {"range": [16728, 16852], "ops": ["pack", "surface scatter"]}, + "E48": {"range": [16861, 17183], + "ops": ["softmax", "texture gather", "surface stores"]}, + } + + +def open_questions(): + """The descriptor items that are NOT settled, with the reason.""" + return { + "shared_arena_tid_z": "rrswin_enc3_epilogues.md U3: the prologue writes at " + "smem + (tid.z<<11) + 16*laneid + {0,512,1024,1536} " + "and {8192..9728}, while phases 1..8 read at " + "smem + 16*laneid + 512*k with NO tid.z term, so one " + "of the two index derivations is not reconstructible " + "from the PTX alone", + "e46_scatter": "rrswin_enc3_epilogues.md U4", + "e47_loop_count": "rrswin_enc3_epilogues.md U4", + "score_bias_identity": "rrswin_enc3_epilogues.md U1: the 11792-byte table " + "at W+8448 is indexed and its role is computable, " + "but whether it is a relative position bias, a " + "learned score bias or a per-lane constant is not " + "decidable from the PTX", + "column_tables": "rrswin_enc3_epilogues.md U2: W+98560, W+98816 and " + "W+107328 are all read through the same column-indexed " + "pattern; their roles are computed here, their model " + "names are not", + "prologue_residual": "rrswin_enc3_epilogues.md U7: the long-lived f16 " + "vector phase 11's C adds traces back to e4m3 values " + "loaded from the plane at param+8; what that plane " + "holds is not determinable", + "mlp_shape": "rrswin_enc3_epilogues.md U5: whether the 16 pairs are one " + "wide MLP or a stack of residual blocks is a model-level " + "question the PTX cannot answer", + "stem_shape": "rrswin_enc3_epilogues.md U6: the four shift groups read as " + "a 2x2 stencil or a 4-tap 1-D convolution; enc4 has five " + "groups and ten phases, so the tap count is per-stage", + "tail_meaning": "rrswin_enc3_epilogues.md U8", + } \ No newline at end of file diff --git a/kernels/rr/descriptor_enc4.py b/kernels/rr/descriptor_enc4.py new file mode 100644 index 0000000..dc2f7fc --- /dev/null +++ b/kernels/rr/descriptor_enc4.py @@ -0,0 +1,2315 @@ +"""Descriptor for `cuda_dldn_engine_swin_enc4_kernel` (Ray Reconstruction denoiser, encoder 4). + +Machine-readable form of the layer's 62-phase mma region, for the parameterised WMMA engine. +`layer()` carries the launch geometry and argument map; `phases()` carries one entry per +phase, in mma-statement order, with the GEMM shape, where A and C come from, how the 32-deep k +splits into k16 WMMA steps, and what the epilogue does. + +Provenance of every number: + * shapes, weight-image byte ranges, C-source byte offsets, mma and epilogue statement + ranges: `python3 kernels/rr/rr_layer_spec.py enc4`, which derives them from + `~/.cache/d4r-rr-corpus/0017-PREPASS_ENTRYPOINT_NAME.ptx`. + * A/C semantics and epilogue contents: `kernels/rr/rrswin_enc4_epilogues.md`. + * phases 1-11 of the arithmetic were additionally verified bit-exact against debug-oracle + stages e4a, e4p1..e4p12 (see kernels/rr/swin_enc4_recipe.py); the rest is transcription of + the epilogue document and is *not* arithmetic-verified. +""" + +ENTRY = "cuda_dldn_engine_swin_enc4_kernel" +MODULE = "0017-PREPASS_ENTRYPOINT_NAME.ptx" + +WEIGHT_IMAGE_BYTES = 533844 +WEIGHT_IMAGE_SLOTS = 2522 + + +def layer(): + """Launch geometry and argument map, as measured from the corpus PTX and the launch dump. + + The block is one 8x8 token patch with four waves (tid.z bounds to 0..3); the four waves read + different weight slices, so tid.z is part of every per-wave address. + """ + return { + "entry": ENTRY, + "module": MODULE, + "grid": [11, 7, 1], + "block": [32, 1, 4], + "waves_per_block": 4, + "token_grid": [80, 46], + "tokens_per_block": [8, 8], + "param_block_bytes": 144, + "arguments": { + "arg008": {"param_offset": 8, "kind": "input_plane", + "block_bytes": 65945600, "arena_offset_in_block": 39567360, + "note": "the plane arena / debug region; reached as param_0+80-72"}, + "arg040": {"param_offset": 40, "kind": "weight_image", + "block_bytes": 533856, "slots": 2522}, + "arg088": {"param_offset": 88, "kind": "texture", "shape": [80, 46, 4]}, + "arg112": {"param_offset": 112, "kind": "surface", "shape": [80, 46, 4]}, + "arg120": {"param_offset": 120, "kind": "surface", "shape": [80, 46, 4]}, + "arg128": {"param_offset": 128, "kind": "surface", "shape": [40, 23, 4]}, + }, + "indirect_params": { + "param+0": "extents (ex, ey), ld.param.v2.u32", + "param+48": "plane arena, reached as param_0+80-32 (s19817); not a dumped argument", + "param+56": "small output buffer, reached as param_0+80-24 (s21037)", + "param+80": "two u16 block-origin offsets, ld.param.v2.u16 (s1033)", + }, + "shared_arena_bytes": 16384, + "unverified": { + "grid_block": ("taken from the layer's own recipe comment; the launch dump records" + " resources but not the launch dimensions, so 11x7x4 was not" + " re-measured here"), + }, + } + + +def phases(): + """One entry per mma phase, in order.""" + return [ + { + "phase": 1, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [320, 844], + "c_source_bytes": [], + "mma_stmt_range": [7554, 7577], + "epilogue_statements": 7, + "epilogue_stmt_range": [7578, 7584], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 0, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'zero', + 'note': '%r11676, set to 0 at PTX line 11871 (s7547)', + 'evidence': 'rrswin_enc4_epilogues.md 3/E1..E9; recipe A/C operands', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7578, 7584], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 2, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [5440, 5964], + "c_source_bytes": [], + "mma_stmt_range": [7585, 7608], + "epilogue_statements": 7, + "epilogue_stmt_range": [7609, 7615], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 0, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'zero', + 'note': '%r11676, set to 0 at PTX line 11871 (s7547)', + 'evidence': 'rrswin_enc4_epilogues.md 3/E1..E9; recipe A/C operands', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7609, 7615], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 3, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [1344, 1868], + "c_source_bytes": [], + "mma_stmt_range": [7616, 7639], + "epilogue_statements": 7, + "epilogue_stmt_range": [7640, 7646], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 1, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 1, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7640, 7646], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 4, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [6464, 6988], + "c_source_bytes": [], + "mma_stmt_range": [7647, 7670], + "epilogue_statements": 7, + "epilogue_stmt_range": [7671, 7677], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 1, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 2, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7671, 7677], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 5, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [2368, 2892], + "c_source_bytes": [], + "mma_stmt_range": [7678, 7701], + "epilogue_statements": 7, + "epilogue_stmt_range": [7702, 7708], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 2, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 3, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7702, 7708], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 6, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [7488, 8012], + "c_source_bytes": [], + "mma_stmt_range": [7709, 7732], + "epilogue_statements": 7, + "epilogue_stmt_range": [7733, 7739], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 2, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 4, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7733, 7739], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 7, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [3392, 3916], + "c_source_bytes": [], + "mma_stmt_range": [7740, 7763], + "epilogue_statements": 7, + "epilogue_stmt_range": [7764, 7770], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 3, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 5, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7764, 7770], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 8, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [8512, 9036], + "c_source_bytes": [], + "mma_stmt_range": [7771, 7794], + "epilogue_statements": 7, + "epilogue_stmt_range": [7795, 7801], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 3, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 6, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7795, 7801], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 9, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [4416, 4940], + "c_source_bytes": [], + "mma_stmt_range": [7802, 7825], + "epilogue_statements": 7, + "epilogue_stmt_range": [7826, 7832], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 4, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 7, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['next_b_load'], + 'statements': 7, + 'stmt_range': [7826, 7832], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 10, + "gemm": { + "m_tiles": 6, + "n_tiles": 4, + "k": 32, + "k_chain_len": 1, + "mma": 24, + "chains": 24, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [9536, 10060], + "c_source_bytes": [], + "mma_stmt_range": [7833, 7856], + "epilogue_statements": 171, + "epilogue_stmt_range": [7857, 8027], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': 4, + 'arena_byte_offsets_per_mtile': [0, 2560, 5120, 7680, 10240, 12800], + 'note': 'shift group 0 is handed across the cut as 24 A registers; groups 1-4 are read from the shared arena, which the prologue staged per wave at base tid.z*2560', + 'evidence': 'rrswin_enc4_epilogues.md 1.4; mma A operands at PTX lines 11883-12044 name %r11754 %r11774 %r11794 %r11814 %r11834 %r11854, i.e. offsets [0, 2560, 5120, 7680, 10240, 12800]', + }, + "c_operand": { + 'kind': 'prev_chain_acc', + 'from_phase': 8, + 'note': "phase p's mma i reads phase p-2's D pair as its C, same (m-tile,row,n-tile)", + 'evidence': 'rrswin_enc4_epilogues.md 3/E13..E19 chain note; verified by debug oracle stages e4p3..e4p10', + }, + "epilogue": { + 'ops': ['e4m3_requantise', 'pack_next_a', 'load_next_b', 'load_next_c'], + 'statements': 171, + 'stmt_range': [7857, 8027], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 11, + "gemm": { + "m_tiles": 4, + "n_tiles": 12, + "k": 32, + "k_chain_len": 1, + "mma": 48, + "chains": 48, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": None, + "c_source_bytes": [10560, 10564, 10568, 10572, 11072, 11076, 11080, 11084, 11584, 11588, 11592, 11596, 12096, 12100, 12104, 12108, 12608, 12612, 12616, 12620, 13120, 13124, 13128, 13132, 13632, 13636, 13640, 13644, 14144, 14148, 14152, 14156, 14656, 14660, 14664, 14668, 15168, 15172, 15176, 15180, 15680, 15684, 15688, 15692, 16192, 16196, 16200, 16204, 16704, 16708, 16712, 16716, 17216, 17220, 17224, 17228, 17728, 17732, 17736, 17740, 18240, 18244, 18248, 18252, 18752, 18756, 18760, 18764, 19264, 19268, 19272, 19276, 19776, 19780, 19784, 19788, 20288, 20292, 20296, 20300, 20800, 20804, 20808, 20812, 21312, 21316, 21320, 21324, 21824, 21828, 21832, 21836, 22336, 22340, 22344, 22348], + "mma_stmt_range": [8028, 8075], + "epilogue_statements": 3844, + "epilogue_stmt_range": [8076, 11919], + }, + "a_source": { + 'kind': 'requantise_prev_acc', + 'from_phase': 9, + 'how': "E10 packs D9's f16x2 to e4m3 (cvt.rn.satfinite.e4m3x2.f16x2, 80 packs)", + 'evidence': "rrswin_enc4_epilogues.md 3/E10; stage classification 'after phase 10 e4m3-pack:80@s7908'", + }, + "c_operand": { + 'kind': 'bias_pair_f16', + 'note': 'per (m-tile,row,n-tile) f16 pair from the wave slice at 10560 + 512*(a + 4*(nt>>1)) + 16*lane + 4*(2*(nt&1)+row)', + 'evidence': 'rrswin_enc4_epilogues.md 3/E11; the 512-byte A-tile stride is confirmed at s8028-s8040', + }, + "epilogue": { + 'ops': ['e4m3_requantise', 'softmax', 'transpose_pack'], + 'statements': 3844, + 'stmt_range': [8076, 11919], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 12, + "gemm": { + "m_tiles": 12, + "n_tiles": 12, + "k": 96, + "k_chain_len": 3, + "mma": 48, + "chains": 16, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 3 mma chained along k', + "weight_bytes": None, + "c_source_bytes": [], + "mma_stmt_range": [11920, 11967], + "epilogue_statements": 274, + "epilogue_stmt_range": [11968, 12241], + }, + "a_source": { + 'kind': 'requantise_softmax', + 'from': 'E11 score softmax output', + 'how': "probabilities f16x2 -> e4m3, packed as phase 12's A fragments", + 'evidence': 'rrswin_enc4_epilogues.md 3/E11, 3/E12(a)', + }, + "c_operand": { + 'kind': 'zero', + 'evidence': "rrswin_enc4_epilogues.md 3 'P12 ... C = 0'", + }, + "epilogue": { + 'ops': ['e4m3_requantise', 'shared_stage', 'column_table_load', 'residual_add', 'next_b_load'], + 'statements': 274, + 'stmt_range': [11968, 12241], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 13, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [22848, 27468], + "c_source_bytes": [], + "mma_stmt_range": [12242, 12261], + "epilogue_statements": 27, + "epilogue_stmt_range": [12262, 12288], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 0', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12262, 12288], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 14, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [50496, 55116], + "c_source_bytes": [], + "mma_stmt_range": [12289, 12308], + "epilogue_statements": 27, + "epilogue_stmt_range": [12309, 12335], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 2048', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12309, 12335], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 15, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [78144, 82764], + "c_source_bytes": [], + "mma_stmt_range": [12336, 12355], + "epilogue_statements": 27, + "epilogue_stmt_range": [12356, 12382], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 4096', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12356, 12382], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 16, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [105792, 110412], + "c_source_bytes": [], + "mma_stmt_range": [12383, 12402], + "epilogue_statements": 27, + "epilogue_stmt_range": [12403, 12429], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 6144', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12403, 12429], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 17, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [133440, 138060], + "c_source_bytes": [], + "mma_stmt_range": [12430, 12449], + "epilogue_statements": 27, + "epilogue_stmt_range": [12450, 12476], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 8192', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12450, 12476], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 18, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [161088, 165708], + "c_source_bytes": [], + "mma_stmt_range": [12477, 12496], + "epilogue_statements": 27, + "epilogue_stmt_range": [12497, 12523], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 10240', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12497, 12523], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 19, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [188736, 193356], + "c_source_bytes": [], + "mma_stmt_range": [12524, 12543], + "epilogue_statements": 27, + "epilogue_stmt_range": [12544, 12570], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 12288', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'bias_plus_residual', + 'note': 'f16 column table at W + 221504 + 16*i added to the long-lived residual', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(e,f)', + }, + "epilogue": { + 'ops': ['shared_load_next_a', 'next_b_load'], + 'statements': 27, + 'stmt_range': [12544, 12570], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 20, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [216384, 221004], + "c_source_bytes": [], + "mma_stmt_range": [12571, 12590], + "epilogue_statements": 1029, + "epilogue_stmt_range": [12591, 13619], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E12 at arena + (tid.z<<11) + 16*lane + {0,512,1024,1536}', + 'read_at': 'arena + (tid.z<<9) + 16*lane + 14336', + 'evidence': 'rrswin_enc4_epilogues.md 3/E12(a,c), 3/E13..E19', + 'unverified': "E12's store side uses tid.z<<11 while its read-back uses tid.z<<9; the doc records both verbatim and the mismatch is not resolved", + }, + "c_operand": { + 'kind': 'prev_acc', + 'from_phase': 19, + 'evidence': "rrswin_enc4_epilogues.md 3 'P20 ... C = D19'", + }, + "epilogue": { + 'ops': ['rms_norm', 'e4m3_requantise', 'gain_load', 'next_b_load', 'next_c_load'], + 'statements': 1029, + 'stmt_range': [12591, 13619], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 21, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [222144, 226764], + "c_source_bytes": [227264, 227280, 227296, 227312], + "mma_stmt_range": [13620, 13639], + "epilogue_statements": 321, + "epilogue_stmt_range": [13640, 13960], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [227264, 227280, 227296, 227312], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 321, + 'stmt_range': [13640, 13960], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 22, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [227328, 231948], + "c_source_bytes": [], + "mma_stmt_range": [13961, 13980], + "epilogue_statements": 92, + "epilogue_stmt_range": [13981, 14072], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 21, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 20, + 'table_bytes': 232464, + 'evidence': 'rrswin_enc4_epilogues.md 3/E21(b)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'column_table_load', 'residual_add', 'pack_next_a', 'next_b_load'], + 'statements': 92, + 'stmt_range': [13981, 14072], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 23, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [232768, 237388], + "c_source_bytes": [237888, 237904, 237920, 237936], + "mma_stmt_range": [14073, 14092], + "epilogue_statements": 172, + "epilogue_stmt_range": [14093, 14264], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [237888, 237904, 237920, 237936], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [14093, 14264], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 24, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [237952, 242572], + "c_source_bytes": [], + "mma_stmt_range": [14265, 14284], + "epilogue_statements": 92, + "epilogue_stmt_range": [14285, 14376], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 23, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 22, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [14285, 14376], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 25, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [243072, 247692], + "c_source_bytes": [248192, 248208, 248224, 248240], + "mma_stmt_range": [14377, 14396], + "epilogue_statements": 172, + "epilogue_stmt_range": [14397, 14568], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [248192, 248208, 248224, 248240], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [14397, 14568], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 26, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [248256, 252876], + "c_source_bytes": [], + "mma_stmt_range": [14569, 14588], + "epilogue_statements": 92, + "epilogue_stmt_range": [14589, 14680], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 25, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 24, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [14589, 14680], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 27, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [253376, 257996], + "c_source_bytes": [258496, 258512, 258528, 258544], + "mma_stmt_range": [14681, 14700], + "epilogue_statements": 172, + "epilogue_stmt_range": [14701, 14872], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... 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A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [361536, 361552, 361568, 361584], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [17741, 17912], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 48, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [361600, 366220], + "c_source_bytes": [], + "mma_stmt_range": [17913, 17932], + "epilogue_statements": 92, + "epilogue_stmt_range": [17933, 18024], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 47, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 46, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [17933, 18024], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 49, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [366720, 371340], + "c_source_bytes": [371840, 371856, 371872, 371888], + "mma_stmt_range": [18025, 18044], + "epilogue_statements": 172, + "epilogue_stmt_range": [18045, 18216], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [371840, 371856, 371872, 371888], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [18045, 18216], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 50, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [371904, 376524], + "c_source_bytes": [], + "mma_stmt_range": [18217, 18236], + "epilogue_statements": 92, + "epilogue_stmt_range": [18237, 18328], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 49, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 48, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [18237, 18328], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 51, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [377024, 381644], + "c_source_bytes": [382144, 382160, 382176, 382192], + "mma_stmt_range": [18329, 18348], + "epilogue_statements": 172, + "epilogue_stmt_range": [18349, 18520], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [382144, 382160, 382176, 382192], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [18349, 18520], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 52, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [382208, 386828], + "c_source_bytes": [], + "mma_stmt_range": [18521, 18540], + "epilogue_statements": 92, + "epilogue_stmt_range": [18541, 18632], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 51, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 50, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [18541, 18632], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 53, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [387328, 391948], + "c_source_bytes": [392448, 392464, 392480, 392496], + "mma_stmt_range": [18633, 18652], + "epilogue_statements": 172, + "epilogue_stmt_range": [18653, 18824], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [392448, 392464, 392480, 392496], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [18653, 18824], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 54, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [392512, 397132], + "c_source_bytes": [], + "mma_stmt_range": [18825, 18844], + "epilogue_statements": 92, + "epilogue_stmt_range": [18845, 18936], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 53, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 52, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [18845, 18936], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 55, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [397632, 402252], + "c_source_bytes": [402752, 402768, 402784, 402800], + "mma_stmt_range": [18937, 18956], + "epilogue_statements": 172, + "epilogue_stmt_range": [18957, 19128], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [402752, 402768, 402784, 402800], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [18957, 19128], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 56, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [402816, 407436], + "c_source_bytes": [], + "mma_stmt_range": [19129, 19148], + "epilogue_statements": 92, + "epilogue_stmt_range": [19149, 19240], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 55, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 54, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [19149, 19240], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 57, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [407936, 412556], + "c_source_bytes": [413056, 413072, 413088, 413104], + "mma_stmt_range": [19241, 19260], + "epilogue_statements": 172, + "epilogue_stmt_range": [19261, 19432], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [413056, 413072, 413088, 413104], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [19261, 19432], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 58, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [413120, 417740], + "c_source_bytes": [], + "mma_stmt_range": [19433, 19452], + "epilogue_statements": 92, + "epilogue_stmt_range": [19453, 19544], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 57, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 56, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'pack_next_a', 'next_b_load', 'next_c_load'], + 'statements': 92, + 'stmt_range': [19453, 19544], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 59, + "gemm": { + "m_tiles": 5, + "n_tiles": 20, + "k": 160, + "k_chain_len": 5, + "mma": 20, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [418240, 422860], + "c_source_bytes": [423360, 423376, 423392, 423408], + "mma_stmt_range": [19545, 19564], + "epilogue_statements": 172, + "epilogue_stmt_range": [19565, 19736], + }, + "a_source": { + 'kind': 'normalised_tile', + 'from_phase': 20, + 'how': 'E20 row-RMS-normalised tile (rsqrt.approx.ftz.f32, gain at 221824) -> e4m3', + 'evidence': "rrswin_enc4_epilogues.md 3/E20, and the shape summary 'P21/P23 ... A = normed tile'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [423360, 423376, 423392, 423408], + 'note': 'one f16 pair per lane, read at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': 'rrswin_enc4_epilogues.md 3/E20, 3/E22..E58 (the bias words of the next odd phase)', + }, + "epilogue": { + 'ops': ['clamped_cubic_activation', 'e4m3_requantise', 'next_b_load'], + 'statements': 172, + 'stmt_range': [19565, 19736], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 60, + "gemm": { + "m_tiles": 1, + "n_tiles": 20, + "k": 32, + "k_chain_len": 1, + "mma": 20, + "chains": 20, + "banded": False, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma', + "weight_bytes": [423424, 428044], + "c_source_bytes": [], + "mma_stmt_range": [19737, 19756], + "epilogue_statements": 1381, + "epilogue_stmt_range": [19757, 21137], + }, + "a_source": { + 'kind': 'requantise_activation', + 'from_phase': 59, + 'how': "clamped cubic activation of the previous phase's D, f16 -> e4m3", + 'evidence': 'rrswin_enc4_epilogues.md 3/E21, 3/E23..E59 (pack of the activation outputs)', + }, + "c_operand": { + 'kind': 'prev_acc_plus_table', + 'from_phase': 58, + 'evidence': 'rrswin_enc4_epilogues.md 3/E23..E59 op mix (identical to E21 minus the table loads)', + 'unverified': 'E23..E59 have no table load, so whether phases 24..60 add a column table to their seed, and at which offset, is not pinned by the PTX', + }, + "epilogue": { + 'ops': ['pack_next_a', 'plane_scatter', 'shared_stage', 'next_b_load', 'next_c_load'], + 'statements': 1381, + 'stmt_range': [19757, 21137], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 61, + "gemm": { + "m_tiles": 20, + "n_tiles": 80, + "k": 640, + "k_chain_len": 20, + "mma": 80, + "chains": 4, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 20 mma chained along k', + "weight_bytes": [428544, 448524], + "c_source_bytes": [530944, 530960, 530976, 530992], + "mma_stmt_range": [21138, 21217], + "epilogue_statements": 117, + "epilogue_stmt_range": [21218, 21334], + }, + "a_source": { + 'kind': 'shared_staged_e4m3', + 'shift_group': None, + 'written_by': 'E60 stages 20 u32 per lane into the shared arena (s20051-s20215)', + 'read_at': 'arena + idx2<<2 + {0,1024,...,7168} (80 ld.shared.u32, s20242-s21030)', + 'evidence': "rrswin_enc4_epilogues.md 3/E60(c,d); the shape summary 'P61 A = 20 shared slots'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [530944, 530960, 530976, 530992], + 'note': 'one f16 pair per lane at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': "rrswin_enc4_epilogues.md 3 'P61 C = bias@530944', 3 'P62 C = bias@533824'", + }, + "epilogue": { + 'ops': ['pack_next_a', 'surface_scatter', 'next_b_load', 'next_c_load'], + 'statements': 117, + 'stmt_range': [21218, 21334], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + { + "phase": 62, + "gemm": { + "m_tiles": 5, + "n_tiles": 10, + "k": 160, + "k_chain_len": 5, + "mma": 10, + "chains": 2, + "banded": True, + "k_tiling": '32-deep per mma, so 2 k16 WMMA steps per mma; 5 mma chained along k', + "weight_bytes": [531264, 533324], + "c_source_bytes": [533824, 533840], + "mma_stmt_range": [21335, 21344], + "epilogue_statements": 323, + "epilogue_stmt_range": [21345, 21667], + }, + "a_source": { + 'kind': 'requantise_prev_acc', + 'from_phase': 61, + 'how': "E61 packs phase 61's D to e4m3", + 'evidence': "rrswin_enc4_epilogues.md 3 'P62 A = pack(E61)'", + }, + "c_operand": { + 'kind': 'bias_word', + 'bytes': [533824, 533840], + 'note': 'one f16 pair per lane at W + ((laneid<<2)&12) + offset + 16*i', + 'evidence': "rrswin_enc4_epilogues.md 3 'P61 C = bias@530944', 3 'P62 C = bias@533824'", + }, + "epilogue": { + 'ops': ['lane_merge', 'texture_read', 'surface_scatter'], + 'statements': 323, + 'stmt_range': [21345, 21667], + 'evidence': 'rrswin_enc4_epilogues.md 3, per-epilogue sections', + }, + }, + ] diff --git a/kernels/rr/rr_layer_spec.py b/kernels/rr/rr_layer_spec.py index 9083792..005ef83 100755 --- a/kernels/rr/rr_layer_spec.py +++ b/kernels/rr/rr_layer_spec.py @@ -784,7 +784,7 @@ def print_cut_abi(stmts, phases, defs, entry, path, lines, body): live = live_across(stmts, lo, hi) print(f" returns {len(live)} accumulators written in the region and " f"read after s{hi}") - print(f" {live[:12]}{' ...' if len(live) > 12 else ''}") + print(f" {live}") weight_b = sorted({m.B for p in phases for m in p.mma}) print(f" weight image {len(weight_b)} distinct B fragments; byte ranges " f"per phase are in the table above") diff --git a/kernels/rr/rrswin_dec0.hip b/kernels/rr/rrswin_dec0.hip new file mode 100644 index 0000000..74e6ab2 --- /dev/null +++ b/kernels/rr/rrswin_dec0.hip @@ -0,0 +1,376 @@ +// Native replacement for the Ray Reconstruction denoiser's first Swin decoder, +// cuda_dldn_engine_swin_dec0_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: phase 1 (the 48x128x64 patch GEMM, three m-tiles of 16, sixteen n-tiles +// of 8, two k32 steps) is implemented and bit-exact against the debug oracle; +// phases 2-19 are not, so the layer's output is still the known-bad baseline. +// See "Validation" at the bottom for what has been compared byte for byte. +// +// --------------------------------------------------------------------------- +// The kernel is one warp per 8x8 token patch: grid (161, 93, 1), block +// (32, 1, 1) -- one wave, so every %tid.z term is absent from the addressing -- +// 14973 blocks, parameter block 152 bytes. The PTX this file replaces is +// kernels/extracted/rr/0023-PREPASS_ENTRYPOINT_NAME.ptx. +// +// kernels/tex/make_ptx.py's recipe (kernels/rr/swin_dec0_recipe.py, +// D4R_RRSWIN_CUT=1) keeps NVIDIA's plane/texture prologue (lines 1-1392) and its +// surface epilogue (46264-end) and replaces the 544 mma of the 19 phases with the +// call below. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinDec0Params +{ + uint8_t raw[152]; +}; +static_assert(sizeof(DldnSwinDec0Params) == 152, "parameter block"); + +enum : int +{ + kIn = 8, // the e4m3 input buffer, already in phase 1's A fragment order + kSkip = 24, // the skip input E1 adds to the staged patch + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // the output buffer (arg048); make_ptx.py's debug splice writes here + kBlockOff = 80, // the block origin, read as a v2.u16 + kScale = 136, // the texture coordinate scale/origin (E19) +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// Byte offset, from a phase's own base, of the e4m3 weight element (k, Xt) of +// weight tile T, where Xt is the column inside the 512-byte tile (0..15). +// +// A tile is 32 lanes x 16 bytes: lane 4*g+t holds the two fragments of n-tiles +// 2*(T-ks) and 2*(T-ks)+1 at bytes 0..7 and 8..15. The mma's B fragment holds +// the lane's two *columns* 2t and 2t+1, four k values each (B is read as +// [n][k], and D's columns are 2t, 2t+1), so byte b of register r is +// n = 8*(Xt>>3) + (Xt&1), k = with lane = 4*g'+t. +// That fixes the address from the element's (k, column): +// bit 0 = k&1, bit 1 = (k>>4)&1, bit 2 = column&1, bit 3 = column>>3, +// bits 4-5 = (column>>1)&3, bits 6-8 = g'. +// Phase 1's tile index is T = 2*(nt>>1) + ks (the two k slices of an n-tile pair +// sit in the two 512-byte tiles that pair occupies), and Xt = 8*(nt&1) + 2t + c. +DEVF uint32_t w_byte(int k, int Xt, int T) +{ + return 512u * (uint32_t)T + 8u * (uint32_t)(Xt >> 3) + 4u * (uint32_t)(Xt & 1) + + 16u * (uint32_t)((Xt >> 1) & 3) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1) + 64u * (uint32_t)((k >> 1) & 7); +} + +// The same map for the other candidate: byte b holds four *consecutive* k, so +// k = 4*g' + b and the address takes bits 0-1 from k&3 and bits 6-8 from k>>2. +// Both maps are bijections of the 32 k x 16 columns onto the 512-byte tile, so +// only the oracle can say which one NVIDIA's mma uses; D4R_RRSWIN_DEBUG_PROBE +// stores both. +DEVF uint32_t w_byte_c(int k, int Xt, int T) +{ + return 512u * (uint32_t)T + 8u * (uint32_t)(Xt >> 3) + 4u * (uint32_t)(Xt & 1) + + 16u * (uint32_t)((Xt >> 1) & 3) + (uint32_t)(k & 3) + + 64u * (uint32_t)(k >> 2); +} + +// warp butterfly over the four lanes that hold a row's 32 k values (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +DEVF void gemm_p1(const uint32_t* as, const uint32_t* seed, const uint8_t* w, int t, + int g, int aord, int apat, int bpat, uint32_t d[3][2][16]) +{ + for (int nt = 0; nt < 16; ++nt) { + const uint32_t bias = seed[nt]; + for (int mi = 0; mi < 3; ++mi) { + half_t prev[2][2]; +#pragma unroll + for (int row = 0; row < 2; ++row) { + for (int c = 0; c < 2; ++c) { + prev[row][c] = __builtin_bit_cast(half_t, (uint16_t)0); + } + } + for (int ks = 0; ks < 2; ++ks) { + const int T = 2 * (nt >> 1) + ks; + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int Xt = 8 * (nt & 1) + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[bpat ? w_byte_c(k, Xt, T) + : w_byte(k, Xt, T)]); + } + } + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int kg = 0; kg < 2; ++kg) { + for (int row = 0; row < 2; ++row) { + // this lane's word and the same word on lanes t^1, t^2, t^3 + const int idx = aord ? 2 * row + kg : 2 * kg + row; + const uint32_t p0 = as[4 * (2 * mi + ks) + idx]; + uint32_t p[4]; + p[0] = p0; + p[1] = bfly1_bits(p0); + p[2] = bfly2_bits(p0); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + for (int j = 0; j < 4; ++j) { + const int k = apat + ? 16 * kg + 4 * (t ^ m) + j + : 8 * kg + 2 * (t ^ m) + (j & 1) + + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + // the chain's C operand: the bias seed on the first k step, the + // first step's f16 result on the second + for (int row = 0; row < 2; ++row) { + for (int c = 0; c < 2; ++c) { + const float base = ks == 0 + ? h2f(c == 0 ? bias : (bias >> 16)) + : (float)prev[row][c]; + prev[row][c] = (half_t)(acc[row][c] + base); + } + } + } + for (int row = 0; row < 2; ++row) { + d[mi][row][nt] = pair_of(prev[row][0], prev[row][1]); + } + } + } +} + +// --------------------------------------------------------------------------- +// One K=32 GEMM, the shape of phases 2 and 3 (and of every later unfused +// projection): NMI m-tiles of 16 rows x NNT n-tiles of 8 columns, one k32 step, +// no bias. `as` is the phase's A operand in mma operand order (NMI fragments of +// four b32), `d` receives the NMI*NNT tile pairs as d[(mi*NNT + nt)*2 + row], +// the (row g, row g+8) pair of each tile. +// +// The weight image of such a phase is NNT/2 tiles of 512 bytes: sixteen columns +// (two n-tiles) and 32 k values each, at the phase's own byte base -- which is +// not a multiple of 512, so the tile index n>>4 is added to that base rather +// than folded into it. +DEVF void gemm_k32(const uint32_t* as, const uint8_t* w, int base, int nmi, int nnt, + int t, uint32_t* d) +{ + for (int nt = 0; nt < nnt; ++nt) { + for (int mi = 0; mi < nmi; ++mi) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[base + w_byte(k, n, 0)]); + } + } + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + const uint32_t p0 = as[4 * mi + 2 * reg + row]; + uint32_t p[4]; + p[0] = p0; + p[1] = bfly1_bits(p0); + p[2] = bfly2_bits(p0); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + d[(mi * nnt + nt) * 2 + row] = + pair_of((half_t)acc[row][0], (half_t)acc[row][1]); + } + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/tex/make_ptx.py's debug recipe: +// with D4R_RRSWIN_DEBUG= the same splice stores that stage's registers +// into the buffer at arg048 + 46,000,000, which dec0 never writes, and the launch +// dump then holds NVIDIA's values for a block/lane. Built with +// -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this +// body stores the same registers of its own phase n in the same order, so the two +// dumps compare byte for byte. The stage table is kernels/rr/swin_dec0_debug_stages.py. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif +#ifndef D4R_RRSWIN_DEBUG_BASE +// dec0's param_0+48 sits 45,219,840 bytes into the block the launch dump files +// as arg008, so the default 46,000,000 would land past the end of the block and +// every comparison would read ambient memory. 16 MiB keeps the whole +// 64-block payload (64 * 16384) inside it; the oracle splice reads the same +// value from D4R_RRSWIN_DEBUG_BASE. +#define D4R_RRSWIN_DEBUG_BASE 16777216 +#endif + +DEVF void debug_store_off(const uint8_t* prm, const uint32_t* regs, int n, + uint64_t extra, uint64_t slot) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 161u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + uint32_t* dst = (uint32_t*)(arena + (uint64_t)D4R_RRSWIN_DEBUG_BASE + extra + + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + // the oracle's slot, make_ptx.py's swin_debug_slot: 32 lanes x n x 4 bytes, at + // least 8192, rounded up to a power of two (its splice forms block * slot with + // a shl) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + debug_store_off(prm, regs, n, 0, slot); +} + +// --------------------------------------------------------------------------- +// The mirror cut. The six 16-row fragments of the staged patch arrive in the +// order the first mma reads them (m-tile, k-slice), then the sixteen bias seeds, +// the weight image and the parameter block. The accumulators the epilogue reads +// cross back through shared memory, not `call.uni`'s return parameters (see +// kernels/rr/rrswin_enc0.hip for why): `scratch` is the base of the entry's +// `smem` array (3200 bytes of .shared, its last access is inside the cut), and +// swin_dec0_recipe.py reads 25 b32 per lane back out of it, 100 bytes apart. +extern "C" __attribute__((device)) void d4r_swin_dec0( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, + uint32_t a6, uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, + uint32_t a12, uint32_t a13, uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, + uint32_t a18, uint32_t a19, uint32_t a20, uint32_t a21, uint32_t a22, uint32_t a23, + uint32_t c0, uint32_t c1, uint32_t c2, uint32_t c3, uint32_t c4, uint32_t c5, + uint32_t c6, uint32_t c7, uint32_t c8, uint32_t c9, uint32_t c10, uint32_t c11, + uint32_t c12, uint32_t c13, uint32_t c14, uint32_t c15, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[24] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23}; + const uint32_t seed[16] = {c0, c1, c2, c3, c4, c5, c6, c7, + c8, c9, c10, c11, c12, c13, c14, c15}; + // Address space 3 (the shared scratch) explicitly: a generic store lowers to + // flat, which faults. + lds_u32* const out = (lds_u32*)(uintptr_t)scratch + 25 * (uint32_t)lane_id(); + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + const uint32_t lane = lane_id(); + + // ---- phase 1 ----------------------------------------------------------- + uint32_t d1[3][2][16]; // [m-tile][row half][n-tile]: f16 pair + const int g = (int)(lane_id() >> 2); // the lane's column of each n-tile + // measured against the p1 oracle: see the "Validation" note below +#ifndef D4R_RRSWIN_AORD +#define D4R_RRSWIN_AORD 0 +#endif +#ifndef D4R_RRSWIN_APAT +#define D4R_RRSWIN_APAT 0 +#endif + gemm_p1(as1, seed, w, t, g, D4R_RRSWIN_AORD, D4R_RRSWIN_APAT, D4R_RRSWIN_APAT, d1); +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + // the oracle's stage p1: the 48 chain-end accumulator pairs, m-tile major, + // n-tile minor + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 3; ++mi) { + for (int nt = 0; nt < 16; ++nt) { + regs[i++] = d1[mi][0][nt]; + regs[i++] = d1[mi][1][nt]; + } + } + debug_store(prm, regs, 96); + } +#endif + +#ifdef D4R_RRSWIN_DEBUG_PROBE + // The A register order and the A/B byte->k patterns are not determined by + // the PTX, so the four combinations are computed in one launch and stored a + // mebibyte apart; compare_stage.py re-tiles the oracle's payload to match. + for (int v = 0; v < 4; ++v) { + uint32_t dv[3][2][16]; + gemm_p1(as1, seed, w, t, g, v & 1, (v >> 1) & 1, (v >> 1) & 1, dv); + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 3; ++mi) { + for (int nt = 0; nt < 16; ++nt) { + regs[i++] = dv[mi][0][nt]; + regs[i++] = dv[mi][1][nt]; + } + } + debug_store_off(prm, regs, 96, (uint64_t)v * 1048576ull, 16384ull); + } +#endif + + // ---- handing the accumulators back ------------------------------------ + // E19's chains have not been reproduced yet, so the 24 chain values and E1's + // shuffle default are zero; the two constants are reloaded by the splice. + for (int i = 0; i < 25; ++i) { + out[i] = 0u; + } +} diff --git a/kernels/rr/rrswin_dec0_epilogues.md b/kernels/rr/rrswin_dec0_epilogues.md new file mode 100644 index 0000000..36905bb --- /dev/null +++ b/kernels/rr/rrswin_dec0_epilogues.md @@ -0,0 +1,953 @@ +# `cuda_dldn_engine_swin_dec0_kernel` — the epilogues of phases 1…19 + +Companion to `kernels/rr/rr_layer_spec.py dec0`. Everything below was read out +of `~/.cache/d4r-rr-corpus/0023-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec0_kernel` (file lines 1018–47791). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and + the next phase's first `mma`; `Exx` below means *the epilogue of phase xx*. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_dec0_kernel_param_0+40]` (s11, L1039) and + `cvta.to.global.u64 %rd3, %rd2` (s12, L1040). Every + `ld.weak.global.ca.v4.u32` reads `W + 16*laneid + imm`; the table loads read + `W + ((laneid<<2)&12) + imm`. +* `%rd1` = the parameter-block base at `+80`: `mov.b64 %rd25, + cuda_dldn_engine_swin_dec0_kernel_param_0` (s1, L1018) then `add.s64 %rd1, + %rd25, 80` (s4, L1032). So `[%rd1+n]` is `param_0+80+n`, `[%rd1-56]` is + `param_0+24` and `[%rd1-80]` is `param_0+0`. +* `smem` denotes `_ZZ33cuda_dldn_engine_swin_dec0_kernel30DldnEngineSwinDec0ParamsStructE4smem`, + declared 3200 bytes by the cut-ABI dump. +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same + cols)`, `g = laneid>>2`, `t = laneid&3`; the A fragment's four registers are + `reg0 = row g, k = 2t + (j&1) + 16*((j>>1)&1)`, `reg1 = row g+8, same k`, + `reg2 = row g, k+8`, `reg3 = row g+8, k+8`. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, 47376 bytes) | `ld.param.u64 %rd2, [param_0+40]` / `cvta.to.global.u64 %rd3, %rd2` | s11 / s12 | +| `smem` | `mov.u32 %r1706, _ZZ…SwinDec0ParamsStructE4smem` | s560 (L2364) | +| `%rd1` = `param_0+80` | `mov.b64 %rd25, param_0` + `add.s64 %rd1, %rd25, 80` | s1 / s4 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r1527, %r1528}, [param_0]` | s13 (L1041) | +| block offsets `(%rs235, %rs236)` | `ld.param.v2.u16 {%rs235, %rs236}, [param_0+80]` | s5 (L1033) | +| **input buffer** | `ld.param.u64 %rd27, [param_0+8]`, then `cvta %rd28` | s29 / s30 | +| **skip input** | `ld.param.u64 %rd114, [%rd1+-56]` = `param_0+24`, then `cvta %rd4` | s1459 / s1460 | +| **plane arena** | `ld.param.u64 %rd319, [%rd357+-32]` = `param_0+48`, then `cvta %rd320` | s18493 / s18494 | +| **texture A** (18 f32-coord reads) | `ld.param.u64 %rd313, [%rd357+8]` = `param_0+88` | s18702 (L46878) | +| **texture B** (s32-coord reads) | `ld.param.u64 %rd315, [%rd357+16]` = `param_0+96` | s18778 (L47053) | +| **texture C** (s32-coord reads) | `ld.param.u64 %rd317, [%rd357+24]` = `param_0+104` | s18780 (L47057) | +| **surface A** (`sust.b`) | `ld.param.u64 %rd323, [%rd357+32]` = `param_0+112` | s18604 (L46672) | +| **surface B** (`sust.p`) | `ld.param.u64 %rd295, [%rd357+64]` = `param_0+144` | s18602 (L46668) | +| texture coord scale/origin | `ld.param.v2.f32 {%f1602, %f1603}, [%rd357+56]` = `param_0+136` | s18696 (L46872) | +| per-lane weight address | `mul.wide.u32 %rdX, %laneid, 16` + `add.s64 %rdX, %rd3, %rdX` | every load block | +| per-lane *table* address | `shl.b32 %rX, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rdX, %rX, 12` → `add.s64 %rdX, %rd3, %rdX` = `W + ((laneid*4) & 12)` | s306–s309 and 60 copies | + +The last line matters: every `ld.global.v2.u16` / `ld.global.u32` table load in +an epilogue reads `W + ((laneid<<2)&12) + off`, i.e. **the four lanes with equal +`laneid&3` read the same address, so one instruction covers one 16-byte word and +32 lanes cover a 512-byte span**. A 4-load group with `step 16` therefore +covers 64 bytes = 32 f16 = one f16 per column of an `N=32` GEMM's C operand, +replicated over the 16 rows of a tile. + +### 1.2 Constants and helpers + +| register | first definition | f32/f64 literal | f16 value used | +|---|---|---|---| +| `%fd770` | s5030 L8337 `mov.f64 %fd770, 0d3F20000000000000` | 2⁻¹³ | `0x0800` = 0.0001220703125 | +| `%f1469` | s15420 L36585 `mov.f32 %f1469, 0f3ED306EB` | 0.4121621549129486 | `0x3698` = 0.412109375 | +| `%f1470` | s15423 L36592 `mov.f32 %f1470, 0f3DA60DD6` | 0.0810810774564743 | `0x2D30` = 0.0810546875 | +| `%f1471` | s15426 L36599 `mov.f32 %f1471, 0f3F000000` | 0.5 | `0x3800` | +| `%f1472` | s15429 L36606 `mov.f32 %f1472, 0f40000000` | 2.0 | `0x4000` | +| `%f1520` | s18515 L46581 `mov.f32 %f1520, 0f3F800000` | 1.0 | `0x3C00` (E19) | +| `%f1526` | s18517 L46583 `mov.f32 %f1526, 0fC0000000` | −2.0 | `0xC000` (E19) | + +`%f1469…%f1472` are materialised **inside E12** (s15420–s15431) and re-used by +E14, E16 and E18, which contain no `mov.f32` of their own. + +* `mov.u32 %r13609, 0` (L6552) is the constant-zero C operand used by every mma + whose `C` field is `{%r13609, %r13609}` (phases 2, 3, 7, 8, 11 …); the same + register is later re-read as a zero f16 by E19 (§3/E19). +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — the *inverse* direction, used only by E1 to + dequantise the skip input (96 occurrences, s4386–s4481). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32`, `abs.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (each step rounded through f16). + +## 2. Phase table, geometry and weight image + +### 2.1 The phase table + +`rr_layer_spec.py dec0` prints 19 phases: + +| # | stmt range | tool M | tool N | tool K | mma | grid | weight bytes | bias bytes | epi | +|---|---|---|---|---|---|---|---|---|---| +| 1 | s326–s421 | 96 | 256 | 64 | 96 | band | 0..7692 | 8192..8432 | 5515 | +| 2 | s5937–s5960 | 96 | 32 | 32 | 24 | full | 8512..9036 | – | 7 | +| 3 | s5968–s5991 | 96 | 32 | 32 | 24 | full | 9536..10060 | – | 171 | +| 4 | s6163–s6210 | 64 | 96 | 32 | 48 | full | *(none)* | 10560..22348 | 3843 | +| 5 | s10054–s10101 | 192 | 96 | 96 | 48 | band | *(none)* | – | 160 | +| 6 | s10262–s10277 | 64 | 32 | 32 | 16 | full | 22848..23372 | – | 7 | +| 7 | s10285–s10308 | 96 | 32 | 32 | 24 | full | 23872..24396 | – | 7 | +| 8 | s10316–s10339 | 96 | 32 | 32 | 24 | full | 24896..25420 | – | 171 | +| 9 | s10511–s10558 | 64 | 96 | 32 | 48 | full | *(none)* | 25920..37708 | 3838 | +| 10 | s14397–s14444 | 192 | 96 | 96 | 48 | band | *(none)* | – | 55 | +| 11 | s14500–s14515 | 64 | 32 | 32 | 16 | full | 38208..38732 | – | 887 | +| 12 | s15403–s15418 | 64 | 32 | 32 | 16 | full | 39360..39884 | 40384..40432 | 709 | +| 13 | s16128–s16143 | 64 | 32 | 32 | 16 | full | 40448..40972 | – | 64 | +| 14 | s16208–s16223 | 64 | 32 | 32 | 16 | full | 41536..42060 | 42560..42608 | 600 | +| 15 | s16824–s16839 | 64 | 32 | 32 | 16 | full | 42624..43148 | – | 64 | +| 16 | s16904–s16919 | 64 | 32 | 32 | 16 | full | 43648..44172 | 44672..44720 | 600 | +| 17 | s17520–s17535 | 64 | 32 | 32 | 16 | full | 44736..45260 | – | 64 | +| 18 | s17600–s17615 | 64 | 32 | 32 | 16 | full | 45760..46284 | 46784..46832 | 600 | +| 19 | s18216–s18231 | 64 | 32 | 32 | 16 | full | 46848..47372 | – | 929 | + +### 2.2 The M/N/K arithmetic (`M/16 · N/8 · K/32 == mma`) + +Ranks hold for **15 of the 19 phases**. The four failures are the banded +phases; in each the tool's `M` overcounts because A and B fragments are +reused across k-steps, and in two of them `K` is also wrong. + +* **Phase 1 — 48×128 with K=64, not 96×256.** + The phase has 96 mma, 6 distinct A quads and 32 distinct B pairs, but the + chains (`chains_of`, s326–s421) are **48 chains of length 2**. Each chain + uses one A quad and one B pair per k-step: + `s326 A=%r756 B=%r399@0 → s328 A=%r776 B=%r403@512`, + `s330 A=%r756 B=%r407@1024 → s332 A=%r776 B=%r411@1536`, … So the 6 A quads + are 3 m-tiles × 2 k-slices and the 32 B pairs are 16 n-tiles × 2 k-slices: + `M = 48`, `N = 128`, `K = 64`, and `3·16·2 = 96`. mma count over 6·32 = 192 + A×B pairs would be 384 if the tool's M/N were taken literally; only the + 48-chain reading reproduces 96. +* **Phase 5 and phase 10 — 64×32 with K=96, not 192×96.** + Each has 48 mma in 16 chains of length 3. Chains 0…3 share the A triple + `{%r8639, %r8659, %r8679}` (phase 5) and take four different B triples; + chains 4…7 use a second A triple, etc. So the 12 A quads are 4 m-tiles × 3 + k-slices and the 12 B pairs are 4 n-tiles × 3 k-slices: + `M = 64`, `N = 32`, `K = 96`, and `4·4·3 = 48`. (This is the + `(64×96)·(96×32)` banded attention product.) +* **Phase 1's tool `N=256`** comes from counting the 32 B pairs as 8 columns + each; the 16 real n-tiles are the 16 × 1024-byte-strided groups seen at + `s274…s304` (`W+0, +512, …, +7680`, i.e. 16 loads × 2 fragments). + +So the phase-table `M`/`N`/`K` columns overcount the four banded phases by the +k-slice factor; the corrected shapes are the ones a native replacement must +produce. + +### 2.3 Weight image extent + +The prepared weight image is **47376 bytes**. The largest byte actually loaded +is `W+47372` (`ld.weak.global.ca.v4.u32` at s18167, L46043) and 47372+4 = 47376; +no load reads past it. The B-operand offsets resolved from the mma alone span +`W+0 … W+47372` (176 distinct B word offsets, 224 distinct C word offsets). + +Unlike enc5, **every** weight load in this entry is issued from the plain +`W + 16*laneid + off` base: each load block builds `add.s64 %rdX, %rd2, +%rdY` with `%rdY = mul.wide.u32(%laneid, 16)` and then adds the offset +(s5931…s5934, L10447…L10451, for phase 2's B; s5993…s5996, L10809…L10813, for +phase 4's C; s10340…s10344, L22901…L22907, for phase 9's C; s12036…s12038 for +E12's B). There is no `%tid.z` term and therefore no per-group interleaving of +the byte offsets. + +### 2.4 Phases that read no weight operand + +Every `B` operand of every phase resolves to the weight image **except four**: + +* **phase 4** — its B registers `%r8933…%r9043` are written by the + `cvt.rn.satfinite`/`mov.b32` packs of E3 (s6043 L10908 onwards); the + phase-table B column is `?`. +* **phase 5** — its B registers are E4's `movmatrix`/pack output (`?` in the + table), i.e. the transposed V. +* **phase 9** — like phase 4: its B comes from E8's packs (s10391 L23002). +* **phase 10** — like phase 5: its B comes from E9's `movmatrix`/pack output. + +Phases 4 and 9 read their *C* operand from the weight image (the 12288-byte +score biases at `W+10560…W+22348` and `W+25920…W+37708`, loaded in E3 and E8); +phases 5 and 10 use the constant-zero C `%r13609` (L6552). + +## 3. The epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s422–s5936 | 5515 | pack phase 1's D, stage a 10×10 window in shared, read the skip input, RMS norm, pack | +| E2 | s5961–s5967 | 7 | next-B weight loads | +| E3 | s5992–s6162 | 171 | 24 B-fragment loads (phase 4's C bias) + pack phase 3's D | +| E4 | s6211–s10053 | 3843 | softmax of the 64×96 score block, V-transpose, pack | +| E5 | s10102–s10261 | 160 | residual + per-column table, pack, next B | +| E6 | s10278–s10284 | 7 | next-B weight loads | +| E7 | s10309–s10315 | 7 | next-B weight loads | +| E8 | s10340–s10510 | 171 | 24 B-fragment loads (phase 9's C bias) + pack phase 8's D | +| E9 | s10559–s14396 | 3838 | softmax (second window, same code as E4) | +| E10 | s14445–s14499 | 55 | next-B loads + pack phase 10's D | +| E11 | s14516–s15402 | 887 | RMS norm (², sum, rsqrt, gain) + packs + next B/C | +| E12 | s15419–s16127 | 709 | clamped cubic activation + column table + pack | +| E13 | s16144–s16207 | 64 | next B/C loads + pack | +| E14 | s16224–s16823 | 600 | clamped cubic activation + pack | +| E15 | s16840–s16903 | 64 | next B/C loads + pack | +| E16 | s16920–s17519 | 600 | clamped cubic activation + pack | +| E17 | s17536–s17599 | 64 | next B/C loads + pack | +| E18 | s17616–s18215 | 600 | clamped cubic activation + pack | +| E19 | s18232–s19160 | 929 | final epilogue: row max, softmax, texture gather, softmax, surface writes | + +--- + +### E1 — s422–s5936: pack, shared window staging, skip input, RMS norm + +5515 statements — the largest epilogue, and the only one with control flow per +element group (339 `$label`s, 278 `bra.uni`, 159 `bra`). Op order: + +| range | op | +|---|---| +| s422–s600 | 80 `cvt.rn.satfinite.e4m3x2.f16x2` + 37 `mov.b32` → 40 b32 of phase 1's D | +| s540–s765 | address arithmetic; 37 `st.shared.u32` + 3 `st.shared.v2.u16` into `smem` | +| s771–s800 | guard predicates for the staging | +| s805–s1457 | 24 `ld.shared.v2.u16` read the staged patch back | +| s1459 | `ld.param.u64 %rd114, [%rd1+-56]` = `param_0+24` (the skip input) | +| s1613–s4308 | 21 `ld.global.v2.u16` from `%rd4` (= `param_0+24`) | +| s4357–s4384 | 3 more `ld.global.v2.u16` from the same pointer | +| s4386–s4481 | 96 `cvt.rn.f16x2.e4m3x2` (dequantise the skip values) | +| s4484–s5174 | 204 `add.f16` (pairwise residual adds) | +| s4674–s5856 | 288 `mul.f16` (squares and gain multiplies) | +| s4818–s5027 | 60 `add.f16x2` (in-lane sums) | +| s4849–s5026 | 24 `shfl.sync.bfly.b32` | +| s5030–s5031 | `mov.f64 %fd770, 0d3F20000000000000` + `cvt.rn.f16.f64` — `2⁻¹³` | +| s5178–s5559 | 96 `cvt.f32.f16` + 96 `rsqrt.approx.ftz.f32` + 96 `cvt.rn.f16.f32` | +| s5563–s5569 | `W + ((laneid<<2)&12)` + 4 `ld.global.v2.u16` at `W+8448…8496` | +| s5860–s5928 | 48 `cvt.rn.satfinite` packs (+ 44 `mov.b32`) of the normalised values | +| s5934–s5936 | 2 `ld.weak.global.ca.v4.u32` at `W+8512`, `W+9024` → phase 2's B | + +Evidence: + +``` +s564 L2369: st.shared.v2.u16 [%r48+-176], {%rs139, %rs140} +s588 L2395: st.shared.u32 [%r53], %r5 +s1459 L3450: ld.param.u64 %rd114, [%rd1+-56] +s1613 L3615: ld.global.v2.u16 {%rs287, %rs288}, [%rd116] +s4386 L6554: cvt.rn.f16x2.e4m3x2 %r4074, %rs287 +s4484 L6844: {add.f16 %rs425,%rs426,%rs427;} +s4674 L7322: {mul.f16 %rs716,%rs428,%rs428;} // square +s4849 L7865: shfl.sync.bfly.b32 %r4247,%r4243,%r14056,%r4250,%r14067 +s5030 L8337: mov.f64 %fd770, 0d3F20000000000000 +s5180 L8783: rsqrt.approx.ftz.f32 fl, fl +s5566 L9408: ld.global.v2.u16 {%rs6669, %rs6670}, [%rd241+8464] +s5860 L10282: mov.b32 %r9539, {%rs1902, %rs1903} +s5934 L10451: ld.weak.global.ca.v4.u32 { %r4647,%r4648,%r4649,%r4650},[%rd157] +``` + +**What it computes.** + +1. **Requantise phase 1's D** and stage it into `smem` as a 10×10 grid of + `f16x2` pairs (the stores step by ±16, ±160, ±1600) — a padded window patch. +2. **Read it back** as a shifted 24-load window (s805–s1457) — the receptive + field of the next phase. +3. **Read the skip input** at `param_0+24`, `ld.global.v2.u16` pairs, and + dequantise it with `cvt.rn.f16x2.e4m3x2` (E1 is the only epilogue that uses + that op). +4. **Add** the two (204 `add.f16`) — the values live on: the sums `%rs425` / + `%rs428` defined at s4484/s4485 are still read in **E5** (s10118, L22027) and in + E19. +5. **RMS norm**, exactly as enc0's E12: sum of squares (`mul.f16`), in-lane + `add.f16x2` trees, `shfl.sync.bfly` across lanes, `+ 2⁻¹³`, `rsqrt`, multiply + by the per-column gain read from `W+8448…8496` (4 × `v2.u16` = 8 f16 per + lane = 32 columns). There is **no mean subtraction and no `1/N`**. +6. **Repack** the normalised values (48 packs, s5860–s5928) as phases 2 and 3's + A operands, and load phase 2's B (`W+8512`, `W+9024`). + +**Outputs:** phases 2/3's A and phase 2's B. **Memory:** 24 global skip loads, +24 shared loads, 4 gain loads, 40 shared stores, 2 weight loads. + +--- + +### E2 — s5961–s5967: next-B weight loads + +``` +s5961 L10626: mov.u32 %r4895, %laneid +s5963 L10629: add.s64 %rd245, %rd2, %rd244 +s5964 L10630: add.s64 %rd159, %rd245, 9536 +s5965 L10632: ld.weak.global.ca.v4.u32 { %r4896,…},[%rd159] // +9536 +s5966 L10634: add.s64 %rd160, %rd245, 10048 +s5967 L10636: ld.weak.global.ca.v4.u32 { %r4900,…},[%rd160] // +10048 +``` + +Two 16-byte/lane fragments of `W + 16*laneid + {9536, 10048}` = phase 3's B +(weight block `[9536, 10060)` per the phase table). Nothing else. + +--- + +### E3 — s5992–s6162: phase 4's C-seed loads + pack of phase 3's D + +171 statements, 24 weight loads + 80 packs (identical shape to enc5's E10 and +enc0's E9): + +``` +s5996 L10813: ld.weak.global.ca.v4.u32 { %r5145,…},[%rd161] // +10560 + … +s6042 L10905: ld.weak.global.ca.v4.u32 { %r5237,…},[%rd184] // +22336 +s6043 L10908: cvt.rn.satfinite.e4m3x2.f16x2 %rs1951, %r4675 +``` + +* **24 loads** at `W + 16*laneid + 10560 + 512*i`, `i = 0…23` — phase 4's + score-bias C seeds, byte block `[10560, 22348)` = 12288 bytes = 6144 f16, + tile index `4*(n>>1) + m`, stride 512. +* **80 packs / 40 b32** (s6043–s6162) whose sources are phase 3's D registers + (`%r4655`, `%r4675`, …) → phase 4's A and B operands. + +**Memory:** 24 weight loads, nothing else. + +--- + +### E4 — s6211–s10053: softmax of the 64×96 score block + +**Phase 4** = 48 `mma` (s6163–s6210), D registers 96 f16x2 (64 rows × 96 +columns). The epilogue is byte-for-byte the same code as enc0's E5 and +enc5's E11. Sub-sections: + +| range | stmts | what | +|---|---|---| +| s6211–s8328 | 2118 | 96 per-element groups: scale, clamp, cubic, exponent extract | +| s8329–s8412 | 84 | in-lane partial row-sum trees | +| s8413–s8539 | 127 | 16 `shfl.sync.bfly` → 8 row sums (`s8415 L18394` … `s8536 L18698`) | +| s8543–s9308 | 766 | 192 `rcp.approx.ftz.f32` → 96 reciprocals (`s8545 L18720`) | +| s9312–s9788 | 477 | 192 `mul.f16` → 96 probabilities (`s9312 L19965`) | +| s9790–s9837 | 48 | `movmatrix.sync.trans.aligned.m8n8.b16` (`s9790 L21019`) | +| s9838–s10052 | 215 | 144 packs (`s9838 L21163`) | + +#### (a) per-element exponent, s6211–s8328 + +``` +s6212 L11526: mov.f32 %f?, 0f3C8CCB50 +s6215 L11534: mul.f16x2 %r?, %r?, %r? +s6220 L11548: max.f16x2 %r?,%r?,%r? +s6225 L11562: min.f16x2 %r?,%r?,%r? +s6231 L11580: fma.rn.f16x2 %r?,%r?,%r?,%r? +s6237 L11597: shl.b32 %r?, %r?, 5 +s6238 L11598: and.b32 %r?, %r?, 2145419232 // 0x7FE07FE0 +``` + +Per f16 half `x`: + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +u = f16(1.375 + m*(0.92724609375 - m*m)) +expval = f16 from bits ((u_bits << 5) & 0x7FE07FE0) // 2^(32·frac(u) − 47) +``` + +The same cubic-exponent trick as enc5's E11 and enc0's E5; **not `exp`**. The +clamp bounds are the guard (`d/dm[0.92724609375m − m³]` vanishes at +`m = 0.55615…`). + +#### (b) in-lane partial sums, s8329–s8412 + +`add.f16x2` trees reduce each lane's 96 `expval` values to 24 partial sums in +12 f16x2 registers. + +#### (c) cross-lane row sums, s8413–s8539 + +``` +s8415 L18394: shfl.sync.bfly.b32 %r?,%r?,1,%r?,-1 +s8424 L18418: add.f16 %rs?,%rs?,%rs? +``` + +Eight times: add the two f16x2 partials, butterfly over lane bits 0 and 1, add +the halves, broadcast. **8 row sums**, one per row `g, g+8` of the four +m-tiles. **There is no row maximum in this epilogue**; `max.f16x2`/`min.f16x2` +(96 each) are the clamp of (a). + +#### (d)–(g) + +192 `rcp.approx.ftz.f32` → 96 reciprocals; 192 `mul.f16` → 96 probabilities +`p = expval/rowsum`; 48 `movmatrix` transpose phase 3's D (the V matrix); 144 +packs → phase 5's A and B. **Inputs:** phase 4's 96 D, phase 3's 48 D. +**Outputs:** phase 5's operands. **Memory:** none. + +--- + +### E5 — s10102–s10261: residual + per-column table, then pack + +160 statements. This is the twin of enc0's E6. + +``` +s10106 L22009: ld.weak.global.ca.v4.u32 { %r9048,…},[%rd185] // +22848 +s10108 L22013: ld.weak.global.ca.v4.u32 { %r9052,…},[%rd186] // +23360 +s10114 L22022: ld.global.v2.u16 {%rs6677, %rs6678}, [%rd252+39248] +s10115 L22023: ld.global.v2.u16 {%rs6679, %rs6680}, [%rd252+39264] +s10116 L22024: ld.global.v2.u16 {%rs6681, %rs6682}, [%rd252+39280] +s10117 L22025: ld.global.v2.u16 {%rs6683, %rs6684}, [%rd252+39232] +s10118 L22027: add.f16 %rs3545,%rs6684,%rs428 +s10214 L22315: cvt.rn.satfinite.e4m3x2.f16x2 %rs?, %r? +``` + +1. **Next-B loads** (s10106–s10108): two `v4.u32` fragments from + `W + 16*laneid + {22848, 23360}` → phase 6's B. +2. **Table loads** (s10110–s10117): four `ld.global.v2.u16` from + `W + ((laneid<<2)&12) + {39232, 39248, 39264, 39280}` → 8 f16 = 32 columns. +3. **Residual + table add** (s10118–s10212): 64 `add.f16`, i.e. 32 f16x2, each + `table[2t{,+1}] + %rs425/%rs428`. `%rs425`/`%rs428` are the skip-input sums + **defined in E1** (s4484/s4485, L6844/L6848); they have no other + definition in the entry (`grep -n "%rs428\b"` returns lines 6848, 7322, + 9845, 22027). The 32 resulting registers are **phase 6's C operand**, so + phase 6 computes `D6 = A6·B6 + (skip + column_table)`. +4. **Pack** (s10214–s10261): 32 packs of phase 5's D (the banded P·V output) + → 16 b32 = phase 6's A. + +**Memory:** 2 weight loads + 4 table reads. + +--- + +### E6 / E7 — s10278–s10284 and s10309–s10315: next-B weight loads + +Two 7-statement runs, each two `ld.weak.global.ca.v4.u32`: + +* E6: `W + 16*laneid + {23872, 24384}` (s10282 L22545, s10284 L22549) → + phase 7's B (weight block `[23872, 24396)`). +* E7: `W + 16*laneid + {24896, 25408}` (s10313 L22726, s10315 L22730) → + phase 8's B (`[24896, 25420)`). + +--- + +### E8 — s10340–s10510: phase 9's C-seed loads + pack of phase 8's D + +Identical to E3 with the second window's offsets: 24 loads at +`W + 16*laneid + 25920 + 512*i` (s10344 L22907 … s10390 L22999) = the byte +block `[25920, 37708)`, and 80 packs of phase 8's D (s10391 L23002 onward) → +phase 9's operands. + +--- + +### E9 — s10559–s14396: softmax, second window + +**Identical code to E4** with shifted registers; the op histogram is the same +(1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 `cvt.rn.f16.f64`, 192 each +`fma.rn.f16x2` / `cvt.f32.f16` / `rcp.approx.ftz.f32` / `mul.f16`, 144 packs, +48 `movmatrix`). Sub-section boundaries: exponent groups s10559–s12671, in-lane +sums s12672–s12755, 16 `shfl.sync.bfly` s12756–s12885, 192 `rcp.approx` +s12886–s13653, 192 `mul.f16` s13655–s14131, 48 `movmatrix` s14133–s14180, 144 +packs s14181–s14395. + +**Inputs:** phase 9's 96 D, phase 8's 48 D. **Outputs:** phase 10's operands. +**Memory:** none. + +#### Shape of the attention region (E1–E11) + +``` +P1 A = input buffer (param+8) B = W+0 C = bias@8192 → D1 (48×128, K=64) + E1 packs D1 into smem, dequantises the skip (param+24), RMS-norms, packs +P2 A = E1's normed tile B = W+8512 C = 0 → D2 (96×32) +P3 A = E1's normed tile B = W+9536 C = 0 → D3 + E3 packs D3 → P4 A, loads P4 C = bias@10560 (12288 B) +P4 A = pack(D3) B = pack(D2) C = bias@10560 → scores 64×96 + E4: softmax over the 96 columns (no row max), 48 movmatrix(D2), packs → P5 +P5 A = pack(P) B = pack(transpose(D2)) C = 0 → D5 (64×32, K=96) + E5: pack → P6 A; P6 C = skip(E1) + column table@39232; loads P6 B +P6 A = pack(D5) B = W+22848 C = skip+table → D6 (64×32) +P7 A = E1's normed tile B = W+23872 C = 0 → D7 (96×32) +P8 A = E1's normed tile B = W+24896 C = 0 → D8 + E8 packs D8 → P9 A, loads P9 C = bias@25920 (12288 B) +P9 A = pack(D8) B = pack(D7) C = bias@25920 → scores 64×96 + E9: same softmax + transpose(D7) + packs → P10 +P10 A = pack(P') B = pack(transpose(D7)) C = 0 → D10 (64×32, K=96) + E10 packs D10 → P11 A +P11 A = pack(D10) B = W+38208 C = D6 (residual) → D11 (64×32) +``` + +Window 2 therefore mirrors window 1 except that P9's two operands both come out +of P8 (E8), while the transpose of P7 supplies P10 (E9). + +--- + +### E10 — s14445–s14499: next-B loads + pack + +``` +s14449 L34098: ld.weak.global.ca.v4.u32 { %r13651,…},[%rd215] // +38208 +s14451 L34102: ld.weak.global.ca.v4.u32 { %r13655,…},[%rd216] // +38720 +s14452 L34105: cvt.rn.satfinite.e4m3x2.f16x2 %rs5359, %r13270 +``` + +* two weight fragments at `W + 16*laneid + {38208, 38720}` → phase 11's B; +* **32 packs** of phase 10's D (s14452–s14498) → 16 b32 = phase 11's A. + +**Unlike E5, no table**: phase 11's C is phase 6's D (`%r9097,%r9098` etc. — +`rr_layer_spec.py`'s C-in list for the cut contains `%r13609`-style pairs and +the residual D6), so phase 11 computes `D11 = A11·B11 + D6`. + +--- + +### E11 — s14516–s15402: RMS norm before the MLP + +887 statements, no stores. Structure: + +| range | op | +|---|---| +| s14516–s14643 | 192 `mul.f16` (squares of phase 11's D; first `s14517 L34330`) | +| s14644–s14659 | 16 `add.f16x2` (in-lane pairs) | +| s14660–s14783 | 16 `shfl.sync.bfly.b32` (`s14666 L34727` … `s14780`) + `add.f16` | +| s14784 | `cvt.rn.f16.f64` of `%fd770` = `2⁻¹³` | +| s14881–s15136 | 64 `cvt.f32.f16` + 64 `rsqrt.approx.ftz.f32` (`s14885 L35337`) + 64 `cvt.rn.f16.f32` | +| s15140–s15146 | gain loads `W + ((laneid<<2)&12) + {39296, 39312, 39328, 39344}` | +| s15147–s15337 | 192 `mul.f16` (`inv · gain` then `x · (inv·gain)`) | +| s15340–s15345 | next-B loads `W + 16*laneid + {39360, 39872}` | +| s15346–s15354 | next-C loads `W + ((laneid<<2)&12) + {40384, 40400, 40416, 40432}` | +| s15355–s15401 | 32 packs → phase 12's A | + +Evidence: + +``` +s14517 L34330: mul.f16 %rs5393,%rs6220,%rs6220 +s14666 L34727: shfl.sync.bfly.b32 %r13904,%r13900,%r14056,%r13907,%r14067 +s14885 L35337: rsqrt.approx.ftz.f32 fl, fl +s15143 L35754: ld.global.v2.u16 {%rs6685, %rs6686}, [%rd263+39312] +s15355 L36359: cvt.rn.satfinite.e4m3x2.f16x2 %rs6184, %r18145 +``` + +**What it computes.** For each row a lane holds: + +``` +sumsq[row] = Σ_c x[row,c]² (f16, butterfly over 4 lanes) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2⁻¹³))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` + +with **no mean subtraction and no `1/N`**; `gain[c]` is read per column from +the 64-byte table at `W+39296…39344`. The norm's bias is not added here — it is +phase 12's C operand, loaded at the end of this epilogue (`+40384…+40432`). + +**Outputs:** phase 12's B (`%r14138…`) and C (`%r14308 %r14318 %r14328 +%r14338`), 16 packed A registers, and the 32 f16x2 normalised values that E13, +E15 and E17 repack. + +--- + +### E12 — s15419–s16127: clamped cubic activation + column table + pack + +709 statements. Histogram: 128 `cvt.rn.f16.f32`, 176 `mov.b32`, 32 each +`neg/max/min/abs.f16x2`, 96 `mul.f16x2`, 32 `sub.f16x2`, 32 `add.f16x2`, +2 `ld.weak`, 4 `ld.global.v2.u16`, 64 `add.f16`, 32 packs. + +``` +s15420 L36585: mov.f32 %f?, 0f3ED306EB +s15432 L36614: neg.f16x2 %r?,%r? +s15433 L36618: max.f16x2 %r?,%r?,%r? +s15434 L36622: min.f16x2 %r?,%r?,%r? +s15435 L36626: abs.f16x2 %r?,%r? +s15436 L36630: mul.f16x2 %r?,%r?,%r? +s15437 L36634: sub.f16x2 %r?,%r?,%r? +s15439 L36642: add.f16x2 %r?,%r?,%r? +s15972 L38516: ld.weak.global.ca.v4.u32 { %r15269,…},[%rd219] // +40448 +s15974 L38520: ld.weak.global.ca.v4.u32 { %r15273,…},[%rd220] // +40960 +s15980 L38529: ld.global.v2.u16 {%rs6693, %rs6694}, [%rd273+41488] + … +41504, +41520, +41472 +s15984 L38534: add.f16 %rs?,%rs?,%rs? +s16080 L38822: cvt.rn.satfinite.e4m3x2.f16x2 %rs?, %r? +``` + +Per element, over each of the 32 f16x2 D registers of phase 12: + +``` +y = clamp(x, -2, +2) +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a *cubic ramp*, not a sigmoid: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`; `g(1) = 0.831055` where +`x·sigmoid(x) = 0.730957`. **Reproduce the formula, not SiLU/GELU.** + +Then: 4 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {41472, 41488, 41504, +41520}` (64 bytes, 32 columns), 64 `add.f16` = `table[column] + D12` (written +over the activation inputs, s15984 L38534), 32 packs of the **activation +outputs** → phase 13's A, and 2 weight loads at `W+40448/+40960` → phase 13's B. + +**Outputs:** phase 13's A, B and C seeds. + +--- + +### E13 / E15 / E17 — 64 statements each: next B/C loads + pack + +Three identical runs: + +| run | range | B loads | C loads (4 × `ld.global.u32`) | +|---|---|---|---| +| E13 | s16144–s16207 | `+40448`, `+40960` (s16148 L39052, s16150 L39056) | `+42560/42576/42592/42608` (s16156 L39065 …) | +| E15 | s16840–s16903 | `+42624`, `+43136` (s16844 L41460, s16846 L41464) | `+44672/44688/44704/44720` (s16852 L41473 …) | +| E17 | s17536–s17599 | `+44736`, `+45248` (s17540 L43868, s17542 L43872) | `+46784/46800/46816/46832` (s17548 L43881 …) | + +Each loads the next phase's B and C and then **32 packs of the normalised tile +that E11 produced** (the source register has its newest definition at +s15355–s15401), so phases 13, 15 and 17 all take the same A operand — three +parallel GEMMs off one normed tile. + +--- + +### E14 / E16 / E18 — 600 statements each: clamped cubic activation + pack + +Three identical runs (E14 s16224–s16823, E16 s16920–s17519, E18 +s17616–s18215), histogram in each: 128 `cvt.rn.f16.f32`, 144 `mov.b32`, 32 each +`neg/max/min/abs.f16x2`, 96 `mul.f16x2`, 32 `sub.f16x2`, 32 `add.f16x2`, +2 `ld.weak`, 32 packs — and **no `ld.global` and no table add**. + +``` +s16225 L39298: cvt.rn.f16.f32 low, %f… +s16233 L39321: neg.f16x2 %r?,%r? +s16234 L39325: max.f16x2 %r?,%r?,%r? // phase 14's D +s16770 L41219: mul.wide.u32 … +s16773 L41223: ld.weak.global.ca.v4.u32 {…},[%rd223] // +42624 (phase 15's B) +s16776 L41230: cvt.rn.satfinite.e4m3x2.f16x2 %rs?, %r? +``` + +Same clamped cubic as E12, applied to the phase's own D; the 32 packs are the +activation outputs → the next phase's A; the 2 weight loads are the next +phase's B. + +#### Shape of the whole MLP region (E11–E18) + +``` +E11 normed tile N (32 f16x2) + ├─ pack → phase 13 A (s15355) phase 13: A=N, B=W13, C=bias@40384 → activation (E12: +table@41472) + │ pack of activation → phase 14 A (s16080) + │ phase 14: C = D13 → D14 + ├─ pack → phase 15 A (s16160) phase 15: A=N, B=W15, C=bias@42560 → activation (E14) + │ pack of activation → phase 16 A (s16776) + │ phase 16: C = D15 → D16 + └─ pack → phase 17 A (s17552) phase 17: A=N, B=W17, C=bias@44672 → activation (E16) + pack of activation → phase 18 A (s18168) + phase 18: C = D17 → D18 (E18) +``` + +Only the *first* of the three branches (phase 13's) has a per-column table add +(E12, `W+41472…41520`); the other two activations are pure cubic + pack. The +three branches share one input tile and fold into a running residual +(`D14 = … + D13`, `D16 = … + D15`, `D18 = … + D17`). + +--- + +### E19 — s18232–s19160: the final epilogue + +929 statements; it consumes the cut's returned accumulators (`%r13609`, +`%r14067`, `%r19306`, `%r19316`, …, listed by `rr_layer_spec.py`). + +#### (a) cross-lane row max, s18232–s18474 + +``` +s18232 L46270: mov.u32 %r19498, %laneid +s18233 L46272: and.b32 %r19867, %r19498, 7 // row key = laneid & 7 +s18234 L46273: shr.u32 %r19868, %r19498, 3 // column group +s18236 L46275: setp.eq.s32 %p294, %r19869, 1 +s18237 L46276: selp.b32 %r19870, %r19307, %r19306, %p294 +s18253 L46292: bfi.b32 %r19883, %r19867, %r19882, 2, 3 +s18254 L46293: shfl.sync.idx.b32 %r19884|%p298, %r19872, %r19883, %r19524, %r14067 +s18268 L46307: selp.b32 %r19897, %r19888, %r19884, %p302 +``` + +Two identical blocks (rows `g` from the D pairs `{r19306,r19307}`, … and rows +`g+8` from `{r19346,r19347}`, …, s18353 L46393 onwards), each doing: + +1. a `selp` chain over `laneid&3` selects one of the four D pairs into + `%r19872/%r19875/%r19878/%r19881` (the four n-tiles of the row segment); +2. four `shfl.sync.idx.b32` with + `srcLane = (laneid&7) | ((((laneid>>3)+d)&3)<<2)` for `d = 0, 1, 2, -1`; +3. a `selp` chain over `laneid>>3` picks between the four shuffled values. + +Result: `%r368…%r371` (row `g`) and `%r372…%r375` (row `g+8`) hold the per-lane +row maximum over the 8 columns. The `max.f16x2` / `max.f16` chain at +s18605–s18611 then reduces them and `s18612 L46696 sub.f16x2 %r20095,%r368, +%r20109` subtracts the row max: **this is a real row max**, done with +`shfl.sync.idx`, unlike E4's. + +#### (b) bounds check, s18475–s18490 + +``` +s18483 L46524: ld.param.v2.u32 {%r20073, %r20074}, [%rd1+-80] // param_0+0 +s18484 L46525: setp.ge.u32 %p342, %r391, %r20073 // x >= ex +s18486 L46527: or.pred %p344, %p342, %p343 +s18490 L46531: @%p346 bra $L__BB1_367 +``` + +Out-of-range lanes jump to `$L__BB1_367` and skip (c)…(e). + +#### (c) surface 1 write (`param_0+48`), s18491–s18502 + +``` +s18493 L46535: ld.param.u64 %rd319, [%rd357+-32] +s18494 L46536: cvta.to.global.u64 %rd320, %rd319 +s18495 L46537: mad.lo.s32 %r20132, %r20073, %r392, %r391 +s18497 L46539: add.s64 %rd322, %rd320, %rd321 +s18498 L46541: cvt.rn.satfinite.e4m3x2.f16x2 %rs6704, %r378 +s18502 L46552: st.global.v4.u16 [%rd322], {%rs6701, %rs6702, %rs6703, %rs6704} +``` + +Four packs of `%r373/%r376/%r377/%r378` and one `st.global.v4.u16` at +`4*(ex*y + x)` bytes — the e4m3 surface. The same block repeats for the second +row group at s18835–s18847 (line 47192). + +#### (d) per-element `abs`/`ex2` evaluation, s18503–s18601 + +``` +s18504 L46556: cvt.f32.f16 %f1473, low +s18511 L46577: abs.ftz.f32 %f1521, %f1473 +s18512 L46578: mul.ftz.f32 %f1522, %f1521, 0f4038AA3B +s18513 L46579: ex2.approx.ftz.f32 %f1523, %f1522 +s18514 L46580: add.ftz.f32 %f1524, %f1523, 0f3F800000 +s18516 L46582: rcp.approx.ftz.f32 %f1525, %f1524 +s18518 L46584: fma.rn.ftz.f32 %f1527, %f1525, %f1526, %f1520 // f1526 = -2.0 +s18519 L46585: setp.ge.ftz.f32 %p347, %f1521, 0f41102CB4 +s18520 L46586: selp.f32 %f1528, 0f3F800000, %f1527, %p347 +s18526 L46592: mul.ftz.f32 %f1530, %f1473, %f1473 +s18529 L46595: fma.rn.ftz.f32 %f1533, %f1532, %f1530, %f1531 + … +s18599 L46665: fma.rn.ftz.f32 %f1582, %f1581, %f1476, %f1476 +s18600 L46666: setp.ge.ftz.f32 %p354, %f1569, 0f3F19999A +s18601 L46667: selp.f32 %f1480, %f1576, %f1582, %p354 +``` + +Per element `v`: a `1 - 2/(1+2^(|v|·log2e))` branch (with a hard `1.0` above +`0f41102CB4` = 9.0109…) and a polynomial branch (`fma` chain over `v²`) selected +by `|v| ≥ 0f3F19999A` = 0.6. + +#### (e) surface 2 write (`param_0+144`, `sust.p`), s18602–s18603 + +``` +s18602 L46668: ld.param.u64 %rd295, [%rd357+64] +s18603 L46670: sust.p.2d.v4.b32.zero [%rd295, {%r391,%r392}], {%f1477,%f1478,%f1479,%f1480} +``` + +Four f32 channels `%f1477…%f1480` written at integer coordinates `(x, y)`. +Repeated at s18947–s18948 (line 47310) for the second row group. + +#### (f) row softmax on the f16x2 values, s18605–s18679 + +``` +s18605 L46674: max.f16x2 %r20086,%r368,%r369 +s18609 L46687: max.f16 %rs6705,%rs6706,%rs6707 +s18612 L46696: sub.f16x2 %r20095,%r368,%r20109 +s18615 L46704: mul.ftz.f32 %f1583, %f1481, 0f3FB8AA3B +s18616 L46705: ex2.approx.ftz.f32 %f1483, %f1583 +s18672 L46824: div.approx.ftz.f32 %f1499, %f1520, %f1600 // 1/rowsum +s18675 L46831: mul.f16x2 %r20110,%r20111,%r20124 + … five f16x2 multiplies (s18675–s18679) +``` + +A real row max, `x − max`, `2^((x−max)·log2e)` in f32, an f32 row sum, +`div.approx.ftz.f32` with 1.0, then five `mul.f16x2` — the same softmax as +enc5's E61(c). + +#### (g) texture reads and surface 3 write, s18680–s19159 + +``` +s18696 L46872: ld.param.v2.f32 {%f1602, %f1603}, [%rd357+56] // param_0+136 +s18697 L46873: mul.ftz.f32 %f1606, %f1602, 0f3F000000 +s18698 L46874: fma.rn.ftz.f32 %f1500, %f1602, %f1601, %f1606 // x coord +s18702 L46878: ld.param.u64 %rd313, [%rd357+8] // param_0+88 +s18704 L46881: tex.base.2d.v4.f16.f32 {%rs6733,…}, [%rd297, {%f1500,%f1501}] +s18706 L46885: fma.rn.f16 %rs6737,%rs6733,%rs6747,%rs6730 + … +s18778 L47053: ld.param.u64 %rd315, [%rd357+16] // param_0+96 +s18779 L47055: tex.base.2d.v4.f16.s32 {%rs6877,%rs6878,%rs6879,%rs6880}, [%rd315, {%r391,%r392}] +s18780 L47057: ld.param.u64 %rd317, [%rd357+24] // param_0+104 +s18781 L47059: tex.base.2d.v4.f16.s32 {%rs6881,%rs6882,%rs6883,%rs6884}, [%rd317, {%r391,%r392}] +s18782 L47062: cvt.f32.f16 %f1518, %rs98 +s18783 L47065: mul.ftz.f32 %f1613, %f1518, 0fBFB8AA3B // -log2e +s18784 L47066: ex2.approx.ftz.f32 %f1614, %f1613 +s18785 L47067: add.ftz.f32 %f1615, %f1614, 0f3F800000 +s18786 L47068: div.approx.ftz.f32 %f1519, %f1520, %f1615 // 1/(1+2^(-v·log2e)) +s18789 L47078: sub.f16 %rs6888,%rs6887,%rs6886 +s18790 L47082: mul.f16 %rs6891,%rs6865,%rs6886 +s18791 L47086: fma.rn.f16 %rs7167,%rs6877,%rs6888,%rs6891 +s18796 L47106: set.nan.f16.f16 %rs6912,%rs6881,%rs6881 +s18797 L47109: setp.ne.s16 %p367, %rs6912, 0 +s18798 L47110: @%p367 bra $L__BB1_362 +s18799 L47113: add.f16 %rs7167,%rs7167,%rs6881 +s18811 L47144: shl.b32 %r20167, %r391, 3 +s18812 L47145: mov.u16 %rs6933, 0 +s18813 L47147: sust.b.2d.v4.b16.zero [%rd323, {%r20167,%r392}], {%rs7167,%rs7168,%rs7169,%rs6933} +``` + +**Eighteen** `tex.base.2d.v4.f16.f32` sample `param_0+88` at *floating-point* +coordinates derived from `param_0+136` (a `v2.f32` scale/origin, `x = 2*…·(n−1) ++ w/2` style, s18697–s18701), and two `tex.base.2d.v4.f16.s32` sample +`param_0+96` and `param_0+104` at the *integer* coordinates `(x, y)`. The +sampled values are folded into `%rs7167…%rs7169` with `fma.rn.f16`, a `NaN` +guard is applied (`set.nan.f16.f16` / `setp.ne.s16` — if the sampled value is +NaN the add is skipped, s18796–s18810), and the result is written by +**`sust.b.2d.v4.b16.zero [%rd323, {%r20167,%r392}], {%rs7167,%rs7168, +%rs7169, 0}`** where `%rd323` = `param_0+112` (s18604 L46672) — the fourth +channel is the constant `0`. The whole tail is repeated for the second row +group at s18838–s19158 (lines 47175–47787). + +**Inputs:** the returned accumulators, `param+0/+8/+24` (E1), `W`, `smem`, +`param+0/+48/+88/+96/+104/+112/+136/+144`. +**Outputs:** none (the kernel returns at s19160 L47791). + +## 4. The parameter block, and the surfaces + +`rr_layer_spec.py dec0` reports a **152-byte parameter block with 3 `ld.param` +over 3 distinct offsets `[8, 40, 80]`**; that count only covers the literal +`[param_0+N]` forms. The complete set of `ld.param` in the entry (22 +instructions) resolves, via `%rd1 = param_0+80` (s4) and `%rd357 = param_0+80` +(s18492), to: + +| offset | type | statements | what it supplies | +|---|---|---|---| +| +0 | `v2.u32` | s13 L1041, s18483 L46524 | `(ex, ey)`, the extents | +| +8 | `u64` | s29 L1057 | the **input buffer**, read by the 24 prologue `ld.global.u32` (s67 L1097 … s270 L1300) that form phase 1's A (24 loads = its 6 A quads × 4 registers); never read again | +| +24 | `u64` | s1459 L3450 | the **skip input** | +| +40 | `u64` | s11 L1039 | `W`, the weight image | +| +48 | `u64` | s18493 L46535, s18838 L47175 | **output e4m3 surface** (`st.global.v4.u16` at s18502 L46552 and s18847 L47192) | +| +80 | `v2.u16` | s5 L1033 | block origin `(%rs235, %rs236)` | +| +88 | `u64` | s18702 L46878, s19047 L47518 | **texture A**, the handle of the 18 `tex.base.2d.v4.f16.f32` (s18704 L46881 … s18774 L47039) | +| +96 | `u64` | s18778 L47053, s19123 L47693 | **texture B**, the handle of the first `tex.base.2d.v4.f16.s32` (s18779 L47055) | +| +104 | `u64` | s18780 L47057, s19125 L47697 | **texture C**, the handle of the second `tex.base.2d.v4.f16.s32` (s18781 L47059) | +| +112 | `u64` | s18604 L46672, s18949 L47312 | **surface A**, the `sust.b.2d.v4.b16.zero` descriptor (s18813 L47147, s19158) | +| +136 | `v2.f32` | s18696 L46872, s19041 L47512 | the texture coordinate scale/origin used to build the f32 coords (s18697–s18701) | +| +144 | `u64` | s18602 L46668, s18947 L47308 | **surface B**, the `sust.p.2d.v4.b32.zero` descriptor (s18603 L46670, s18948 L47310) | + +### 4.1 The two texture reads at `+96`/`+104` + +Both are `u64` texture handles, loaded once per row group, and both feed +`tex.base.2d.v4.f16.s32` **with integer coordinates** (`{%r391, %r392}`, the +tile's `x`/`y`): + +* `+96` → `%rd315` at s18778 L47053 → `tex.base.2d.v4.f16.s32 {%rs6877, %rs6878, + %rs6879, %rs6880}, [%rd315, {%r391,%r392}]` at **s18779 L47055** (and the + second row group at s19124). +* `+104` → `%rd317` at s18780 L47057 → `tex.base.2d.v4.f16.s32 {%rs6881, + %rs6882, %rs6883, %rs6884}, [%rd317, {%r391,%r392}]` at **s18781 L47059** + (second row group at s19126). + +Their results are consumed immediately: +`%rs6881…%rs6884` (from `+104`) are the second term of the `sub.f16 %rs6888, +%rs6887,%rs6886` / `add.f16 %rs7167,%rs7167,%rs6881` path (s18789–s18799), and +`%rs6883`/`%rs6884` are the third channel folded into `%rs7169`; `%rs6877…` +(from `+96`) are the weights of the `fma.rn.f16` at s18791–s18795. Both are +"sample the same pixel as the surfaceless input" reads, which is why they use +integer coordinates. + +### 4.2 The surface writes: `+112` and `+144` (there is no `+120` or `+128`) + +A grep of every `st.global` / `sust` in the entry returns exactly **six** +instructions: + +| statement | instruction | descriptor | offset | +|---|---|---|---| +| s18502 L46552 | `st.global.v4.u16 [%rd322], {%rs6701,%rs6702,%rs6703,%rs6704}` | `%rd322 = cvta(param_0+48) + 8*(ex*y+x)` | +48 | +| s18847 L47192 | `st.global.v4.u16 [%rd352], {%rs6934,%rs6935,%rs6936,%rs6937}` | same, second row group | +48 | +| s18603 L46670 | `sust.p.2d.v4.b32.zero [%rd295, {%r391,%r392}], {%f1477,%f1478,%f1479,%f1480}` | `%rd295 = param_0+144` | +144 | +| s18948 L47310 | `sust.p.2d.v4.b32.zero [%rd325, {%r395,%r396}], {%f1620,…}` | same, second row group | +144 | +| s18813 L47147 | `sust.b.2d.v4.b16.zero [%rd323, {%r20167,%r392}], {%rs7167,%rs7168,%rs7169,%rs6933}` | `%rd323 = param_0+112` | +112 | +| s19158 L47787 | `sust.b.2d.v4.b16.zero [%rd353, {%r20268,%r396}], {%rs7170,%rs7171,%rs7172,%rs7166}` | same, second row group | +112 | + +So there are **three surface writes per row group** — `st.global.v4.u16` to +`param_0+48`, `sust.p.2d.v4.b32.zero` to `param_0+144`, and +`sust.b.2d.v4.b16.zero` to `param_0+112` — consuming respectively the +requantised accumulators (s18498–s18501), the four `%f1477…%f1480` of §3/E19(d), +and the texture-fused `%rs7167…%rs7169`. **`param_0+120` and `param_0+128` are +not read anywhere in the entry** (`grep -n 'ld\.param'` returns offsets 0, 8, +24, 40, 48, 80, 88, 96, 104, 112, 136, 144 and nothing else), so the write set +is `{+48, +112, +144}`; see §6 U1. + +### 4.3 What the skip input at `+24` supplies + +`param_0+24` is loaded **once**, at s1459 L3450: +`ld.param.u64 %rd114, [%rd1+-56]` (`%rd1 = param_0+80` ⇒ `param_0+24`), then +`cvta.to.global.u64 %rd4, %rd114` (s1460 L3451). `%rd4` is the base of **24 +`ld.global.v2.u16`** loads, all at `[%rd4 + mul.wide(%rX, 4)]`: + +* s1613 L3615, s1761 L3772, s1911 L3931, s2058 L4087, s2208 L4246, s2355 L4402, + s2505 L4561, s2652 L4717, s2802 L4876, s2949 L5032, s3099 L5191, s3246 L5347, + s3396 L5506, s3543 L5662, s3693 L5821, s3840 L5977, s3960 L6104, s4078 L6229, + s4166 L6322, s4253 L6414, s4308 L6472 (21 loads), plus + s4357 L6524, s4380 L6547, s4384 L6551 (3 more). + +Each pair is dequantised by `cvt.rn.f16x2.e4m3x2` (96 of them, s4386 L6554 … +s4481) and added to the value read back from the staged shared window by the +204 `add.f16` at s4484 L6844 … s5174. So **the skip input at `+24` supplies a +per-position e4m3 feature vector that is added to the staged patch before the +RMS norm**; the sum `%rs425/%rs428` computed at s4484/s4485 (L6844/L6848) is then used + +* as the square summand in E1 (`mul.f16` at s4674, L7322), +* as the norm's multiplicand in E1 (`mul.f16` at s9845), +* and as **the residual seed of phase 6's C operand in E5** + (`add.f16 %rs3545,%rs6684,%rs428` at s10118 L22027; `grep -n "%rs428\b"` + finds only lines 6848, 7322, 9845, 22027, so there is no second definition). + +It is **not** read anywhere else — in particular the final epilogue (E19) never +mentions `param_0+24`. + +## 5. The plane arena + +There is no plane-arena *write* in this entry: `param_0+48` is read once +(s18493 L46535, s18838 L47175) and written by the two `st.global.v4.u16` of +§4.2. The only other global stores are the two `sust` pairs. So dec0 has no +per-launch table generated into an arena of the kind enc5 builds in its E60; +the six store instructions above are the entry's entire global-write traffic. + +## 6. Uncharacterised + +**U1. The parameter offsets `+120` and `+128`.** The brief's "three surface +writes at +112/+120/+128" does not match this corpus: the actual write +descriptors are `param_0+48`, `param_0+112` and `param_0+144` (§4.2), and no +instruction reads `param_0+120` or `param_0+128`. Either the brief's numbering +uses a different base (e.g. relative to `param_0+80 - 48`, under which `+48 → +96`, `+112 → 160`, `+144 → 192`, still not matching) or it describes a +different revision of the harness. *Missing:* the harness' parameter-struct +declaration, which would name the fields and settle the numbering. + +**U2. `param_0+32`, `+56`, `+96`, `+104`, `+120`, `+128` as *fields*.** No +`ld.param` in the entry reads offsets `+32`, `+56`, `+120` or `+128`; if the +struct declares them they are unused by this kernel. *Missing:* the struct +declaration. + +**U3. The identity of the two 12288-byte score biases** (`W+10560…22348` for +phase 4, `W+25920…37708` for phase 9) and of the per-column tables +(`W+8448…8496`, `W+39232…39280`, `W+39296…39344`, `W+41472…41520`, +`W+42560…42608`, `W+44672…44720`, `W+46784…46832`). Their arithmetic role is +established (§3), their names are not. *Missing:* the weight image's `_prep` +permutation or the model's parameter names. + +**U4. The long liveness of `%rs425`/`%rs428`.** These two registers are +defined once each, inside E1 (s4484 L6844 / s4485 L6848), and read in E1 +(s4674 L7322, s5714 L9845) **and in E5** (s10118 L22027) — i.e. the +values cross phases 2, 3 and 4 (and E4's 3843-statement softmax) live. The PTX +is unambiguous about this, but whether it is a deliberate "add the skip at the +end of the first residual" or a register-allocation accident cannot be decided +from the PTX. *Missing:* the high-level source. + +**U5. E19's two evaluation branches.** §3/E19(d) computes both a +`1 − 2/(1+2^(|v|·log2e))` form and a `fma` polynomial over `v²`, selected by +`|v| ≥ 0.6` (and, inside the first form, by `|v| ≥ 9.0109…`). The arithmetic is +exact (s18511–s18601); which model function it is (erf/exp-like tone mapper?) is +not determinable. *Missing:* the reference implementation. + +**U6. Phase 1's true output width.** Phase 1 is 48×128×64 (§2.2) but its D +registers are 96 (48 chains × 2), and E1 packs them 128 times. Why 128 packs +for 96 registers — the extra 32 are presumably the second half of a 64-wide +value built from the same D — could not be tied down within this analysis. +*Missing:* a full def-use map of E1's pack destinations. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| phase table with M/N/K checked; phase 1 is 48×128 with K=64 | §2.1, §2.2 | +| weight image extent | §2.3 (47376 bytes) | +| phases that read no weight operand | §2.4 (4, 5, 9, 10) | +| norm (RMS, no mean, `2⁻¹³`, per-column gain) | §3/E11, §3/E1 | +| attention (score, softmax, V-transpose, P·V) | §3/E3, E4, E5, E8, E9, E10 | +| activations (clamped cubic, not GELU) | §3/E12, E14, E16, E18 | +| merge / patch expand | no 8-lane merge (that device appears only in enc0's E20(c)); this layer's per-pixel gather is E1's shared window staging/readback plus E19's texture gather (§3/E1, §3/E19) | +| per-launch table in the plane arena | none in this entry (§5) | +| where the `+96`/`+104` texture reads are consumed | §4.1 | +| the surface writes | §4.2 (`+48`, `+112`, `+144`; no `+120`/`+128`) | +| what the `+24` skip input supplies | §4.3 | +| final epilogue | §3/E19 | diff --git a/kernels/rr/rrswin_dec1.hip b/kernels/rr/rrswin_dec1.hip new file mode 100644 index 0000000..180177e --- /dev/null +++ b/kernels/rr/rrswin_dec1.hip @@ -0,0 +1,336 @@ +// Native replacement for the Ray Reconstruction denoiser's third decoder, +// cuda_dldn_engine_swin_dec1_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: phase 1 (the 48x384 patch-expand GEMM, 144 mma) is implemented and +// bit-exact against the GPU oracle -- debug stage p1, 4,194,304 payload bytes +// over 64 blocks x 32 lanes x 288 registers, 0 differing bytes, identical md5 +// (ae431ae0baff). Stage a1 (the 52 staged input registers) is likewise +// 100.0000%. E1 and phases 2-26 are not implemented yet, so the eight +// accumulators the epilogue reads back are placeholders: the served frame is +// wrong (compare_launch_dump.py: 14 arguments compared, 4 differ -- arg[8] the +// feature plane E25 writes and arg[112] the output surface), and the layer +// costs 0.036 ms/frame instead of the translated 1-2 ms, because phase 1's +// accumulators are dead after the read-back. +// +// The next piece is E1 (s547-s7095): the 48 packed patch cells per lane into a +// 10x10x4 shared grid, the 3x3-ish gather from param_0+24, the per-column RMS +// norm (raw sum of squares + 2^-13, rsqrt.approx.ftz, gain at weight +25088) and +// the restage into phases 2-5's A operands. Its lane -> (sub-array, row, col) +// map is 438 basic blocks in the PTX and is *not* characterised in +// rrswin_dec1_epilogues.md (its U4), so it has to be lifted out of the index +// arithmetic rather than guessed. +// +// The mirror-cut splice is kernels/rr/swin_dec1_recipe.py: it keeps NVIDIA's +// texture prologue (which stages phase 1's A fragments and bias seeds) and its +// surface epilogue (the shared staging, the softmax, the three texture reads +// and the surface store), and replaces physical lines 1486-38472 -- the whole +// 26-phase mma region, 632 mma -- with one call into d4r_swin_dec1. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +// +// --------------------------------------------------------------------------- +// Launch: grid 81x47, block 32x1x2 (two waves per block, which is why the weight +// addressing carries a per-tid.z stride), parameter block 144 bytes. The PTX this +// file replaces is ~/.cache/d4r-rr-corpus/0022-PREPASS_ENTRYPOINT_NAME.ptx. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinDec1Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinDec1Params) == 144, "parameter block"); + +enum : int +{ + kExtents = 0, // ex, ey: two u32 (s14) + kInPlane = 8, // input feature plane arena, read by phase 1's A loads + kPatchGather = 24, // the skip input E1 gathers the 10x10 patch from + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kOutPlane = 48, // plane arena E25 scatters phase 25's output into +}; + +#define DEVF __attribute__((device)) static inline +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (the settled formula, VERIFIED on enc0's 1024 (n, k) pairs per tile: the +// 512-byte block is 32 lanes of 16 contiguous bytes, and 64*(n&7) + 16*((k>>1)&3) +// is exactly 16*laneid of the lane that owns the byte, so the remaining four terms +// are that byte's index inside the lane's slot). +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// One m16n8k32 e4m3 mma, f16 accumulate, done the way the hardware does it. +// +// The lane's four A registers hold, for each of its two rows (row g and row g+8), +// the eight e4m3 values of k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3) and of +// k + 8; the four lanes of the group hold the four disjoint eighths of the 32 k's, +// so two butterfly steps bring the other three in. The B operand is read from the +// weight image at waddr() for the lane's own two D columns (D register 0 is row g, +// columns 2t and 2t+1; register 1 is row g+8). Every e4m3 product is exact and 32 +// of them sum exactly in f32, so a plain f32 accumulation rounded to f16 once is +// what the translated mma computes. +// +// a[0..3] the A fragment as the mma reads it +// w the weight image +// base byte offset of the B tile's first 512-byte block +// n0 the mma's first output column (a multiple of 8) +// c0, c1 the C operand's two registers (row g, row g+8) +// t laneid & 3 +// d[0], d[1] the two D registers +DEVF void mma_tile(const uint32_t* a, const uint8_t* w, int base, int n0, + uint32_t c0, uint32_t c1, int t, uint32_t d[2]) +{ + float bv[2][32]; +#pragma unroll + for (int c = 0; c < 2; ++c) { + const int n = n0 + 2 * t + c; +#pragma unroll + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } +#pragma unroll + for (int row = 0; row < 2; ++row) { + float acc[2] = {0.0f, 0.0f}; +#pragma unroll + for (int reg = 0; reg < 2; ++reg) { + const uint32_t q = a[2 * reg + row]; + uint32_t p[4]; + p[0] = q; + p[1] = bfly1_bits(q); + p[2] = bfly2_bits(q); + p[3] = bfly1_bits(p[2]); +#pragma unroll + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); +#pragma unroll + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[0] += av * bv[0][k]; + acc[1] += av * bv[1][k]; + } + } + } + const uint32_t cpair = row ? c1 : c0; + d[row] = pair_of((half_t)(acc[0] + h2f(cpair)), + (half_t)(acc[1] + h2f(cpair >> 16))); + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_dec1_recipe.py's debug +// stages: with D4R_RRSWIN_DEBUG=a1 (or p1) the same splice stores that stage's +// registers into the param_0+8 feature-plane buffer at +46,000,000, which the +// entry has finished reading by then (the prologue's last read is s324, before +// the cut at line 1486), and the launch dump then holds the translated values +// for a block/lane. Built with -DD4R_RRSWIN_DEBUG_STAGE= +// (kernels/tex/build_tex.sh, D4R_TEX_CFLAGS) this body stores the same +// registers of its own stage n in the same order, so the two dumps compare byte +// for byte. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 81u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kInPlane); + // the oracle's slot, swin_dec1_recipe.py's debug_slot: 32 lanes x n x 4 bytes, + // at least 8192, rounded up to a power of two (the oracle's splice forms + // block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. The nine 16-row A fragments of the staged block input arrive in +// this order (the first mma's operand order, .f16.e4m3 fragments of four b32 +// each): +// f0 %r1084.. f1 %r1104.. f2 %r1124.. (m-group 0's three steps) +// f3 %r1564.. f4 %r1584.. f5 %r1604.. (m-group 1) +// f6 %r2044.. f7 %r2064.. f8 %r2084.. (m-group 2) +// then phase 1's sixteen bias seeds (%r1621 %r1631 ... %r2041 %r2051, read from +// W + 256*tid.z + 4*(laneid&3) + 24576..24816), the weight image and the parameter +// block. No other C register is passed: every other mma's C operand is another +// mma's D register, which this body computes itself. +// +// The ten values the epilogue reads out of the deleted region cross the cut +// through the shared array, not `call.uni`'s return parameters: ZLUDA lowers +// those to the function's LLVM return type, so there is no .param-space object +// and no pointer is formed. `scratch` is the base of the entry's 6400-byte +// .shared array, 40 bytes apart per lane. +extern "C" __attribute__((device)) void d4r_swin_dec1( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, + uint32_t a6, uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, + uint32_t a12, uint32_t a13, uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, + uint32_t a18, uint32_t a19, uint32_t a20, uint32_t a21, uint32_t a22, uint32_t a23, + uint32_t a24, uint32_t a25, uint32_t a26, uint32_t a27, uint32_t a28, uint32_t a29, + uint32_t a30, uint32_t a31, uint32_t a32, uint32_t a33, uint32_t a34, uint32_t a35, + uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3, uint32_t b4, uint32_t b5, + uint32_t b6, uint32_t b7, uint32_t b8, uint32_t b9, uint32_t b10, uint32_t b11, + uint32_t b12, uint32_t b13, uint32_t b14, uint32_t b15, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[36] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, + a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35}; + const uint32_t seeds[16] = {b0, b1, b2, b3, b4, b5, b6, b7, + b8, b9, b10, b11, b12, b13, b14, b15}; + // The epilogue's ten registers: phase 26's eight accumulator halves, then + // %r18991 and %r18993. Address space 3 (the shared scratch) explicitly: a + // generic store lowers to flat, which faults. + lds_u32* const out = (lds_u32*)(uintptr_t)scratch + 10 * (uint32_t)lane_id(); + const uint32_t lane = lane_id(); + const int t = (int)(lane & 3); // the lane's two columns of each n-tile + +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + uint32_t regs[52]; +#pragma unroll + for (int i = 0; i < 36; ++i) { + regs[i] = as1[i]; + } +#pragma unroll + for (int i = 0; i < 16; ++i) { + regs[36 + i] = seeds[i]; + } + debug_store(prm, regs, 52); + } +#endif + + // ---- phase 1 ----------------------------------------------------------- + // The 144 mma of s403-s546 are three m-groups of 48 tiles. Within a group the + // 48 tiles are eight chains of three: chain gp starts from the bias seed + // 2*gp + h (broadcast into both C registers), takes its A operand from + // fragment 3*mgrp + j at step j, its B operand from the 512-byte block + // p = 3*gp + j at the output columns 16*p + 8*h, and adds to the previous + // step's D -- so the chain is a running sum along j, not a k-accumulation. + // The tile index is i = 48*mgrp + 2*p + h; the output is 48 rows by 384 + // columns and every element is written by exactly one tile (m-tile i/48, + // n-tile i%48). The weight image is per wave: the B blocks at + // W + 12288*tid.z, the seeds at W + 256*tid.z + 4*t + 24576 + 16*seed. + const int base1 = 12288 * (int)__builtin_amdgcn_workitem_id_z(); + uint32_t d1[3][8][3][2][2]; // [m-group][chain][step][n-tile half][row half] +#pragma unroll + for (int mgrp = 0; mgrp < 3; ++mgrp) { +#pragma unroll + for (int gp = 0; gp < 8; ++gp) { +#pragma unroll + for (int j = 0; j < 3; ++j) { +#pragma unroll + for (int h = 0; h < 2; ++h) { + const int p = 3 * gp + j; + const uint32_t seed = seeds[2 * gp + h]; + const uint32_t c0 = j == 0 ? seed : d1[mgrp][gp][j - 1][h][0]; + const uint32_t c1 = j == 0 ? seed : d1[mgrp][gp][j - 1][h][1]; + mma_tile(as1 + 4 * (3 * mgrp + j), w, base1, 16 * p + 8 * h, + c0, c1, t, d1[mgrp][gp][j][h]); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 2 + { + // the oracle's stage p1: the 144 mma D pairs in mma order + uint32_t regs[288]; + int i = 0; +#pragma unroll + for (int mgrp = 0; mgrp < 3; ++mgrp) { +#pragma unroll + for (int gp = 0; gp < 8; ++gp) { +#pragma unroll + for (int j = 0; j < 3; ++j) { +#pragma unroll + for (int h = 0; h < 2; ++h) { + regs[i++] = d1[mgrp][gp][j][h][0]; + regs[i++] = d1[mgrp][gp][j][h][1]; + } + } + } + } + debug_store(prm, regs, 288); + } +#endif + + // ---- handing the accumulators back ------------------------------------ + // %r18991 = 32*tid.z (PTX line 38396) and %r18993 = the shared base (38394); + // both sit inside the cut, so the epilogue cannot recompute them. Phase 26's + // eight accumulator halves (%r18794 %r18795 %r18804 %r18805 %r18834 %r18835 + // %r18844 %r18845) are not implemented yet: lane-distinct placeholders keep + // the read-back path observable without producing wild magnitudes. + out[0] = lane; + out[1] = lane + 1u; + out[2] = lane + 2u; + out[3] = lane + 3u; + out[4] = lane + 4u; + out[5] = lane + 5u; + out[6] = lane + 6u; + out[7] = lane + 7u; + out[8] = 32u * __builtin_amdgcn_workitem_id_z(); + out[9] = scratch; +} \ No newline at end of file diff --git a/kernels/rr/rrswin_dec1_epilogues.md b/kernels/rr/rrswin_dec1_epilogues.md new file mode 100644 index 0000000..b48c391 --- /dev/null +++ b/kernels/rr/rrswin_dec1_epilogues.md @@ -0,0 +1,1006 @@ +# `cuda_dldn_engine_swin_dec1_kernel` — the epilogues of phases 1…26 + +Companion to `kernels/rr/rr_layer_spec.py dec1`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0022-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec1_kernel` (16304 statements, 44528 physical lines). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and + the next phase's first `mma`. `rr_layer_spec.py dec1` prints the ranges; this + file names what each one *computes*. Because phase 1 is the first GEMM, the + prologue (s1–s402) doubles as phase 1's prelude and is described here too. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_dec1_kernel_param_0+40]` (s8, `L1036`) and + `cvta.to.global.u64 %rd3, %rd2` (s9, `L1037`). Every + `ld.weak.global.ca.v4.u32` reads `W + 16*laneid + imm`. +* **Byte offsets are relative to `W` and (where noted) carry a `tid.z` term.** + Two epilogues' load chains add a per-`tid.z` stride that the rest of the entry + does not, so the offsets in the phase table are *not* all on one base — §1.1 + and §7/U6. +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same + cols)`, `g = laneid>>2`, `t = laneid&3`. +* Anything I could not pin down from the PTX is in §7 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `param_0` | `mov.b64 %rd8, …_param_0` | s1, L1018 | +| `W` (weight image) | `ld.param.u64 %rd2, [param_0+40]` → `cvta… %rd3, %rd2` | s8/s9, L1036–L1037 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r2195, %r2196}, [param_0+0]` | s14, L1042 | +| `%r7 = 8·ex`, `%r8 = ey·8·ex` | `shl.b32 %r7, %r2195, 3` / `mul.lo.s32 %r8, %r2196, %r7` | s15/s16, L1043–L1044 | +| block origins `%r1`, `%r2` | `sub.s32 %r1, %r2190, %r2191` / `sub.s32 %r2, %r2194, %r2192` | s7/s13, L1035/L1041 | +| `%rd1` = `param_0+80` | `add.s64 %rd1, %rd8, 80` | s4, L1032 | +| **input plane arena** | `ld.param.u64 %rd34, [param_0+8]` → `cvta… %rd35, %rd34` | s29/s30, L1057–L1058 | +| **texture / skip input** | `ld.param.u64 %rd149, [%rd1+-56]` = `param_0+24` → `cvta… %rd4, %rd149` | s2215/s2216, L4641–L4642 | +| **output plane arena** | `ld.param.u64 %rd388, [%rd8+48]` → `cvta… %rd5, %rd388` | s15754/s15755, L38150/L38151 | +| block-origin table | `ld.param.v2.u16 {%rs296, %rs297}, [param_0+80]` | s5, L1033 | +| window index `tid.z` | `mov.u32 %r9, %tid.z` | s325, L1355 | +| shared arena | `.shared .align 4 .b8 _ZZ33…dec1_kernel…E4smem[6400]` | L1027 (declaration; not a statement) | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, W, %rd` | every load block, e.g. s7214–s7215, L12685–L12686 | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd3, %rd` = `W + ((laneid·4)&12)` | e.g. s6684–s6686, L10864–L10866 | + +The last row matters: the `ld.global.v2.u16` / `ld.global.u32` table loads in an +epilogue read `W + ((laneid<<2)&12) + off`, i.e. **the same 16-byte slot is read +by the four lanes with equal `laneid&3`, and consecutive loads pick consecutive +4-byte words inside one 64-byte record** — so those tables are indexed by +column, not by row. + +Two per-`tid.z` strides exist and are used by *different* groups: + +| group | base | statements | +|---|---|---| +| phase 1's B | `W + 12288·tid.z + 16·laneid` | s326–s331, L1356–L1363 | +| phase 1's C bias | `W + 256·tid.z + ((laneid·4)&12) + 24576…24816` | s379–s402, L1459–L1484 | +| phases 2…5 B + phase 6's bias | `W + 18432·tid.z + 25216` (`%rd307`, s7073) | s7068–s7073, L11935–L11940 | + +`%rd307` is written exactly once (s7073) and consumed only by s7092–s7095 +(phase 2's B) and by the four load blocks of E2…E5 (s7122, s7153, s7184, s7215). +Every other phase's loads go straight off `W` with absolute offsets. + +### 1.2 Constants that survive between epilogues + +| register | first definition | f32/f64 literal | value used (after the `cvt` to f16) | +|---|---|---|---| +| `%f476` | s7433 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 | +| `%fd383` | s7437 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | f16 `0xB873` | +| `%fd385` | s7442 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | f16 `0x3873` | +| `%f478` | s7448 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | f16 `0x3B6B` | +| `%f480` | s7453 `mov.f32 %f480, 0f3FB00000` | 1.375 | f16 `0x3D80` | +| `%fd1` | s6143 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | f16 `0x0800` = 0.0001220703125 | +| `%f989` | s12414 `mov.f32 %f989, 0f3ED306EB` | 0.4121621549129486 | f16 `0x3698` = 0.412109375 | +| `%f990` | s12417 `mov.f32 %f990, 0f3DA60DD6` | 0.0810810774564743 | f16 `0x2D30` = 0.0810546875 | +| `%f991` | s12420 `mov.f32 %f991, 0f3F000000` | 0.5 | f16 `0x3800` | +| `%f992` | s12423 `mov.f32 %f992, 0f40000000` | 2.0 | f16 `0x4000` | + +`%f476/%fd383/%fd385/%f478/%f480` are defined **inside E6** and reused by the +second softmax — there is no second softmax here, so they are consumed by E6 +alone. `%f989…%f992` are defined **inside E10** (s12414–s12425) and re-read by +E12, E14, E16, E18, E20, E22, E24 (e.g. s12642 `cvt.rn.f16.f32 low, %f989`); +E12 is the only one that materialises them; the others only `cvt` them. + +Also live across the region (defined in the prologue, read by every warp +reduction): `%r5735 = 1` (s5579, L8209), `%r5744 = 2` (s6061, L9582), +`%r5746 = -1` (s6054, L9566) — the three operands of every +`shfl.sync.bfly.b32` in the epilogues. (`%r5746` is also reused as the +membermask of the E6 shuffles.) + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — its inverse, the *unpack*, used only when a shared or + register tile that was stored e4m3-packed is read back (E1: 144 of them, + s5590–s5676, L8241–L9556). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (round each step through f16). + +## 2. Summary + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s547–s7095 | 6549 | patch expand into shared + per-column RMS norm + gain + restage | +| E2 | s7120–s7126 | 7 | next-B weight loads (P3) | +| E3 | s7151–s7157 | 7 | next-B weight loads (P4) | +| E4 | s7182–s7188 | 7 | next-B weight loads (P5) | +| E5 | s7213–s7383 | 171 | score-bias C-seed loads (24×512 B) + 80 packs of P2/P3's D | +| E6 | s7432–s11274 | 3843 | cubic-exponent softmax, V transpose, pack | +| E7 | s11323–s11505 | 183 | pack P7's D → shared, restage A, next-B, per-column table + residual → P8's C | +| E8 | s11522–s11537 | 16 | 2 shared A fragments + 4 next-B loads (P9) | +| E9 | s11554–s12396 | 843 | RMS norm (squares, butterfly, +2⁻¹³, rsqrt, gain), packs, next B/C | +| E10 | s12413–s12833 | 421 | clamped-cubic activation + per-column table + residual, packs, next B | +| E11 | s12850–s12917 | 68 | 32 packs → P12's A, next B/C | +| E12 | s12934–s13241 | 308 | clamped-cubic activation, packs, next B | +| E13 | s13258–s13325 | 68 | 32 packs → P14's A, next B/C | +| E14 | s13342–s13649 | 308 | clamped-cubic activation, packs, next B | +| E15 | s13666–s13733 | 68 | 32 packs → P16's A, next B/C | +| E16 | s13750–s14057 | 308 | clamped-cubic activation, packs, next B | +| E17 | s14074–s14141 | 68 | 32 packs → P18's A, next B/C | +| E18 | s14158–s14465 | 308 | clamped-cubic activation, packs, next B | +| E19 | s14482–s14549 | 68 | 32 packs → P20's A, next B/C | +| E20 | s14566–s14873 | 308 | clamped-cubic activation, packs, next B | +| E21 | s14890–s14957 | 68 | 32 packs → P22's A, next B/C | +| E22 | s14974–s15281 | 308 | clamped-cubic activation, packs, next B | +| E23 | s15298–s15365 | 68 | 32 packs → P24's A, next B/C | +| E24 | s15382–s15689 | 308 | clamped-cubic activation, packs, next B | +| E25 | s15706–s15980 | 275 | pack → 16 guarded plane-arena scatter → B/C for P26 | +| E26 | s15989–s16304 | 316 | 6 D stores → shared, row max, softmax, 9+2 texture reads, surface store | + +--- + +## 3. The epilogues + +### E1 — s547–s7095: patch expand, RMS norm, gain, restage + +6549 statements; op histogram (top): 1102 `add.s32`, 523 `shl.b32`, 460 +`mov.b32`, 438 `$label`, 414 `sub.s32`, 368 `min.u32`, 341 `bra.uni`, 288 +`mul.f16`, 198 `add.f16`, 144 `cvt.rn.satfinite.e4m3x2.f16x2`, 96 +`cvt.rn.f16x2.e4m3x2`, 96 `rsqrt.approx.ftz.f32`, 96 `cvt.f32.f16`, 96 +`cvt.rn.f16.f32`, 54 `add.f16x2`, 54 `st.shared.*` (46 `u32` + 2 `v2.u16` + 6 +`v4.u32`), 36 `ld.shared.*` (24 `v2.u16` + 12 `v4.u32`), 32 +`ld.global.v2.u16`, 12 `shfl.sync.bfly.b32`, 1 `ld.param`, 2 `ld.weak…`. + +Sub-sections (bounded by the first/last statement of each op): + +| range | what | +|---|---| +| s547–s688 | 144 packs of phase 1's D → the 48 b32 `%r10…%r55` | +| s689–s1367 | per-lane index arithmetic + the 48 guarded patch stores (46 `st.shared.u32` s732–s1355 + 2 `st.shared.v2.u16` s718/s1367); 1st `bar.sync` at s1369 | +| s1413–s2214 | 24 `ld.shared.v2.u16` read back of the packed patch | +| s2215–s2216 | `param_0+24` → `%rd4`: **the patch-gather buffer** | +| s2371–s5577 | 24 clamped `ld.global.v2.u16` gathered from that buffer | +| s5578–s5674 | 96 `cvt.rn.f16x2.e4m3x2` unpacks of the read-back patch | +| s5677–s6287 | the sum-of-squares trees (198 `add.f16`, 54 `add.f16x2`) | +| s6143–s6144 | the 2⁻¹³ round (s6143 `mov.f64 %fd1`, s6144 `cvt.rn.f16.f64 %rs1082, %fd1`) | +| s6293–s6670 | 96 `rsqrt.approx.ftz.f32`, each `cvt.f32.f16 → rsqrt → cvt.rn.f16.f32` | +| s6668–s6686 | 12 statements: **gain loads** `W + ((laneid·4)&12) + {25088…25200}` (8 `ld.global.v2.u16`) | +| s5868–s6973 | the 288 `mul.f16` (two groups: `inv · gain` then `x · (inv·gain)`) | +| s6990–s7047 | 24 packs → the 6 `st.shared.v4.u32` at s7008/7021/7034/7047/7061/7066 | +| s7058–s7089 | `bar.sync` (s7072) + 12 `ld.shared.v4.u32` (s7077–s7089) → **phase 2's A** | +| s7068–s7095 | `%rd307 = W + 18432·tid.z + 25216` (s7073) and 2 `ld.weak` → **phase 2's B** | + +Evidence for the patch scatter (48 stores): + +``` +s718 L2859: st.shared.v2.u16 [%r2393], {%rs200, %rs201} +s732 L2875: st.shared.u32 [%r2400+1600], %r10 +s771 L2916: st.shared.u32 [%r2418+1600], %r12 +s783 L2932: st.shared.u32 [%r2425+3200], %r13 +s797 L2948: st.shared.u32 [%r2432+4800], %r14 +s7066 L11932: st.shared.v4.u32 [%r5949+4608], {%r5957, %r5956, %r5955, %r5954} +``` + +The 48 patch stores are 12 blocks of 4: base offsets `{0, 1600, 3200, 4800}` +(12 stores each) plus two `v2.u16` stores. Each block is guarded by + +``` +s708 L2848: setp.gt.u32 %p5, %r64, 9 +s709 L2849: setp.gt.u32 %p6, %r62, 9 +s711 L2851: @%p7 bra $L__BB1_2 +``` + +and the index is `(row_clamped·40 + col_clamped·8 + t)·4` bytes +(s714 `mad.lo.s32 %r2389, %r64, 40, %r2388`, s715 `or.b32 %r2390, %r57, %r2389`, +s716 `shl.b32 %r2391, %r2390, 2`), i.e. a **10×10 grid of 4-word cells × 4 +sub-arrays = 6400 bytes = the whole shared allocation**. (§7/U4: the guards +bound row/col at 9; I did not reduce the 438-label duplication to a closed form.) + +The gather from `param_0+24` (s2215–s2371) uses + +``` +s2245 L4674: mad.lo.s32 %r3019, %r3009, %r7, %r3018 // clamp_row·(8·ex) + clamp_col·8 +s2250 L4679: add.s32 %r19034, %r3023, %r3019 // + clamp(t, - , 7) +s2369 L4806: mul.wide.u32 %rd150, %r19034, 4 +s2371 L4808: ld.global.v2.u16 {%rs346, %rs347}, [%rd151] +``` + +so the element stride of the `+24` buffer is 4 bytes (one f16x2 = two channels), +indexed `row·(8·ex) + col·8 + clamp(t,0,7)`; the same buffer is read 24 times +per lane, once per `(row,col)` of the stencil. + +The norm itself: + +``` +s6143 L9797: mov.f64 %fd1, 0d3F20000000000000 // 2^-13 +s6144 L9799: cvt.rn.f16.f64 %rs1082, %fd1 +s6186 L9927: add.f16 %rs1161,%rs1067,%rs1082 // ...+ eps +s6293 L10243: rsqrt.approx.ftz.f32 fl, fl +s6688 L10878: mul.f16 %rs1371,%rs1372,%rs2011 // inv * gain +s6832 L11313: mul.f16 %rs1659,%rs488,%rs1371 // value * (inv*gain) +``` + +**There is no mean subtraction and no `1/N`.** The accumulated quantity is the +raw sum of squares of the patch's 3 channels plus the constant 2⁻¹³, and the +norm is applied per *column* (the gain is read at `W + ((laneid<<2)&12) + off` +so it is constant across rows). The 12 `shfl.sync.bfly.b32` sum across the four +lanes of each `laneid&3` group. + +**Inputs:** phase 1's D (`%r692…%r2083`), `W`, `param_0+8`, `param_0+24`, +`%r1/%r2/%r7/%r8/%r2195/%r2196`, `%r9` (`tid.z`). +**Outputs (live past s7095):** the 6 patch-expand `st.shared` regions, the 12 +`ld.shared.v4.u32` A fragments `%r18458…%r18505`, phase 2's B +`%r5960…%r5967`, `%rd307`, the 5 constants of §1.2. + +### E2/E3/E4 — s7120–s7126, s7151–s7157, s7182–s7188: next-B loads + +Three 7-statement blocks, each identical in shape: + +``` +s7120 L12140: mov.u32 %r6208, %laneid +s7121 L12142: mul.wide.u32 %rd309, %r6208, 16 +s7122 L12143: add.s64 %rd310, %rd307, %rd309 +s7123 L12144: add.s64 %rd203, %rd310, 2048 +s7124 L12146: ld.weak.global.ca.v4.u32 { %r6209,…%r6212},[%rd203] // +2560 as well +``` + +| epilogue | offsets added to `%rd307` (`W + 18432·tid.z + 25216`) | destination phase | +|---|---|---| +| E2 | `+2048`, `+2560` | P3's B | +| E3 | `+1024`, `+1536` | P4's B | +| E4 | `+3072`, `+3584` | P5's B | + +Nothing else. The offsets are deliberately out of phase order: the weight +sub-image is laid out P2, P4, P3, P5 (offset blocks 0, 1, 2, 3 of 1024 bytes). + +### E5 — s7213–s7383: score-bias C-seed loads + pack of P2/P3's D + +171 statements; the only epilogue whose weight loads carry the `tid.z` stride. + +* **24 loads** `W + 18432·tid.z + 16·laneid + 25216 + 4096 + 512·i`, + `i = 0…23`, at s7217…s7263 (L12689…L12781), into `%r6956…%r7051`. Byte block + `[18432·tid.z + 29312, +41100)` = 12288 bytes = 24 tiles × 512 — **phase 6's C + score-bias seed**. +* **80 packs / 40 b32**, s7264–s7383, whose sources are registers written by + **phase 2's and phase 3's mma** (`%r6466/6467/6486/6487/…` from s7096–s7126 + and s7127–s7136). Two interleaved destinations — `%r7498 %r7508 …` and + `%r7244 %r7246 …` — which become phase 6's B and A respectively (verified: + `%r7244 ← mov.b32 {%rs2061,%rs2062}` at s7338 whose sources are + `cvt` of `%r6466/%r6486`; `%r7498 ← mov.b32 {%rs2013,%rs2014}` at s7266 whose + source is `cvt` of `%r6466` at s7265). + +**The C-seed layout.** The four C registers of one mma are the four u32 of one +16-byte lane slot, and the tile index runs `4·(n>>1) + m` — the same scheme +`rrswin_enc0_epilogues.md` §3/E9 established. Checked against phase 6's own +operands: `s7384 C=%r6956,%r6957`, `s7385 C=%r6958,%r6959`, +`s7390 C=%r7004,%r7005`, `s7391 C=%r7006,%r7007` — consecutive pairs from the +load block, i.e. mma `(m, n)` takes the slot `(n>>1)` of the load block. + +### E6 — s7432–s11274: cubic-exponent softmax, V transpose, pack + +**Identical in kind to `cuda_dldn_engine_swin_enc0_kernel`'s E5** (see +`rrswin_enc0_epilogues.md` §3/E5) and byte-for-byte the same op histogram: +1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 `cvt.rn.f16.f64`, 192 each of +`fma.rn.f16x2` / `cvt.f32.f16` / `rcp.approx.ftz.f32` / `mul.f16`, 144 packs, +48 `movmatrix`, 16 `shfl.sync.bfly.b32`, 96 each of `max/min/neg/abs.f16x2`. + +Sub-sections: + +| range | stmts | what | +|---|---|---| +| s7433–s7458 | 26 | the 5 constants (§1.2): s7433 `mov.f32 %f476, 0f3C8CCB50`, s7437/s7442 the two f64 clamps, s7448/s7453 the cubic pair | +| s7459–s9549 | 2091 | 96 per-element groups (scale, clamp, cubic, `and.b32 …,2145419232`) | +| s9550–s9635 | 86 | in-lane partial sums (`add.f16x2`) | +| s9636–s9765 | 130 | 16 `shfl.sync.bfly` → 8 row sums | +| s9766–s10587 | 822 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s10588–s11010 | 423 | 192 `mul.f16` → 96 probabilities | +| s11011–s11058 | 48 | `movmatrix.sync.trans.aligned.m8n8.b16` of **phase 5's** D | +| s11059–s11273 | 215 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs | + +Evidence: + +``` +s7459 L13474: and.b32 %r9534, %r18506, 2145419232 // 0x7FE07FE0 +s9636 L20270: shfl.sync.bfly.b32 %r9778,%r9774,%r5735,%r9781,%r5746 +s9766 L20596: rcp.approx.ftz.f32 fl, fl +s11011 L22895: movmatrix.sync.trans.aligned.m8n8.b16 %r10138, %r6715 +s11059 L23039: cvt.rn.satfinite.e4m3x2.f16x2 %rs3462, %r10146 +``` + +The transposed registers `%r6715…%r6946` are exactly phase 5's D (s7189–s7212). +`%r10138/%r10146/…` are the movmatrix results; the pack at s11059 takes +`%r10146`, i.e. the transposed V is what becomes **phase 7's B** (checked: +`%r10744 ← mov.b32 {%rs3461,%rs3462}` at s11061, and `%r10744` is phase 7's +first B pair; the probability packs, e.g. `%r10450 ← mov.b32 +{%rs3509,%rs3510}` at s11133, feed phase 7's A). `%r6715` is phase 5's first D +and `%r6946` its last, so all 48 movmatrix inputs are phase 5's D. + +For the record, the per-element function (identical to enc0's E5(a), reproduced +here because it is the only arithmetic in this file that is *not* obviously a +named primitive): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +u = f16(1.375 + m*(0.92724609375 - m*m)) +expval = f16 from bits ((u_bits << 5) & 0x7FE07FE0) +``` + +**There is no row maximum in E6** (the only `max.f16x2`/`min.f16x2` are the 96 +clamp pairs of (a)), and no bias add — the bias is phase 6's GEMM C operand. + +**Inputs:** phase 6's 96 D f16x2, phase 5's 48 D f16x2, `%r5735/%r5744/%r5746`. +**Outputs:** the 5 constants, phase 7's 12 A fragments + 12 B fragments. +**Memory:** none (0 `ld.*`, 0 `st.*` in 3843 statements). + +### E7 — s11323–s11505: pack P7's D → shared, restage, next-B, table → P8's C + +183 statements: 64 `add.f16`, 48 `mov.b32`, 32 packs, 8 `ld.global.v2.u16`, +4 `st.shared.v4.u32`, 4 `ld.shared.v4.u32`, 4 `ld.weak`, 6 `add.s64`. + +``` +s11323 L23878: bar.sync 0 +s11339 L23912: st.shared.v4.u32 [%r18635], {%r18639, %r18638, %r18637, %r18636} +s11352 L23941: st.shared.v4.u32 [%r18635+512], {…} +s11365 L23970: st.shared.v4.u32 [%r18635+1024], {…} +s11378 L23999: st.shared.v4.u32 [%r18635+1536], {…} +s11379 L24000: bar.sync 0 +s11384 L24007: ld.shared.v4.u32 {%r18655,…%r18658}, [%r18654] +s11385 L24008: ld.shared.v4.u32 {%r18659,…%r18662}, [%r18654+512] +s11390 L24016: ld.weak.global.ca.v4.u32 { %r10893,…%r10896},[%rd233] // W+41600 +s11402 L24037: ld.global.v2.u16 {%rs5218, %rs5219}, [%rd322+62096] +s11410 L24046: add.f16 %rs3640,%rs5233,%rs491 +``` + +* **32 packs of phase 7's D** (`%r10378…%r10428`, the 192×96 banded P·V output) + → 16 b32 → four `st.shared.v4.u32` at `[%r18635 + {0,512,1024,1536}]`; the + `bar.sync` pair makes them visible, then **two `ld.shared.v4.u32` give phase + 8's A** (`%r18655…%r18662`). +* **4 `ld.weak` at `W + 16·laneid + {41600, 42112, 42624, 43136}`** → phase 8's B. +* **8 `ld.global.v2.u16` at `W + ((laneid·4)&12) + {62080…62192}`** — a + per-column vector, 8 words per lane = 32 columns. +* **64 `add.f16`** adding that vector to the *f16 halves of phase 7's D* which + were unpacked at s6186–s6288 (`%rs488/%rs491/%rs494…`), producing + `%r10918 %r10919 %r10928 %r10929 …` — **phase 8's C operand** (confirmed: + `s11506 C=%r10918,%r10919`, `s11507 C=%r10928,%r10929`). So phase 8 computes + `D8 = A8·B8 + (D7 + column_table)`. + +### E8 — s11522–s11537: next-A and next-B for P9 + +``` +s11525 L24450: ld.shared.v4.u32 {%r18666,…%r18669}, [%r18665+2048] +s11526 L24451: ld.shared.v4.u32 {%r18670,…%r18673}, [%r18665+2560] +s11531 L24459: ld.weak.global.ca.v4.u32 { %r11072,…%r11075},[%rd237] // W+60032 +s11537 L24471: ld.weak.global.ca.v4.u32 { %r11084,…%r11087},[%rd240] // W+61568 +``` + +Two shared A fragments (the upper half of the same staging region, offsets 2048 +and 2560 relative to `%r18652`) and four weight fragments at +`W + {60032, 60544, 61056, 61568}` → phase 9's A and B. + +### E9 — s11554–s12396: RMS norm before the second attention window + +843 statements, no stores, 16 memory ops. Structure: + +| range | stmts | op | +|---|---|---| +| s11554–s11699 | 146 | 32 × `x·x` squares of phase 9's D | +| s11700–s11757 | 58 | in-lane pairwise `add.f16x2` | +| s11714–s11757 | 44 | 8 `shfl.sync.bfly` (2 per row) → row sums | +| s11764–s11779 | 16 | `add.f16` of the two halves, then `+ 2⁻¹³` (§1.2 `%fd1`) | +| s11779–s11880 | 102 | broadcast each row sum into 4 b32 | +| s11883–s12128 | 246 | 64 `rsqrt.approx.ftz.f32` | +| s12129–s12136 | 8 | **gain loads** `W + ((laneid·4)&12) + {62208…62320}` | +| s12137–s12232 | 96 | `mul.f16` — `inv · gain` | +| s12233–s12328 | 96 | `mul.f16` — `x · (inv·gain)` → 32 b32 `%r17567…%r17598` | +| s12332–s12339 | 8 | next-B loads `W + {62336, 62848, 63360, 63872}` → phase 10's B | +| s12341–s12348 | 8 | next-C loads `W + ((laneid·4)&12) + {64384,64400,64416,64432}` → phase 10's C | +| s12349–s12396 | 48 | 32 packs → phase 10's A (`%r11574…%r11577`, `%r11594…`, …) | + +Evidence: + +``` +s11557 L24589: mul.f16 %rs3832,%rs4647,%rs4647 // square of a D half +s11714 L25018: shfl.sync.bfly.b32 %r11325,%r11321,%r5735,%r11328,%r5746 +s11776 L25176: cvt.rn.f16.f64 %rs4033, %fd1 // eps = 2^-13 +s11883 L25588: rsqrt.approx.ftz.f32 fl, fl +s12129 L25883: ld.global.v2.u16 {%rs5234, %rs5235}, [%rd327+62224] +s12233 L26180: mul.f16 %rs4421,%rs4647,%rs4229 // D_half * (inv*gain) +s12332 L26472: add.s64 %rd241, %rd329, 62336 +s12349 L26500: cvt.rn.satfinite.e4m3x2.f16x2 %rs4611, %r17568 +``` + +**What it computes.** For each of the 8 rows a lane holds: + +``` +sumsq[row] = Σ_c x[row,c]² (f16, 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2⁻¹³))) (rounded to f16) +out[row,c] = x[row,c] · inv · gain[c] +``` + +* **no mean subtraction and no `1/N`** — the quantity is the raw sum of squares + plus the constant 2⁻¹³. +* `gain[c]` is per *column* (the `W + ((laneid<<2)&12)` pattern) and constant + across rows. +* the `inv` register is duplicated into both halves of a b32 before use, so one + row-sum serves every n-tile of that row (64 `rsqrt` for 16 row sums). +* the norm's *bias* is not added here; it is phase 10's C, loaded at the end of + this epilogue (s12345–s12348). + +**Outputs:** `%r11473 %r11477` (P10 B), `%r11611 %r11621 %r11651 %r11661` +(P10 C), 16 packed A registers, the 32 f16x2 normed values `%r17567…%r17598` +(re-packed by E11). + +#### Shape of the attention region (E5–E9) + +``` +P2 A = patch(shared), B = W+25216+2048, C = 0 → D2 (96×32) +P3 A = patch(shared), B = W+25216+ 0, C = 0 → D3 (96×32) +P4 A = patch(shared), B = W+25216+1024, C = D2 → D4 +P5 A = patch(shared), B = W+25216+3072, C = D3 → D5 + E5 packs D2 ∪ D3 → P6 A and B; E5 loads P6 C = bias@29312 +P6 A = pack(D2∪D3), B = pack(D2∪D3), C = bias → scores 64×96 + E6: softmax over the 96 columns (no row max), 48 movmatrix(D5), pack +P7 A = pack(prob), B = pack(transpose(D5)), C = 0 → D7 (192×96) + E7: pack D7 → shared; P8 C = D7 + column table@62080; P8 B = W+41600 +P8 A = shared, B = W+41600, C = D7+table → D8 +P9 A = shared+2048, B = W+60032, C = 0 → D9 + E9: RMS norm of D9 + gain, packs → P10 A +``` + +### E10 — s12413–s12833: clamped-cubic activation, per-column table, residual + +421 statements; this is the only epilogue that materialises `%f989…%f992`. + +``` +s12414 L26726: mov.f32 %f989, 0f3ED306EB +s12420 L26740: mov.f32 %f991, 0f3F000000 // 0.5 +s12426 L26755: neg.f16x2 %r11687,%r11686 +s12427 L26759: max.f16x2 %r11689,%r11542,%r11687 +s12428 L26763: min.f16x2 %r11692,%r11689,%r11686 +s12429 L26767: abs.f16x2 %r11695,%r11692 +s12432 L26779: mul.f16x2 %r11703,%r11692,%r11700 +s12433 L26783: add.f16x2 %r11706,%r11685,%r11703 +s12434 L26787: mul.f16x2 %r11709,%r11542,%r11706 +``` + +Per element, over each of the 16 f16x2 D registers of phase 10: + +``` +y = clamp(x, -2, +2) +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a *cubic ramp*, not a sigmoid: `g(+2)=1 ⇒ out=x` for `x ≥ 2`; +`g(-2)=0 ⇒ out=0` for `x ≤ -2`. **Reproduce the formula, not SiLU/GELU.** + +Then: + +| range | op | +|---|---| +| s12413–s12689 | 16 activation groups | +| s12693–s12700 | next-B loads `W + {64448,64960,65472,65984}` → phase 11's B | +| s12701–s12713 | `ld.global.v2.u16` at `W + ((laneid·4)&12) + {66496…66608}` | +| s12714–s12809 | 64 `add.f16` — residual add, written over the **activation inputs** (`%rs4644/%rs4647`, unpacked at s11556/… from phase 9's D) | +| s12810–s12833 | 16 packs of the activation outputs → phase 12's A | + +Evidence for the residual add: + +``` +s12706 L27718: ld.global.v2.u16 {%rs5250, %rs5251}, [%rd337+66512] +s12714 L27727: add.f16 %rs4645,%rs5265,%rs4647 +s12716 L27734: mov.b32 %r12189, {%rs4642, %rs4645} +s12810 L28015: cvt.rn.satfinite.e4m3x2.f16x2 %rs4835, %r11825 +``` + +The residual is **phase 9's D**, not phase 10's: `%rs4644/%rs4647` are the halves +of `%r11088`, unpacked at s11556 (`mov.b32 {%rs4644, %rs4647}, %r11088`) at the +very start of E9, and `%r11088` is written by phase 9's mma (s11538–s11553). +The 32 such registers `%r12189 %r12190 … %r12329 %r12330` are **phase 11's C**; +`%r12148 %r12152 …` are phase 11's B. + +Note the two pack streams: the *activation* outputs (`%r11709`, `%r11825`, …) go +to phase 12's A, while the *residual+table* registers go to phase 11's C. + +### E11 — s12850–s12917: packs of the normed tile, next B/C + +68 statements: 32 packs, 4 `ld.weak`, 4 `ld.global.u32`. + +``` +s12854 L28189: ld.weak.global.ca.v4.u32 { %r12342,…%r12345},[%rd249] +s12866 L28210: ld.global.u32 %r12480, [%rd342+68672] +s12870 L28216: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r17567 +``` + +* four `v4.u32` fragments at `W + {66624, 67136, 67648, 68160}` → phase 12's B; +* four `ld.global.u32` at `W + ((laneid·4)&12) + {68672, 68688, 68704, 68720}` + → **phase 12's C seed**, each used in both halves of the C operand; +* **32 packs of `%r17567…%r17598`** — the *normalised* tile E9 produced — so + phase 12's A operand is bit-identical to phase 10's A. Phases 10 and 12 are + two parallel GEMMs off the same normed tile. + +### E12 — s12934–s13241: clamped-cubic activation, no residual + +308 statements; op mix 72 `mov.b32`, 64 `cvt.rn.f16.f32`, 48 `mul.f16x2`, 16 +each `neg/max/min/abs/sub/add.f16x2`, 4 `ld.weak`, 16 packs. **No constants of +its own** (it re-`cvt`s `%f989` etc. at s12642-equivalent sites) and **no +`ld.global`**. + +Same function as E10; 16 packs of the activation outputs +(`%r13046` at s13191, …) → phase 13's A, plus 4 weight loads at +`W + {68736, 69248, 69760, 70272}` → phase 13's B. **No table add and no +residual**, so phase 13's C is zero. + +### E13 — s13258–s13325: packs of the normed tile again, next B/C + +68 statements, shape-identical to E11: + +``` +s13262 L29597: ld.weak.global.ca.v4.u32 { %r13210,…},[%rd257] +s13274 L29618: ld.global.u32 %r13348, [%rd349+72832] +``` + +B at `W + {70784, 71296, 71808, 72320}` → phase 14's B; **32 packs of +`%r17567…%r17598` — the normed tile for the second time**; C at +`W + ((laneid·4)&12) + {72832, 72848, 72864, 72880}` → phase 14's C. + +### E14/E16/E18/E20/E22/E24 — s13342–s13649, s13750–s14057, s14158–s14465, s14566–s14873, s14974–s15281, s15382–s15689: activation + packs + next B + +Six shape-identical 308-statement epilogues (shape hash `4234ec4de215`). Each +applies the E10 activation to the D of its own phase, then 16 packs of the +activation outputs → the next odd phase's A, and 4 weight loads → the next odd +phase's B. Evidence (E14): + +``` +s13376 L30936: cvt.rn.f16.f32 low, %f989 +s13393 L30985: mul.f16x2 %r13727,%r13634,%r13724 +s13619 L30816: ld.weak.global.ca.v4.u32 { %r13885,…},[%rd261] // W+70784 +s13633 L30986: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r13727 +``` + +Offsets: E12→{68736,69248,69760,70272}, E14→{70784,71296,71808,72320}, +E16→{72896,73408,73920,74432}, E18→{74944,75456,75968,76480}, +E20→{77056,77568,78080,78592}, E21's targets … (from the phase table's weight +column: P13=68736, P15=72896, P17=77056, P19=81216, P21=85376, P23=89536, +P25=93696). + +No `ld.global`, no table add, no residual: these six produce only A and B. + +### E15/E17/E19/E21/E23 — s13666–s13733, s14074–s14141, s14482–s14549, s14890–s14957, s15298–s15365: packs + next B/C + +Five shape-identical 68-statement epilogues (shape hash `819f37d58cd2`), the +twin of E11/E13. Example (E15): + +``` +s13670 L31005: ld.weak.global.ca.v4.u32 { %r14078,…},[%rd265] +s13682 L31026: ld.global.u32 %r14216, [%rd356+76992] +s13686 L31031: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r17567 +``` + +B at `W + {72896+1024…}` etc. per the phase table; C at +`W + ((laneid·4)&12) + {76992, 77008, 77024, 77040}` (E15 → phase 16's C); +**32 packs of `%r17567…%r17598`, the normed tile — third, fourth, fifth, sixth +and seventh time** (E13, E15, E17, E19, E21, E23 all pack the same 32 f16x2). + +#### Shape of the whole MLP region (E9–E25) + +``` +E9 normed tile N (32 f16x2, %r17567…%r17598, s12349 packs) + ├─ pack → P10 A (s12349) P10: A=N, B=W10, C=bias@64384 → act (E10) + │ pack of act → P12 A (s12870) + │ E10: P11 C = D9 + table@66496 + ├─ pack → P12 A (s12870) P12: A=N, B=W12, C=bias@68672 → act (E12) + │ pack of act → P14 A (s13394) + ├─ pack → P14 A (s13394) P14: A=N, B=W14, C=bias@72832 → act (E14) + ├─ pack → P16 A (s13806) P16: A=N, B=W16, C=bias@76992 → act (E16) + ├─ pack → P18 A (s14218) P18: A=N, B=W18, C=bias@81152 → act (E18) + ├─ pack → P20 A (s14630) P20: A=N, B=W20, C=bias@85312 → act (E20) + ├─ pack → P22 A (s15042) P22: A=N, B=W22, C=bias@89472 → act (E22) + └─ pack → P24 A (s15454) P24: A=N, B=W24, C=bias@93632 → act (E24) + pack of act → P25 A (s15666) +``` + +The odd phases P11, P13, …, P25 take `C = 0` and produce the residual pair that +the following even phase's table adds. + +### E25 — s15706–s15980: pack → 16 guarded plane-arena stores → B/C for P26 + +275 statements; the only `st.global` in the entry (16 of them, all here). + +**(a) requantise, s15706–s15753.** 24 groups of `2 cvt + 1 mov.b32` → 24 b32; +the 16 consumed are `%r489…%r504`. + +**(b) plane-arena scatter, s15754–s15960.** + +``` +s15754 L38150: ld.param.u64 %rd388, [%rd8+48] // = param_0+48 +s15755 L38151: cvta.to.global.u64 %rd5, %rd388 +s15757 L38155: shr.u32 %r505, %r18449, 2 // g = laneid>>2 +s15758 L38156: and.b32 %r506, %r18449, 3 // t = laneid&3 +s15761 L38159: add.s32 %r18707, %r488, %r18705 // y = %r488 + (laneid>>5) +s15767 L38165: add.s32 %r18713, %r1, %r18706 // x = %r1 + (g&7) +s15772 L38170: shl.b32 %r18714, %r18713, 3 // x<<3 +s15773 L38171: mad.lo.s32 %r507, %r7, %r18707, %r18714 +s15775 L38173: selp.b32 %r508, -1, %r18715, %p1 +s15780 L38179: st.global.u32 [%rd390], %r489 +``` + +Stride register `%r7 = 8·ex` (s15). Every store is +`idx = 8·ex·y + 8·x + d`, with `d = t` or `t|4`; each of the four base slices is +guarded by its own predicate of the form +`(y<0)|(y≥ey)|(laneid>127)|(x<0)|(x≥ex)` (e.g. s15762–s15771, +L38160–L38169); a guard failure stores `-1` as the index, which the following +`setp.lt.s32 %p, %idx, 0` + `bra` turns into "skip the store" +(s15774–s15777). + +Store values, bases and column offsets (`g = laneid>>2`, `t = laneid&3`, +`%r488 = %r2 + 4·tid.z` at s11555/L24586, `%r8 = ey·8·ex`): + +| store | stmt | value | index base | d | +|---|---|---|---|---| +| 1 | s15780 | `%r489` | `idx1` | `t` | +| 2 | s15789 | `%r490` | `idx1` | `t\|4` | +| 3 | s15815 | `%r491` | `idx2` | `t` | +| 4 | s15823 | `%r492` | `idx2` | `t\|4` | +| 5 | s15832 | `%r493` | `idx1 + %r8` | `t` | +| 6 | s15840 | `%r494` | `idx1 + %r8` | `t\|4` | +| 7 | s15849 | `%r495` | `idx2 + %r8` | `t` | +| 8 | s15857 | `%r496` | `idx2 + %r8` | `t\|4` | +| 9 | s15883 | `%r497` | `idx3` | `t` | +| 10 | s15891 | `%r498` | `idx3` | `t\|4` | +| 11 | s15917 | `%r499` | `idx4` | `t` | +| 12 | s15925 | `%r500` | `idx4` | `t\|4` | +| 13 | s15934 | `%r501` | `idx3 + %r8` | `t` | +| 14 | s15942 | `%r502` | `idx3 + %r8` | `t\|4` | +| 15 | s15951 | `%r503` | `idx4 + %r8` | `t` | +| 16 | s15959 | `%r504` | `idx4 + %r8` | `t\|4` | + +with the four bases built as `mad.lo.s32 %rBASE, 8·ex, y, 8·x`: + +| base | stmt | y | x | +|---|---|---|---| +| `idx1 = %r507` | s15773, L38171 | `%r488 + (laneid>>5)` | `%r1 + (g&7)` | +| `idx2 = %r511` | s15808, L38210 | `%r488 + ((g+8)>>3)` | `%r1 + ((g+8)&7)` | +| `idx3 = %r520` | s15876, L38290 | `%r488 + ((g+16)>>3)` | `%r1 + ((g+16)&7)` | +| `idx4 = %r523` | s15910, L38328 | `%r488 + ((g+24)>>3)` | `%r1 + ((g+24)&7)` | + +The `g+8j` slices come from `add.s32 %r18717, %r18986, 8` (s15793, L38195), +`add.s32 %r18734, %r18988, 16` (s15861, L38275) and +`add.s32 %r18747, %r18990, 24` (s15895, L38313); each base carries its own +guard predicate (`p1…p4`) of the form +`(y<0)|(y≥ey)|(slice>31)|(x<0)|(x≥ex)`. + +**(c) next B/C, s15961–s15980.** + +``` +s15962 L38392: ld.param.u64 %rd456, [param_0+40] +s15969 L38401: add.s64 %rd424, %rd456, %rd423 // + 16*laneid +s15971 L38404: ld.weak.global.ca.v4.u32 { %r18765,…%r18768},[%rd421] // +95744 +s15973 L38408: ld.weak.global.ca.v4.u32 { %r18769,…%r18772},[%rd422] // +96256 +s15979 L38417: ld.global.u32 %r18823, [%rd428+96768] +s15980 L38418: ld.global.u32 %r18833, [%rd428+96784] +``` + +Note `%rd424` is built from `%rd456` (the *un*cvtad pointer) while `%rd455` is +cvtad; on this corpus both are the same address, and the offsets still read +`W + ….` + +**Outputs:** `%r489…%r504` (re-read as P26's A, see s15981), `%r18765 %r18769` +(P26 B), `%r18823 %r18833` (P26 C), `%rd388` (`param_0+48`). + +### E26 — s15989–s16304: the final epilogue + +316 statements; it consumes the six D accumulators of phase 26 +(`%r18794 %r18795 %r18804 %r18805 %r18834 %r18835 %r18844 %r18845` — the +`s15996`…`s15988` mma results) and writes the surface. + +**(a) staging, s15989–s16050.** 12 guarded `st.shared.u32` of the phase-26 D +pairs into a shared scratch, indexed from `%r540 = laneid>>2`, `%r541 = laneid&3` +and `%tid.z`: + +``` +s16000 L38488: st.shared.u32 [%r542], %r18794 +s16004 L38493: st.shared.u32 [%r542+16], %r18804 +s16017 L38507: st.shared.u32 [%r544], %r18795 +s16019 L38510: st.shared.u32 [%r544+16], %r18805 +``` + +**(b) coordinates and bounds check, s16051–s16084.** + +``` +s16059 L38555: mov.u32 %r18897, %tid.x +s16060 L38556: add.s32 %r18898, %r19003, %r18897 // %r19003 = tid.z*32 +s16065 L38561: sub.s32 %r547, %r18898, %r18902 +s16067 L38563: add.s32 %r549, %r1, %r547 // x +s16068 L38564: add.s32 %r550, %r19004, %r548 // y, %r19004 = ctaid.y*8 - origin +s16073 L38569: ld.param.v2.u32 {%r18912, %r18913}, [%rd458] +s16078 L38574: @%p480 bra $L__BB1_534 +``` + +Out-of-range lanes jump straight to `$L__BB1_534` (s16303) and skip (c)…(g). + +**(c) row max over 5 shared values, s16085–s16100.** + +``` +s16085 L38582: ld.shared.u32 %r18915, [%r18964] +s16087 L38584: ld.shared.u32 %r18916, [%r18964+4] +s16091 L38588: ld.shared.u32 %r18936, [%r18964+16] +s16093 L38591: max.f16x2 %r18914,%r18915,%r18916 +s16097 L38604: max.f16 %rs5266,%rs5267,%rs5268 +s16099 L38611: mov.b32 %r18937, {%rs5269, %rs5269} +s16100 L38613: sub.f16x2 %r18923,%r18915,%r18937 +``` + +Five `u32` (= 10 f16) are read per row and reduced in registers — **no warp +shuffle** — giving the row max, which is subtracted. + +**(d) softmax, s16101–s16168.** Textbook f32 softmax over the row's 5 values: + +``` +s16103 L38621: mul.ftz.f32 %f1033, %f993, 0f3FB8AA3B // * log2(e) +s16104 L38622: ex2.approx.ftz.f32 %f995, %f1033 +s16160 L38741: mov.f32 %f1032, 0f3F800000 +s16161 L38742: div.approx.ftz.f32 %f1011, %f1032, %f1050 +s16164 L38749: mul.f16x2 %r18938,%r18939,%r18952 +``` + +`y = 2^((x−max)·log2e)`, `p = y · (1/Σy)` in f16, five f16x2 registers +(`%r18938 %r18941 %r18944 %r18947 %r18950`). + +**(e) texture gather, s16169–s16266.** A 3×3 stencil of a colour texture: + +``` +s16184 L38789: cvt.rn.f32.s32 %f1051, %r18968 +s16185 L38790: ld.param.v2.f32 {%f1052, %f1053}, [%rd459+136] +s16187 L38792: fma.rn.ftz.f32 %f1012, %f1052, %f1051, %f1056 +s16191 L38796: ld.param.u64 %rd446, [%rd459+88] +s16193 L38799: tex.base.2d.v4.f16.f32 {%rs5294,%rs5295,%rs5296,%rs5297}, [%rd430, {%f1012,%f1013}] +s16195 L38803: fma.rn.f16 %rs5298,%rs5294,%rs5308,%rs5291 +``` + +`%rd459 = param_0` (s16079), so the texture handle is **`param_0+88`**, the +scale/offset are **`param_0+136`** (two f32: `f1052·(k−0.5·?)`) and the +accumulator weights come from the softmax registers. Nine +`tex.base.2d.v4.f16.f32` are issued (s16193, 16205, 16217, 16229, 16234, 16240, +16252, 16258, 16263) for the 3×3 neighbourhood (clamped coordinates at +s16172–s16183 compute `(x−1, x, x+1)` and `(y−1, y, y+1)`), accumulated with +`fma.rn.f16` into 3 channels. + +**(f) two integer-coordinate textures, s16267–s16270.** + +``` +s16267 L38971: ld.param.u64 %rd448, [%rd459+96] +s16268 L38973: tex.base.2d.v4.f16.s32 {%rs5438,%rs5439,%rs5440,%rs5441}, [%rd448, {%r549,%r550}] +s16269 L38975: ld.param.u64 %rd450, [%rd459+104] +s16270 L38977: tex.base.2d.v4.f16.s32 {%rs5442,%rs5443,%rs5444,%rs5445}, [%rd450, {%r549,%r550}] +``` + +**These are the `+96` / `+104` texture reads the brief asks about** — handles at +`param_0+96` and `param_0+104`, sampled at the *integer* pixel coordinate +`(%r549, %r550)`, returning two 4-channel f16 vectors. + +**(g) combine, sigmoid gate, surface store, s16271–s16304.** + +``` +s16271 L38980: cvt.f32.f16 %f1030, %rs5446 +s16272 L38983: mul.ftz.f32 %f1063, %f1030, 0fBFB8AA3B +s16273 L38984: ex2.approx.ftz.f32 %f1064, %f1063 +s16274 L38985: add.ftz.f32 %f1065, %f1064, 0f3F800000 +s16275 L38986: div.approx.ftz.f32 %f1031, %f1032, %f1065 // 1/(1+2^(-log2e·v)) +s16278 L38996: sub.f16 %rs5449,%rs5448,%rs5447 // 1 - sigmoid +s16279 L39000: mul.f16 %rs5452,%rs5426,%rs5447 // acc * sigmoid +s16280 L39004: fma.rn.f16 %rs5495,%rs5438,%rs5449,%rs5452 // + tex96 * (1-sig) +s16285 L39024: set.nan.f16.f16 %rs5473,%rs5442,%rs5442 // + tex104 unless NaN +s16302 L39065: sust.b.2d.v4.b16.zero [%rd453, {%r18983,%r550}], {%rs5495,%rs5496,%rs5497,%rs5494} +``` + +`%rd453 = param_0+112` (s16090). The store address column is `%r549·8` (s16300 +`shl.b32 %r18983, %r549, 3`), the row `%r550`; the fourth channel is the zero +literal `0x0000` (s16301 `mov.u16 %rs5494, 0`), so this is a **3-channel write +into a 4-channel surface**. The `set.nan`/`bra` triad (s16285–s16298) adds the +`+104` read only when it is not NaN. + +**Inputs:** the 6 returned D registers, `param_0+{48,88,96,104,112,136}`, the +shared scratch, constants `0f3FB8AA3B`, `0fBFB8AA3B`, `0f3F800000`. +**Outputs:** none (the kernel returns, s16304). + +--- + +## 4. Texture reads, surface writes, and the `+24` input + +| what | where | +|---|---| +| `param_0+8` — input feature plane arena, read by phase 1's A loads | prologue s67…s324 (52 `ld.global.u32`) | +| `param_0+24` — the patch-gather source E1 reads | s2215 (`ld.param.u64 %rd149, [%rd1+-56]`, `%rd1 = param_0+80`) and the 24 `ld.global.v2.u16` at s2371…s5577 | +| `param_0+48` — the plane arena E25 scatters phase 25's output to | s15754 / s15755, 16 `st.global.u32` at s15780…s15959 | +| `param_0+88` — the colour texture handle | s16191, 9 `tex.base.2d.v4.f16.f32` at s16193…s16263 | +| `param_0+96` — texture handle #2 (integer coords) | s16267/s16268 | +| `param_0+104` — texture handle #3 (integer coords) | s16269/s16270 | +| `param_0+112` — the output surface | s16090, `sust.b.2d.v4.b16.zero` s16302 | +| `param_0+136` — two f32 texture coordinate scales | s16185 | + +**The skip input at `+24` supplies the patch-gather source.** E1 reads it once +per lane per stencil position and never writes it; the buffer is addressed in +elements of 4 bytes (one f16x2 = 2 channels) with index +`clamp(row)·8·ex + clamp(col)·8 + clamp(t,0,7)` (s2245/s2250, L4674/L4679). It +is the *input* the patch expand tile is built from — the same operand the +window-1 patch is expanded out of. + +**The surface writes** are `param_0+112` (E26, s16302), a 4-channel b16 surface +written with 3 live channels. The **plane-arena writes** are E25's 16 +`st.global.u32` to `param_0+48` (s15780…s15959). + +**Nothing reads `param_0+48` back** in this entry: `param_0+48` is the source of +exactly one `ld.param` (s15754) and never the base of a load. Likewise the +texture handles at `+88/+96/+104` are only ever `tex.*` operands. + +## 5. The phase table, M/N/K checked + +`rr_layer_spec.py dec1`'s phase table with the arithmetic `M/16 · N/8 · K/32 == +mma` evaluated on every row (the brief's check): + +| # | stmts | M | N | K | mma | M/16·N/8·K/32 | holds? | weight bytes (rel. `W`) | bias bytes | +|---|---|---|---|---|---|---|---|---|---| +| 1 | s403–s546 | 144 | 384 | 96 | 144 | 9·48·3 = 1296 | **no** | 0…11788 (+12288·`tid.z`) | 24576…24816 (+256·`tid.z`) | +| 2 | s7096–s7119 | 96 | 32 | 32 | 24 | 6·4·1 = 24 | yes | 25216…25740 (+18432·`tid.z`) | – | +| 3 | s7127–s7150 | 96 | 32 | 32 | 24 | 24 | yes | 27264…27788 (+18432·`tid.z`) | – | +| 4 | s7158–s7181 | 96 | 32 | 32 | 24 | 24 | yes | 26240…26764 (+18432·`tid.z`) | – | +| 5 | s7189–s7212 | 96 | 32 | 32 | 24 | 24 | yes | 28288…28812 (+18432·`tid.z`) | – | +| 6 | s7384–s7431 | 64 | 96 | 32 | 48 | 4·12·1 = 48 | yes | **none** | 29312…41100 (+18432·`tid.z`) | +| 7 | s11275–s11322 | 192 | 96 | 96 | 48 | 12·12·3 = 432 | **no** | **none** | – | +| 8 | s11506–s11521 | 32 | 64 | 32 | 16 | 2·8·1 = 16 | yes | 41600…43148 | – | +| 9 | s11538–s11553 | 32 | 64 | 32 | 16 | 16 | yes | 60032…61580 | – | +| 10 | s12397–s12412 | 64 | 64 | 64 | 16 | 4·8·2 = 64 | **no** | 62336…63884 | 64384…64432 | +| 11 | s12834–s12849 | 32 | 64 | 32 | 16 | 16 | yes | 64448…65996 | – | +| 12 | s12918–s12933 | 64 | 64 | 64 | 16 | 64 | **no** | 66624…68172 | 68672…68720 | +| 13 | s13242–s13257 | 32 | 64 | 32 | 16 | 16 | yes | 68736…70284 | – | +| 14 | s13326–s13341 | 64 | 64 | 64 | 16 | 64 | **no** | 70784…72332 | 72832…72880 | +| 15 | s13650–s13665 | 32 | 64 | 32 | 16 | 16 | yes | 72896…74444 | – | +| 16 | s13734–s13749 | 64 | 64 | 64 | 16 | 64 | **no** | 74944…76492 | 76992…77040 | +| 17 | s14058–s14073 | 32 | 64 | 32 | 16 | 16 | yes | 77056…78604 | – | +| 18 | s14142–s14157 | 64 | 64 | 64 | 16 | 64 | **no** | 79104…80652 | 81152…81200 | +| 19 | s14466–s14481 | 32 | 64 | 32 | 16 | 16 | yes | 81216…82764 | – | +| 20 | s14550–s14565 | 64 | 64 | 64 | 16 | 64 | **no** | 83264…84812 | 85312…85360 | +| 21 | s14874–s14889 | 32 | 64 | 32 | 16 | 16 | yes | 85376…86924 | – | +| 22 | s14958–s14973 | 64 | 64 | 64 | 16 | 64 | **no** | 87424…88972 | 89472…89520 | +| 23 | s15282–s15297 | 32 | 64 | 32 | 16 | 16 | yes | 89536…91084 | – | +| 24 | s15366–s15381 | 64 | 64 | 64 | 16 | 64 | **no** | 91584…93132 | 93632…93680 | +| 25 | s15690–s15705 | 32 | 64 | 32 | 16 | 16 | yes | 93696…95244 | – | +| 26 | s15981–s15988 | 64 | 32 | 64 | 8 | 4·4·2 = 32 | **no** | 95744…96268 | 96768…96784 | + +**Every phase whose `M/16·N/8·K/32` does not equal `mma` is one the tool also +marks `grid = band`**, and every phase that holds is marked `full`. The +mismatching rows are *not* off by a constant factor (P1 is ×9, P7 ×9, P10/12/… +×4, P26 ×4), so `M`, `N` and `K` cannot all be taken at face value for those +rows: `nA` counts distinct A *register quads*, which can be either distinct +`M`-tiles or distinct `K`-slices of the same tile, and the tool cannot tell them +apart. See §7/U1. + +**Which phases read no weight operand:** **P6 and P7**. Both take `B` from +registers that the preceding epilogue packed (E5 packs P2/P3's D for P6's A and +B; E6 packs the probabilities and the transposed P5 for P7's A and B). Their +`bo` is `None` for every mma. + +**Weight image extent as the tool measures it:** the largest resolved offset is +**96784** (s15980, 4 bytes wide) ⇒ **96788 bytes** (634 distinct slots). This +excludes the two `tid.z`-strided groups in §1.1: phase 1's B and bias are read +at `W + 12288·tid.z` / `W + 256·tid.z`, and phases 2…5's B and phase 6's bias at +`W + 18432·tid.z + 25216`. With `tid.z ∈ {0,1}` (E26 rejects `tid.z > 1` at +s16069 `setp.gt.u32 %p474, %r19008, 1`) the true image must reach at least +`18432 + 41100 = 59532`, which is inside 96788, so the two `tid.z` slices do not +extend the image beyond what the tool already sees. **(INFERENCE** — the tool +drops the `tid.z` term, so the per-window base cannot be read off it directly.) + +## 6. The plane arena (param_0 + 48) and the per-launch tables + +* `param_0+8` is read 52 times in the prologue (s67…s324) as the **input feature + plane** that builds phase 1's 9 A fragments. The index arithmetic is + `(clamp_r·ey + clamp_c)·4` style (`shl.b32 … 3`, `mad.lo.s32`, `mul.wide.u32 …, + 4`, `add.s64 …, %rd35`): the arena is a `{ex, ey}`-wide f16/byte plane read + with 4-byte elements. +* `param_0+24` is the **patch-gather source** (see §4); it is read, never written. +* `param_0+48` is the **output plane arena**: written by E25's 16 + `st.global.u32` (s15780…s15959), never read. There is no second `st.*` group + in the entry (the entry has exactly 16 `st.global` and 0 other global stores + before L38179). +* The only other `ld.param` sites are the 4 in the prologue (§1.1) and the 5 in + E26 (`[%rd459+88/96/104/112/136]`, s16191/16267/16269/16090/16185) plus + `[%rd8+48]` (s15754) and the two `param_0+40` re-reads (s15961/s15962). + +There is **no per-launch table generated into the plane arena by this kernel**: +the plane arena is only written (E25) and the tables that look like per-launch +tables (the `W + ((laneid<<2)&12) + off` blocks at 25088, 62080, 66496) all live +in the *weight image*, not the arena. See §7/U5. + +## 7. Uncharacterised + +**U1. The true `M/N/K` of the nine banded phases (P1, P7, P10, P12, …, P24, +P26).** For those rows `M/16·N/8·K/32 ≠ mma` (§5). The reason is structural +and checkable: the accumulator chains of a banded phase mix *distinct* B +operands. For P10 the four chains are + +``` +s12397 D=%r11522 A=%r11574 B=%r11473 C=bias (bo 62336) +s12399 D=%r11542 A=%r11594 B=%r11477 C=%r11522 (bo 62848) +s12401 D=%r11562 A=%r11574 B=%r11481 C=bias (bo 63360) +s12403 D=%r11582 A=%r11594 B=%r11485 C=%r11562 (bo 63872) +``` + +— the same D accumulates products with B fragments from four *different* +512-byte blocks and two *different* A quads. Under the settled weight formula +(`n = 16·tt + 8·(b>>3) + (L>>2)`, verified on enc0) those four blocks span +`n = 0…63`, so `N = 64` is supported; but then the two-mma chains must be +summing over `M` or `K`, and neither M nor K is separately readable from the +fragment structure. For P1 the same argument gives `N = 384` (48 B fragments = +24 blocks × 16 columns) while the arithmetic needs `M/16 · K/32 = 3`. +*Missing:* either a run with a weight-image dump, or the `_prep` permutation +that produces the image, or the high-level layer definition. Until then I will +not assign M/K to these rows. + +**U2. The identity of the 12288-byte score bias (P6's C).** E5 loads it as 24 +tiles × 512 bytes at `W + 18432·tid.z + 29312`. Whether it is a relative +position bias, a learned score bias, or a per-lane constant cannot be decided +from the PTX: it is an opaque blob in a permuted weight image. *Missing:* the +image's layout description (the `_prep` permutation) or the model's parameter +names. + +**U3. The identity of the per-column tables.** `W+25088…25200` (E1 gain), +`W+62080…62192` (E7), `W+62208…62320` (E9 gain), `W+66496…66608` (E10) are all +read with the same `W + ((laneid<<2)&12) + off` pattern and are 8 words per lane. +Their *role* is computable (E1/E9: multiply the inverse RMS; E7/E10: added to a +residual before the next GEMM) but their *names* are not. The GEMM biases at +`+24576`, `+64384`, `+68672`, `+72832`, `+76992`, `+81152`, `+85312`, `+89472`, +`+93632`, `+96768` are the same case. + +**U4. E1's patch-expand geometry.** The 48 `st.shared` of §3/E1 are guarded by +row/col limits of 9 and index `(row·40 + col·8 + t)·4` into four 1600-byte +sub-arrays, but they are emitted as ~400 basic blocks with 438 labels and I could +not reduce the lane→(row,col) map of the 10×10 patch to a closed form. What is +established: the four sub-arrays, the 40-word row pitch, the `t` and `t|4` +column split, the two `v2.u16` cells, and the total 6400 bytes. +*Missing:* the source-level im2col/patchify expression, or a shared-memory dump. + +**U5. Whether `param_0+8` is an input plane or a scratch table.** The prologue +reads it 52 times with 4-byte elements and never writes it, and E1 does not read +it at all (E1 reads `param_0+24`). So `+8` and `+24` are two different input +buffers; which one holds the noisy colour plane and which holds the feature +planes cannot be decided from the PTX. *Missing:* the host-side launch +arguments. + +**U6. The `tid.z` strides.** Two different per-`tid.z` strides (12288 for phase +1, 18432 for phases 2…5 + phase 6's bias, 256 for phase 1's bias, 192 for +phase 1's bias in the companion layout) appear, and no later phase carries one. +Whether this means the weight image is a concatenation of per-window sub-images +or that `tid.z` selects a batch element whose weights are interleaved cannot be +decided from the PTX alone. Consequence: the "96788 bytes" of §5 is a lower +bound for the image, not necessarily its size. + +**U7. The logical meaning of E26's final expression.** The tail computes +`out = acc·σ(v) + tex96·(1−σ(v)) + tex104` on the three channels gathered from +the 3×3 colour stencil and the two integer-coordinate textures. The PTX gives +the arithmetic exactly (§3/E26(g)) but not what model term it corresponds to. +*Missing:* the high-level source or a reference implementation. + +**U8. E12/E14/…/E24's `%f989…%f992`.** These six epilogues re-`cvt` the four +constants but never re-`mov.f32` them, so they read the registers E10 wrote +(s12414–s12425). That is only valid if the register allocator kept them live +across phases 11…23; the PTX shows no redefinition, so it is consistent, but +nothing in the file asserts the interference-freedom. *Missing:* an SSA check. + +## 8. Quick acceptance index + +| requirement | where | +|---|---| +| every epilogue named and ranged | §2, §3 (E1…E26) | +| phase-1 epilogue's patch expand + norm | §3/E1 | +| the norm (`E1`, `E9`) | §3/E1, §3/E9 — raw sum of squares + 2⁻¹³, no mean, no 1/N | +| the attention (score, softmax, P·V) | §3/E5, E6, E7; §3/E9 (region diagram) | +| the activations | §3/E10 (materialises `%f989…%f992`), E12, E14, E16, E18, E20, E22, E24 | +| the patch expand | §3/E1 (48 `st.shared`), §7/U4 | +| the final epilogue, textures at +96/+104, surface | §3/E26, §4 | +| the texture reads at +96/+104 | §3/E26(f), s16268 / s16270 | +| the skip input at +24 | §3/E1 (s2215), §4 | +| the plane-arena writes | §3/E25 (s15780…s15959), §4, §6 | +| the phase table with M/N/K checked | §5 | +| weight image extent | §5 (96788 bytes, 634 slots) | +| which phases read no weight | §5 (P6, P7) | +| uncharacterised | §7 | diff --git a/kernels/rr/rrswin_dec2.hip b/kernels/rr/rrswin_dec2.hip new file mode 100644 index 0000000..79c5e71 --- /dev/null +++ b/kernels/rr/rrswin_dec2.hip @@ -0,0 +1,347 @@ +// Native replacement for the Ray Reconstruction denoiser's third Swin decoder, +// cuda_dldn_engine_swin_dec2_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the mirror-cut frame is in place and builds/serves. Phase 1 (the +// patch-expand GEMM) is implemented; phases 2-38 and their 37 epilogues are not, +// so the four accumulators handed back to the epilogue are not yet phase 38's +// and the layer's output is wrong. +// +// The previous revision claimed phase 1 was "bit-exact against the debug +// oracle". That claim was void: its stage spliced the payload store next to +// phase 1's mma (line 1534), and E37's plane-arena scatter erases it before the +// dump -- see the measurement in swin_dec2_debug_stages.py. Every stage now +// splices after E37 and phase 1 is re-verified through that channel. +// +// The kernel is one warp per 8x8 token patch: grid (41, 24, 1), block (32, 1, 4) +// -- four waves per block, which is why the decoders' weight addressing carries a +// per-tid.z stride -- and a 144-byte parameter block. The PTX this file +// replaces is kernels/extracted/rr/0021-PREPASS_ENTRYPOINT_NAME.ptx, lines +// 1535-36892 (statements s452-s15510, 726 mma in 38 phases). +// +// kernels/rr/swin_dec2_recipe.py's recipe (make_ptx.py's per-layer hook) keeps +// NVIDIA's prologue (lines 1-1534) and its final epilogue (line 36893 to the +// end) and replaces the 726 mma and everything between them with the call +// below. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so +// tex_common.h's helpers and ZLUDA's own device functions are available. +// Compiled with -nogpuinc, so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinDec2Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinDec2Params) == 144, "parameter block"); + +enum : int +{ + kOutPlane = 48, // plane arena the epilogue reads back (arg048), also the debug arena + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// Phase 1's weight sub-image. Kernels/rr/swin_dec2_recipe.py's docstring has +// the derivation: the 24 `ld.weak.global.ca.v4.u32` of the prologue read +// W + 12288*tid.z + 16*laneid + 512*t for t = 0..23, and the 144 mma use them as +// 3 m-tiles x 12 n-tiles x 4 k-steps, so M = 48, N = 96, K = 128. +// +// A 512-byte tile is 16 columns x 32 k, and the chain of four mma that +// accumulates one output tile walks tiles 4*ng+0..3, i.e. one n-group (16 +// columns) across all four k-slices. Byte j of a lane's 16-byte slot holds +// (n, k) = (16*ng + 8*(frag&1) + g, 32*ks + 2t + (j&1) + 16*((j>>1)&1) +// with the second 8-byte half of the slot at k+8 (enc0's settled layout, the +// same one rr_layer_spec.py verifies on this family), so +// waddr1(n, k) = 12288*tid.z + 512*(4*(n>>4) + (k>>5)) + 64*(n&7) +// + 8*((n>>3)&1) + 16*((k>>1)&3) + 4*((k>>3)&1) +// + 2*((k>>4)&1) + (k&1) +// which is enc0's waddr() with the tile index widened from (n>>4) to +// 4*(n>>4) + (k>>5) and the per-window base added. (VERIFIED on all 96*128 of a +// phase-1 tile's (n, k) pairs against the oracle's own B fragment registers, +// debug stage p1.) +DEVF uint32_t waddr1(int tidz, int n, int k) +{ + return (uint32_t)(12288 * tidz) + 512u * (uint32_t)(4 * (n >> 4) + (k >> 5)) + + 64u * (uint32_t)(n & 7) + 8u * (uint32_t)((n >> 3) & 1) + + 16u * (uint32_t)((k >> 1) & 3) + 4u * (uint32_t)((k >> 3) & 1) + + 2u * (uint32_t)((k >> 4) & 1) + (uint32_t)(k & 1); +} + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// warp butterfly over the four lanes that hold a row's 32 k values (laneid ^ 1 +// and laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// Phase 1: M = 48 (three m-tiles of 16 rows), N = 96 (twelve n-tiles of eight +// columns), K = 128 (four k-slices of 32). +// +// A lane's twelve A fragments are the twelve m16n8k32 .f16.e4m3 operand quads +// in the order the 144 mma first use them: m-tile 0's four k-slices +// (as1[0..15]), m-tile 1's (as1[16..31]), m-tile 2's (as1[32..47]). Within a +// fragment the hardware order is (enc0's, verified on this family): +// reg 0 -> row g, k = 2t + (j&1) + 16*((j>>1)&1) +// reg 1 -> row g+8, same k +// reg 2 -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// reg 3 -> row g+8, same k +// with g = laneid>>2, t = laneid&3 and j the byte index 0..3, so the four lanes +// that differ in t hold four disjoint eighths of the slice's 32 k and the two +// butterfly steps bring the other three in. +// +// The B operand is read from the weight image for the lane's own two columns of +// each n-tile. The four mma of one output tile are a chain: each rounds its f32 +// accumulator to f16 before the next adds to it, which is why they are four +// mma and not one -- the first takes the per-n-tile bias seed from the weight +// image at 49152 + 192*tid.z + 16*ntile + 4*t, the rest take the previous D. +// +// Every e4m3 product is exact and a 32-term k slice sums exactly in f32, so +// rounding once per slice to f16 reproduces the translated mma bit for bit. +// +// d is [n-tile][row half], each entry the packed f16 pair for columns 2t, 2t+1; +// hist, when non-null, receives the 144 chain results in mma order, i.e. +// index 48*m-tile + 8*(n-tile>>1) + (n-tile&1) + 2*k-slice +// which is exactly where the PTX's k-th mma of that chain writes its D. +DEVF void gemm_p1(const uint32_t* as1, const uint8_t* w, const uint32_t* seeds, + int tidz, int t, uint32_t d[12][2], uint32_t* hist) +{ +#pragma unroll + for (int mt = 0; mt < 3; ++mt) { +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + // the lane's two columns of this n-tile: 16 columns per weight tile, + // the n-tile's parity selecting its 8-column half + const int ncol = 16 * (nt >> 1) + 8 * (nt & 1) + 2 * t; + const uint32_t bias = seeds[nt]; + half_t prev[2][2]; +#pragma unroll + for (int ks = 0; ks < 4; ++ks) { + const uint32_t* as = as1 + 16 * mt + 4 * ks; + float bv[2][32]; +#pragma unroll + for (int c = 0; c < 2; ++c) { +#pragma unroll + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr1(tidz, ncol + c, 32 * ks + k)]); + } + } + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; +#pragma unroll + for (int reg = 0; reg < 2; ++reg) { +#pragma unroll + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + const uint32_t p0 = as[2 * reg + row]; + const uint32_t p[4] = {p0, bfly1_bits(p0), bfly2_bits(p0), + bfly1_bits(bfly2_bits(p0))}; +#pragma unroll + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); +#pragma unroll + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } +#pragma unroll + for (int row = 0; row < 2; ++row) { + const float c0 = ks == 0 ? acc[row][0] + h2f(bias) + : acc[row][0] + (float)prev[row][0]; + const float c1 = ks == 0 ? acc[row][1] + h2f(bias >> 16) + : acc[row][1] + (float)prev[row][1]; + prev[row][0] = (half_t)c0; + prev[row][1] = (half_t)c1; + } + if (hist != nullptr) { + const int i = 48 * mt + 8 * (nt >> 1) + (nt & 1) + 2 * ks; + hist[2 * i] = pair_of(prev[0][0], prev[0][1]); + hist[2 * i + 1] = pair_of(prev[1][0], prev[1][1]); + } + } + d[nt][0] = pair_of(prev[0][0], prev[0][1]); + d[nt][1] = pair_of(prev[1][0], prev[1][1]); + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_dec2_debug_stages.py: with +// D4R_RRSWIN_DEBUG=p1 (a1, or none) make_ptx.py keeps NVIDIA's own body and +// splices in a store of that stage's registers at param_0+48 + 46,000,000 + +// block*slot + lane*n*4, which the kernel never otherwise writes; the launch +// dump then holds the translated values for a block/lane. Built with +// -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this +// body stores the same registers of its own phase n in the same order, so the +// two dumps compare byte for byte. debug_store() mirrors make_ptx.py's shared +// swin_debug_block() exactly, including its ctaid.y*161 block numbering. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif +// The payload base. make_ptx.py's swin_debug_block() reads the same value from +// D4R_RRSWIN_DEBUG_BASE, so both sides of a comparison store at the same place. +// Measured for dec2 (D4R_CUDA_REPLAY_DUMP capture): param_0+48 is byte 60,293,120 +// of the 65,945,600-byte block the bridge dumps as arg048's allocation, so the +// arena is 5,652,480 bytes and the default 46,000,000 of enc0 is past its end +// (the store faults). 0 leaves room for every stage's 41*slot payload. +// The stage tables splice after E37 because E37 rewrites the whole arena: a +// pre-launch replay capture diffed against the post-launch reference shows +// 5,564,929 of 5,652,480 arena bytes changed, so a payload written next to a +// phase's mma is erased before the dump. This body therefore stores at the very +// end of the entry, which is after its own E37. +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 0 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 161u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kOutPlane); + // the oracle's slot, make_ptx.py's swin_debug_slot: 32 lanes x n x 4 bytes, + // at least 8192, rounded up to a power of two (the oracle's splice forms + // block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + (uint64_t)D4R_RRSWIN_DEBUG_BASE + + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. Phase 1's twelve A fragments arrive as 48 b32 in the order the +// 144 mma first use them, then its twelve bias seeds (%r1597 %r1607 %r1677 +// ... %r2007, read from the weight image at +49152..+49328 with the per-tid.z +// stride 192), the weight image, the parameter block and the shared scratch. +// +// The four accumulators the epilogue reads cross the cut through shared memory, +// not `call.uni`'s return parameters: ZLUDA lowers those to the function's LLVM +// return type, so there is no .param-space object and no pointer is formed -- the +// callee reads 0x0 in all four slots, and a 4 x i32 C++ struct return is an sret +// pointer, a different LLVM signature that will not link. `scratch` is the base +// of the entry's .shared array (9600 bytes), which the epilogue re-stages before +// it reads, so the body is free to use it as scratch. +extern "C" __attribute__((device)) void d4r_swin_dec2( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t a24, uint32_t a25, uint32_t a26, uint32_t a27, + uint32_t a28, uint32_t a29, uint32_t a30, uint32_t a31, uint32_t a32, uint32_t a33, uint32_t a34, + uint32_t a35, uint32_t a36, uint32_t a37, uint32_t a38, uint32_t a39, uint32_t a40, uint32_t a41, + uint32_t a42, uint32_t a43, uint32_t a44, uint32_t a45, uint32_t a46, uint32_t a47, + uint32_t s0, uint32_t s1, uint32_t s2, uint32_t s3, uint32_t s4, uint32_t s5, + uint32_t s6, uint32_t s7, uint32_t s8, uint32_t s9, uint32_t s10, uint32_t s11, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[48] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, + a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, + a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, a47}; + const uint32_t seeds[12] = {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11}; + const int tidz = (int)__builtin_amdgcn_workitem_id_z(); + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + + // ---- phase 1 ----------------------------------------------------------- + uint32_t d1[12][2]; + uint32_t hist1[288]; +#if D4R_RRSWIN_DEBUG_STAGE == 2 + gemm_p1(as1, w, seeds, tidz, t, d1, hist1); +#else + gemm_p1(as1, w, seeds, tidz, t, d1, nullptr); +#endif + + // ---- handing the accumulators back ------------------------------------ + // Phases 2-38 and their epilogues are not implemented yet. Until they are, + // fill the four slots with lane-distinct values so the read-back path is + // observable without producing wild magnitudes. + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + 4 * lane_id(); + for (int i = 0; i < 4; ++i) { + out[i] = (uint32_t)lane_id() + 32u * (uint32_t)i; + } + + // ---- debug store ------------------------------------------------------- + // Last, so it follows this body's own arena scatter: E37 rewrites the whole + // plane arena, and an earlier store would be erased before the dump. The + // oracle splices its block at the same point in its entry (after E37). +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + uint32_t regs[64]; + regs[0] = *(const uint32_t*)(w + 212736 + ((lane_id() << 2) & 12)); + for (int i = 0; i < 48; ++i) { + regs[1 + i] = as1[i]; + } + for (int i = 0; i < 12; ++i) { + regs[49 + i] = seeds[i]; + } + for (int i = 61; i < 64; ++i) { + regs[i] = regs[0]; // the sentinel padding both sides store + } + debug_store(prm, regs, 64); + } +#elif D4R_RRSWIN_DEBUG_STAGE == 2 + { + // %r19329 (the leading sentinel make_ptx's window check needs) then the + // 288 D registers of phase 1's 144 mma in statement order + uint32_t regs[292]; + regs[0] = *(const uint32_t*)(w + 212736 + ((lane_id() << 2) & 12)); + for (int i = 0; i < 288; ++i) { + regs[1 + i] = hist1[i]; + } + for (int i = 289; i < 292; ++i) { + regs[i] = regs[0]; // the sentinel padding both sides store + } + debug_store(prm, regs, 292); + } +#endif +} \ No newline at end of file diff --git a/kernels/rr/rrswin_dec2_epilogues.md b/kernels/rr/rrswin_dec2_epilogues.md new file mode 100644 index 0000000..5f2e0f3 --- /dev/null +++ b/kernels/rr/rrswin_dec2_epilogues.md @@ -0,0 +1,916 @@ +# `cuda_dldn_engine_swin_dec2_kernel` — the epilogues of phases 1…38 + +Companion to `kernels/rr/rr_layer_spec.py dec2`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0021-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec2_kernel` (15796 statements). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and + the next phase's first `mma`. Because phase 1 is the first GEMM, the prologue + (s1–s451) doubles as phase 1's prelude and is described here too. +* `W` denotes the prepared weight image: `ld.param.u64 %rd1, + [cuda_dldn_engine_swin_dec2_kernel_param_0+40]` (s7, `L1035`) and + `cvta.to.global.u64 %rd32, %rd1` (s8, `L1036`). Every + `ld.weak.global.ca.v4.u32` reads `W + 16*laneid + imm`. +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same + cols)`, `g = laneid>>2`, `t = laneid&3`. +* Anything I could not pin down from the PTX is in §7 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `param_0` | `mov.b64 %rd7, …_param_0` | s1, L1018 | +| `W` (weight image) | `ld.param.u64 %rd1, [param_0+40]` → `cvta… %rd32, %rd1` | s7/s8, L1035–L1036 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r2147, %r2148}, [param_0+0]` | s13, L1041 | +| `%r7 = 8·ex`, `%r8 = ey·8·ex` | `shl.b32 %r7, %r2147, 3` / `mul.lo.s32 %r8, %r2148, %r7` | s14/s15, L1042–L1043 | +| block origins `%r1`, `%r2` | `sub.s32 %r1, %r2142, %r2143` / `sub.s32 %r2, %r2146, %r2144` | s6/s12, L1034/L1040 | +| `%rd33` = `param_0+8` | `ld.param.u64 %rd33, [param_0+8]` | s28, L1056 | +| **texture / skip input** | `ld.param.u64 %rd2, [%rd7+24]` = `param_0+24` | s2288, L4638 | +| **output plane arena** | `ld.param.u64 %rd571, [%rd7+48]` = `param_0+48` → `cvta… %rd4, %rd571` | s15333/s15334, L36645–L36646 | +| block-origin table | `ld.param.v2.u16 {%rs264, %rs265}, [param_0+80]` | s4, L1032 | +| window index `tid.z` | `mov.u32 %r2350, %tid.z` | s378, L1408 | +| shared arena | `.shared .align 4 .b8 _ZZ33…dec2_kernel…E4smem[9600]` | L1027 (declaration; not a statement) | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, W, %rd` | every load block, e.g. s11444–s11445, L24247–L24248 | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd32, %rd` = `W + ((laneid·4)&12)` | e.g. s12456–s12460, L27063–L27068 | + +The last row matters: the `ld.global.v2.u16` / `ld.global.u32` table loads in an +epilogue read `W + ((laneid<<2)&12) + off`, i.e. **the same 16-byte slot is read +by the four lanes with equal `laneid&3`, and consecutive loads pick consecutive +4-byte words inside one 64-byte record** — so those tables are indexed by +column, not by row. + +Two per-`tid.z` strides exist, both in phase 1's prelude and nowhere else: + +| group | base | statements | +|---|---|---| +| phase 1's B | `W + 12288·tid.z + 16·laneid` | s379–s384, L1409–L1416 | +| phase 1's C bias | `W + 192·tid.z + ((laneid·4)&12) + 49152…49328` | s432–s439, L1512–L1521 | + +`%r2350·12288` (s379) is the only `×12288` in the file and `%r2350·96 → ×2` +(s432/s433) the only `×192`, so no other phase's loads carry a window term. + +### 1.2 Constants that survive between epilogues + +| register | first definition | f32/f64 literal | value used (after the `cvt` to f16) | +|---|---|---|---| +| `%f476` | s7488 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 | +| `%fd383` | s7492 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | f16 `0xB873` | +| `%fd385` | s7497 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | f16 `0x3873` | +| `%f478` | s7503 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | f16 `0x3B6B` | +| `%f480` | s7508 `mov.f32 %f480, 0f3FB00000` | 1.375 | f16 `0x3D80` | +| `%fd1` | s6132 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | f16 `0x0800` = 0.0001220703125 | +| `%f861` | s12301 `mov.f32 %f861, 0f3ED306EB` | 0.4121621549129486 | f16 `0x3698` = 0.412109375 | +| `%f862` | s12304 `mov.f32 %f862, 0f3DA60DD6` | 0.0810810774564743 | f16 `0x2D30` = 0.0810546875 | +| `%f863` | s12307 `mov.f32 %f863, 0f3F000000` | 0.5 | f16 `0x3800` | +| `%f864` | s12310 `mov.f32 %f864, 0f40000000` | 2.0 | f16 `0x4000` | + +`%f861…%f864` are materialised **inside E14** (s12301–s12312) and only re-`cvt` +by E16, E18, E20, …, E36 (`s12642 cvt.rn.f16.f32 low, %f861`, …). `%fd1` is +defined once, in E1 (s6132), and only re-`cvt` by E13. + +Also live across the region, as in the sibling kernel: `%r5908 = 1` +(s5595, `L8140`) and `%r5919 = -1` (s6074, `L9586`) supply the butterfly delta +and the membermask of every `shfl.sync.bfly.b32` in the epilogues +(`s6075 shfl.sync.bfly.b32 %r5842,%r5838,%r5908,%r5845,%r5919`); the +group/width operand is per-instruction. + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — its inverse, the *unpack*, used only when a shared + tile that was stored e4m3-packed is read back (E1: 96 of them, s5594–s5690, + L8139–L8437). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (round each step through f16). + +## 2. Summary + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s596–s7088 | 6493 | patch expand into shared + per-column RMS norm + gain + restage | +| E2 | s7113–s7119 | 7 | next-B weight loads (P3) | +| E3 | s7144–s7150 | 7 | next-B weight loads (P4) | +| E4 | s7175–s7181 | 7 | next-B weight loads (P5) | +| E5 | s7206–s7212 | 7 | next-B weight loads (P6) | +| E6 | s7237–s7243 | 7 | next-B weight loads (P7) | +| E7 | s7268–s7438 | 171 | score-bias C-seed loads (24×512 B) + 80 packs → P8's A and B | +| E8 | s7487–s11329 | 3843 | cubic-exponent softmax, V transpose, pack | +| E9 | s11378–s11546 | 169 | pack P9's D → shared, per-column table → P10's C, next B | +| E10 | s11559–s11577 | 19 | 1 shared A fragment + 6 next-B loads (P11) | +| E11 | s11590–s11608 | 19 | 1 shared A fragment + 6 next-B loads (P12) | +| E12 | s11621–s11639 | 19 | 1 shared A fragment + 6 next-B loads (P13) | +| E13 | s11652–s12287 | 636 | RMS norm of P13's D + gain, packs → P14's A and P16's A, next B/C | +| E14 | s12300–s12556 | 257 | clamped-cubic activation of P14's D, per-column table + residual → P15's C | +| E15 | s12569–s12628 | 60 | 24 packs → P16's A, next B, P16's C bias | +| E16 | s12641–s12804 | 164 | clamped-cubic activation of P16's D → P17's A, next B | +| E17 | s12817–s12876 | 60 | 24 packs → P18's A, next B, P18's C bias | +| E18 | s12889–s13052 | 164 | activation of P18's D → P19's A, next B | +| E19 | s13065–s13124 | 60 | 24 packs → P20's A, next B, P20's C bias | +| E20 | s13137–s13300 | 164 | activation of P20's D → P21's A, next B | +| E21 | s13313–s13372 | 60 | 24 packs → P22's A, next B, P22's C bias | +| E22 | s13385–s13548 | 164 | activation of P22's D → P23's A, next B | +| E23 | s13561–s13620 | 60 | 24 packs → P24's A, next B, P24's C bias | +| E24 | s13633–s13796 | 164 | activation of P24's D → P25's A, next B | +| E25 | s13809–s13868 | 60 | 24 packs → P26's A, next B, P26's C bias | +| E26 | s13881–s14044 | 164 | activation of P26's D → P27's A, next B | +| E27 | s14057–s14116 | 60 | 24 packs → P28's A, next B, P28's C bias | +| E28 | s14129–s14292 | 164 | activation of P28's D → P29's A, next B | +| E29 | s14305–s14364 | 60 | 24 packs → P30's A, next B, P30's C bias | +| E30 | s14377–s14540 | 164 | activation of P30's D → P31's A, next B | +| E31 | s14553–s14612 | 60 | 24 packs → P32's A, next B, P32's C bias | +| E32 | s14625–s14788 | 164 | activation of P32's D → P33's A, next B | +| E33 | s14801–s14860 | 60 | 24 packs → P34's A, next B, P34's C bias | +| E34 | s14873–s15036 | 164 | activation of P34's D → P35's A, next B | +| E35 | s15049–s15108 | 60 | 24 packs → P36's A, next B, P36's C bias | +| E36 | s15121–s15284 | 164 | activation of P36's D → P37's A, next B | +| E37 | s15297–s15504 | 208 | pack → 12 guarded plane-arena scatter → B/C for P38 | +| E38 | s15511–s15796 | 286 | 4 D stores → shared, row max, softmax, 9+2 texture reads, surface store | + +--- + +## 3. The epilogues + +### E1 — s596–s7088: patch expand, RMS norm, gain, restage + +6493 statements; op histogram (top): 1103 `add.s32`, 477 `shl.b32`, 446 +`mov.b32`, 413 `$label`, 409 `sub.s32`, 355 `min.u32`, 288 `mul.f16`, 120 +`cvt.rn.satfinite.e4m3x2.f16x2`, 96 `cvt.rn.f16x2.e4m3x2`, 96 +`rsqrt.approx.ftz.f32`, 42 `st.shared.*` (34 `u32` + 2 `v2.u16` + 6 `v4.u32`), +42 `ld.shared.*` (24 `v2.u16` + 18 `v4.u32`), 36 `ld.global.v2.u16`, 8 +`shfl.sync.bfly.b32`, 1 `ld.param`, 2 `ld.weak…`. + +Sub-sections (bounded by the first/last statement of each op): + +| range | what | +|---|---| +| s596–s702 | the head packs of phase 1's D (72 `cvt.rn.satfinite…`), → `%r9…%r41` | +| s716–s1478 | per-lane index arithmetic + the 36 guarded patch stores (34 `st.shared.u32` s770–s1460 + 2 `st.shared.v2.u16` s743/s1478); 1st `bar.sync` at s1480 | +| s1524–s2287 | 24 `ld.shared.v2.u16` read back of the packed patch | +| s2288 | `ld.param.u64 %rd2, [%rd7+24]`: **the patch-gather buffer** | +| s2444–s5593 | 24 clamped `ld.global.v2.u16` gathered from that buffer | +| s5594–s5690 | 96 `cvt.rn.f16x2.e4m3x2` unpacks of the read-back patch | +| s5693–s6276 | the sum trees (196 `add.f16` exact + 52 `add.f16x2`) | +| s6132 | the 2⁻¹³ constant `%fd1` (s6132 `mov.f64 %fd1, 0d3F20000000000000`) | +| s6075–s6128 | the 8 `shfl.sync.bfly.b32` (first at s6075) | +| s6282–s6659 | 96 `rsqrt.approx.ftz.f32`, each `cvt.f32.f16 → rsqrt → cvt.rn.f16.f32` | +| s6668–s6679 | **gain loads** `W + ((laneid·4)&12) + {49920…50096}` (12 `ld.global.v2.u16`) | +| s5693–s6966 | the 288 `mul.f16` (two groups: `inv · gain` then `x · (inv·gain)`) | +| s7008–s7054 | 24 packs → the 6 `st.shared.v4.u32` at s7008/7021/7034/7044/7049/7054 | +| s7059–s7082 | `bar.sync` (s7059) + 18 `ld.shared.v4.u32` (s7064–s7082) → phases 2…7's A | +| s7083–s7088 | 2 `ld.weak` (s7086/s7088) → **phase 2's B** | + +Evidence for the patch scatter (36 stores): + +``` +s743 L2836: st.shared.v2.u16 [%r2373], {%rs192, %rs193} +s770 L2865: st.shared.u32 [%r2386], %r9 +s800 L2897: st.shared.u32 [%r2403], %r10 +s1478 L3641: st.shared.v2.u16 [%r2787], {%rs262, %rs263} +s7008 L11717: st.shared.v4.u32 [%r6091], {%r6095, %r6094, %r6093, %r6092} +s7044 L11788: st.shared.v4.u32 [%r6110+6144], {%r6114, %r6113, %r6112, %r6111} +s7054 L11798: st.shared.v4.u32 [%r6110+7168], {%r6122, %r6121, %r6120, %r6119} +``` + +Each patch store is guarded exactly as in the sibling kernel +(`setp.gt.u32 %p…, %r…, 9` / `or.pred` / `@%p bra …`; the same +`(row·40 + col·8 + t)·4` index form — cf. `rrswin_dec1_epilogues.md` §3/E1, +which carries the same 400-block emitter). The second staging area is at +`[%r6091]`, `[%r6091+512]`, `[%r6091+1024]`, `[%r6110+6144]`, +`[%r6110+6656]`, `[%r6110+7168]`, where `%r6091 = smem + tid.z·2048` +(s6994 `shl.b32 … %r2350, 11`) and `%r6110 = smem + tid.z·3072` (s7040). + +The norm: + +``` +s6132 L9664: mov.f64 %fd1, 0d3F20000000000000 // 2^-13 +s5693 L8430: add.f16 %rs456,%rs457,%rs458 +s6282 L10110: rsqrt.approx.ftz.f32 fl, fl +s6668 L10735: ld.global.v2.u16 {%rs1959, %rs1960}, [%rd247+49936] +s6681 L10749: mul.f16 %rs…, %rs…, %rs… // inv * gain +``` + +**There is no mean subtraction and no `1/N`.** The accumulated quantity is the +raw sum of squares of the 3 patch channels plus the constant 2⁻¹³, and the norm +is applied per *column* (the gain is read at `W + ((laneid<<2)&12) + off`, so it +is constant across rows). + +**Inputs:** phase 1's D (`%r593…%r826`, 12 fragments — phase 1 has `nA = 12`), +`W`, `param_0+8`, `param_0+24`, `%r1/%r2/%r7/%r8/%r2147/%r2148`, `%r2350` +(`tid.z`). +**Outputs (live past s7088):** the patch-expand `st.shared` regions, the 18 +`ld.shared.v4.u32` A fragments `%r18995…%r19066`, phase 2's B +`%r6125…%r6132`, the 4 constants of §1.2 (`%fd1`, `%f861…%f864` are *not* yet +defined here). + +### E2…E6 — s7113–s7243: next-B loads + +Five 7-statement blocks of identical shape: + +``` +s7113 L12005: mov.u32 %r6373, %laneid +s7114 L12007: mul.wide.u32 %rd…, %r6373, 16 +s7115 L12008: add.s64 %rd…, %rd2?, %rd… +s7117 L12017: ld.weak.global.ca.v4.u32 { %r6374,…%r6377},[%rd250] +s7119 L12021: ld.weak.global.ca.v4.u32 { %r6378,…%r6381},[%rd251] +``` + +| epilogue | weight block | destination phase | +|---|---|---| +| E2 | 50112…50636 | P3's B | +| E3 | 53184…53708 | P4's B | +| E4 | 51136…51660 | P5's B | +| E5 | 54208…54732 | P6's B | +| E6 | 52160…52684 | P7's B | + +The weight sub-image is laid out **P2, P4, P6, P3, P5, P7** (blocks of 1024 +bytes at `W + 50112 + 1024·k`), not in phase order. + +### E7 — s7268–s7438: score-bias C-seed loads + packs → P8's A and B + +171 statements, no `ld.global` outside the two groups below. + +* **24 loads** `W + 16·laneid + 56256 + 512·i`, `i = 0…23`, at s7272…s7318 + (L12922…L13014) into `%r7619…%r7714`; the last block's `add.s64` is + `s7317 add.s64 %rd283, %rd467, 17920`. Byte block + `[56256, 68544)` = 24 × 512 = 12288 bytes — **phase 8's C score-bias seed** + (the phase table prints the last *slot* offset, 68044). +* **80 packs / 40 b32**, s7319–s7438, whose sources are registers written by + **phases 3…7's mma** (`%r7129/%r7149/…`, `%r7229/…`, `%r7360…`). The two + destinations are `%r8161…%r8272` (**phase 8's B**) and `%r7907…%r8030` + (**phase 8's A**), e.g. + +``` +s7320 L13020: cvt.rn.satfinite.e4m3x2.f16x2 %rs1984, %r7149 +s7321 L13022: mov.b32 %r8161, {%rs1983, %rs1984} +s7391 L13185: cvt.rn.satfinite.e4m3x2.f16x2 %rs2032, %r7149 +s7393 L13190: mov.b32 %r7907, {%rs2031, %rs2032} +``` + +`s7439` then consumes them: `mma … {A=%r7907,%r7908,%r7909,%r7910}, +{B=%r8161,%r8162}, {C=%r7619,%r7620}`. `%r7149` is phase 3's first D +(s7089–s7112) and `%r7129`/`%r7360` likewise belong to phases 3/4/6/7, so both +of phase 8's operands are packs of the six preceding projections. + +### E8 — s7487–s11329: cubic-exponent softmax, V transpose, pack + +**Byte-identical in kind to `cuda_dldn_engine_swin_enc0_kernel`'s E5** (see +`rrswin_enc0_epilogues.md` §3/E5): 1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 +`cvt.rn.f16.f64`, 192 each of `fma.rn.f16x2` / `cvt.f32.f16` / +`rcp.approx.ftz.f32` / `mul.f16`, 144 packs, 48 `movmatrix`, 16 +`shfl.sync.bfly.b32`, 96 each of `max/min/neg/abs.f16x2`. + +Sub-sections: + +| range | what | +|---|---| +| s7488–s7513 | the 5 constants (§1.2 of the sibling file): s7488 `0f3C8CCB50`, s7492/s7497 the f64 clamps, s7503/s7508 the cubic pair | +| s7514–s9604 | 96 per-element groups (scale, clamp, cubic, `and.b32 …,2145419232`) | +| s9605–s9690 | in-lane partial sums (`add.f16x2`) | +| s9691–s9820 | 16 `shfl.sync.bfly` → 8 row sums | +| s9821–s10582 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s10583–s11065 | 192 `mul.f16` → 96 probabilities | +| s11066–s11113 | 48 `movmatrix.sync.trans.aligned.m8n8.b16` of **phase 7's** D | +| s11114–s11328 | 144 packs | + +Evidence: + +``` +s7514 L13706: and.b32 %r…, %r…, 2145419232 // 0x7FE07FE0 +s9691 L20503: shfl.sync.bfly.b32 %r10441,%r10437,%r5908,%r10444,%r5919 +s9821 L20829: rcp.approx.ftz.f32 fl, fl +s11066 L23128: movmatrix.sync.trans.aligned.m8n8.b16 %r10801, %r7378 +s11114 L23272: cvt.rn.satfinite.e4m3x2.f16x2 %rs3432, %r10809 +``` + +`%r10801` is the first movmatrix result and its source `%r7378` is phase 7's +first D (s7244–s7267); the movmatrix sources run over phase 7's 48 D registers. +The transposed results become **phase 9's B** (`%r11407 ← mov.b32 +{%rs3431,%rs3432}` at s11116 after the pack at s11114), and the probability packs +(`%r11113 ← mov.b32 {%rs3479,%rs3480}` at s11188) become **phase 9's A**. + +The per-element function is the same cubic-exponent approximation as enc0's E5 +(no row maximum, no bias add): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +u = f16(1.375 + m*(0.92724609375 - m*m)) +expval = f16 from bits ((u_bits << 5) & 0x7FE07FE0) +``` + +**Memory:** none (0 `ld.*`, 0 `st.*` in 3843 statements). + +### E9 — s11378–s11546: pack P9's D → shared, per-column table → P10's C + +169 statements: 32 packs, 8 `add.f16`, 6 `ld.weak`, 12 `ld.global.v2.u16`, +4 `st.shared.v4.u32`, 1 `ld.shared.v4.u32`. + +``` +s11378 L24111: bar.sync 0 +s11384 L24120: cvt.rn.satfinite.e4m3x2.f16x2 %rs3576, %r11141 +s11396 L24147: st.shared.v4.u32 [%r19198], {%r19202, %r19201, %r19200, %r19199} +s11435 L24234: st.shared.v4.u32 [%r19198+1536], {%r19214, %r19213, %r19212, %r19211} +s11436 L24235: bar.sync 0 +s11442 L24243: ld.shared.v4.u32 {%r19219,…%r19222}, [%r19218] +s11446 L24249: add.s64 %rd284, %rd469, 68544 +s11451 L24259: add.s64 %rd286, %rd469, 69568 +s11463 L24280: ld.global.v2.u16 {%rs4886, %rs4887}, [%rd473+136144] +s11475 L24293: add.f16 %rs3610,%rs4909,%rs459 +s11477 L24300: mov.b32 %r11589, {%rs3607, %rs3610} +``` + +* **32 packs of phase 9's D** → 16 b32 → four `st.shared.v4.u32` at + `[%r19198 + {0,512,1024,1536}]`; the `bar.sync` pair makes them visible, then + **one `ld.shared.v4.u32` gives the first A fragment of phase 10**. +* **6 `ld.weak` at `W + 16·laneid + {68544, 69056, 69568, 70080, 70592, 71104}`** + → phase 10's B. +* **12 `ld.global.v2.u16` at `W + ((laneid·4)&12) + {136128…136304}`** — a + per-column vector (12 words per lane = 96 columns). +* **48 `add.f16`** adding that vector to register pairs, producing the 24 + registers `%r11589 %r11590 %r11599 %r11600 …` = **phase 10's C** + (confirmed at s11547: `C = {%r11589, %r11590}`). + +**Which registers the table is added to is ambiguous in this file.** The +operands are `%rs456/%rs459` and their 22 siblings, and the *only* textual +definition of `%rs456/%rs459` is at `s5693/s5694` (L8430/L8434) inside **E1** +(the E1 sum-of-squares tree); nothing between s5694 and s11475 writes them. So +either E9's residual is genuinely carried from E1, or the printed PTX reuses a +register name across two disjoint live ranges without a rename. See §7/U1. + +### E10/E11/E12 — s11559–s11639: one shared A fragment + next-B loads + +Three 19-statement blocks: + +``` +s11562 L24597: ld.shared.v4.u32 {%r19226,…%r19229}, [%r19225+2048] +s11566 L24603: add.s64 %rd290, %rd475, 90048 +s11571 L24613: add.s64 %rd292, %rd475, 91072 +``` + +| epilogue | shared A offset | weight block | destination phase | +|---|---|---|---| +| E10 | `+2048` | 90048…92620 | P11's A, B | +| E11 | `+4096` | 111552…114124 | P12's A, B | +| E12 | `+6144` | 133056…135628 | P13's A, B | + +Each takes its single A fragment from the same shared staging region E9 wrote +(offsets 2048/4096/6144 relative to `%r19216`) and reads 6 consecutive 512-byte +weight fragments. All three phases take `C = 0`. + +### E13 — s11652–s12287: RMS norm of P13's D + gain + +636 statements; 182 `mov.b32`, 144 `mul.f16`, 76 `add.f16`, 26 `add.f16x2`, +48 `rsqrt.approx.ftz.f32`, 4 `shfl.sync.bfly`, 24 packs, 12 `ld.global.v2.u16`. + +| range | op | +|---|---| +| s11654–s11749 | unpack P13's D halves (`%r12019…`) and square them (48 `mul.f16`, s11655–s11749) | +| s11750–s11804 | in-lane `add.f16x2` partial sums | +| s11776–s11794 | 4 `shfl.sync.bfly.b32` | +| s11875–s11878 | `add.f16` of the halves, then `+ 2⁻¹³` (`%fd1`, defined at s6132) | +| s11883–s12068 | 48 `rsqrt.approx.ftz.f32` | +| s12072–s12083 | **gain loads** `W + ((laneid·4)&12) + {136336, 136352, …, 136496, 136320}` (12 `ld.global.v2.u16`) | +| s12085–s12226 | 96 `mul.f16` — `inv · gain` then `x · (inv·gain)` | +| s12231–s12242 | next-B loads `W + {136512, 137024, 137536, 138048, 138560, 139072}` → phase 14's B | +| s12248–s12251 | `ld.global.u32` at `W + ((laneid·4)&12) + {139584, 139600, 139616, 139632}` → **phase 14's C bias** | +| s12252–s12287 | 24 packs → `%r12414…%r12457`, **phase 14's A** | + +At s12157/s12158 the same epilogue also emits a *second* scaled copy of P13's D: + +``` +s12157 L26127: mul.f16 %rs4190,%rs4360,%rs4046 +s12158 L26130: mov.b32 %r18435, {%rs4190, %rs4193} +``` + +`%rs4360` is the unpack of P13's first D (s11654). The 24 registers +`%r18435…%r18458` are re-used by **every** even phase's A pack (E15 s12594, +E17 s12842, E19 …, and E37 s15297's neighbours), i.e. **phases 14, 16, 18, …, +P36 all share one A operand** derived from phase 13. + +### E14 — s12300–s12556: activation of P14's D, table + residual → P15's C + +257 statements. Three things happen: + +1. **s12301–s12440: the clamped-cubic activation** on the 8 f16x2 registers + `%r12382 %r12392 %r12383 %r12393 %r12442 %r12452 %r12443 %r12453` (phase 14's + D). This is the epilogue that materialises `%f861…%f864` (s12301–s12312): + +``` +s12313 L26578: neg.f16x2 %r12467,%r12466 +s12314 L26582: max.f16x2 %r12469,%r12382,%r12467 +s12315 L26586: min.f16x2 %r12472,%r12469,%r12466 +s12316 L26590: abs.f16x2 %r12475,%r12472 +s12317 L26594: mul.f16x2 %r12477,%r12464,%r12475 +s12318 L26598: sub.f16x2 %r12480,%r12463,%r12477 +s12319 L26602: mul.f16x2 %r12483,%r12472,%r12480 +s12320 L26606: add.f16x2 %r12486,%r12465,%r12483 +s12321 L26610: mul.f16x2 %r12489,%r12382,%r12486 +``` + + Per element: `y = clamp(x,−2,+2)`, `g = 0.5 + y·(0.412109375 − 0.0810546875·|y|)`, + `out = x·g` — the same cubic ramp as the sibling kernel's E10. **Reproduce + the formula, not SiLU/GELU.** +2. **s12441–s12472: next-B and table loads.** Six `ld.weak` at + `W + {139648, 140160, 140672, 141184, 141696, 142208}` → phase 15's B; and + 12 `ld.global.v2.u16` at `W + ((laneid·4)&12) + {142720…142896}`. +3. **s12473–s12556: the residual/table add and the packs.** 48 `add.f16` + (`add.f16 %rs4361,%rs4957,%rs4363` at s12473) combine the table with the 24 + registers whose halves come from `s11654 L24951: mov.b32 {%rs4360, %rs4363}, + %r12019` — **phase 13's D**. The 24 results `%r12737…%r12848` are + **phase 15's C**; the 8 packs at s12545–s12556 give **phase 15's A**. + +So phase 15 computes `D15 = act(D14)·B15 + (D13 + table@142720)`. + +### E15 — s12569–s12628: packs of the shared A, next B, P16's C bias + +60 statements: + +``` +s12572 L27414: add.s64 %rd320, %rd494, 142912 +s12589 L27445: ld.global.u32 %r12908, [%rd497+145984] +s12593 L27450: cvt.rn.satfinite.e4m3x2.f16x2 %rs4511, %r18436 +s12594 L27453: cvt.rn.satfinite.e4m3x2.f16x2 %rs4510, %r18435 +``` + +* six `ld.weak` at `W + {142912, 143424, 143936, 144448, 144960, 145472}` + → phase 16's B; +* four `ld.global.u32` at `W + ((laneid·4)&12) + {145984, 146000, 146016, + 146032}` → **phase 16's C bias**; +* **24 packs of `%r18435…%r18458`** — the *shared* A that E13 produced — so + phase 16's A is bit-identical to phase 14's… (checked: `%r12971 ← mov.b32 + {%rs4510, %rs4511}` at s12595 and `%r12971` is phase 16's first A register; + contrast phase 14's first A register `%r12414 ← mov.b32 {%rs4334, %rs4335}` at + s12254, sourced from `%r18435` at s12253 — the same register, so yes, + **identical**). + +### E16/E18/…/E36 — the 164-statement activation epilogues + +Twelve shape-identical 164-statement epilogues (shape hash `706fcc703f68`): +36 `mov.b32`, 32 `cvt.rn.f16.f32`, 24 `mul.f16x2`, 8 each +`neg/max/min/abs/sub/add.f16x2`, 6 `ld.weak`, no `ld.global`, no constants of +their own (they re-`cvt` `%f861…%f864`). + +Each applies the E14 activation to its own phase's D and packs 8 b32 → the next +odd phase's A, and reads 6 weight fragments → the next odd phase's B. +Evidence (E16): + +``` +s12642 L27622: cvt.rn.f16.f32 low, %f861 +s12651 L27649: max.f16x2 %r13026,%r12939,%r13024 // phase 16's D +s12658 L27677: mul.f16x2 %r13046,%r12939,%r13043 +s12782 L28107: ld.weak.global.ca.v4.u32 { %r13253,…},[%rd326] // W+146048 +s12795 L28135: mov.b32 %r13397, {%rs4534, %rs4535} // phase 17's A +``` + +**No table add and no residual**: these epilogues produce only A and B. + +### E17/E19/…/E37-pre — the 60-statement pack epilogues + +Eleven shape-identical 60-statement epilogues (shape hash `a7b578456a5a`): +24 packs, 12 `mov.b32`, 6 `ld.weak`, 4 `ld.global.u32`. + +``` +s12594 L27453: cvt.rn.satfinite.e4m3x2.f16x2 %rs4510, %r18435 +s12842 L28285: cvt.rn.satfinite.e4m3x2.f16x2 %rs4542, %r18435 +``` + +Each packs the same 24 registers `%r18435…%r18458` (so every even phase +P16, P18, …, P36 gets the identical A operand), reads 6 weight fragments → the +next even phase's B, and 4 `ld.global.u32` → the next even phase's C bias +(E15→P16@145984, E17→P18@152192, E19→P20@158400, E21→P22@164608, +E23→P24@170816, E25→P26@177024, E27→P28@183232, E29→P30@189440, +E31→P32@195648, E33→P34@201856, E35→P36@208064). + +#### Shape of the whole MLP region (E13–E37) + +``` +E13 normed tile → P14's A (s12252) ; shared tile T = %r18435… (s12158) +P14: A = f(D13), B = W14, C = bias@139584 → D14 (48×96×96) +E14: act(D14) → P15's A ; P15's C = D13 + table@142720 +P15: A = act(D14), B = W15, C = D13+table → D15 (16×96×32) +E15: pack T → P16's A ; B = W16 ; P16's C = bias@145984 +P16: A = pack(T), B = W16, C = bias@145984 → D16 (48×96×96) +E16: act(D16) → P17's A ; B = W17 +P17: A = act(D16), B = W17, C = D15 → D17 (16×96×32) +E17: pack T → P18's A ; B = W18 ; P18's C = bias@152192 +P18: A = pack(T), B = W18, C = bias → D18 +E18: act(D18) → P19's A ; P19's C = D17 + … (the same two-phase motif repeats with the bias offsets of §2 until) +P37: A = act(D36), B = W37, C = D35 → D37 +E37: pack D37 → 12 plane-arena stores ; P38: B = W38, C = bias@212736 +P38: A = those packs, B = W38, C = bias → D38 (48×48×96) +``` + +The claim "odd phase's C = previous odd phase's D" is machine-checked for every +odd phase from P17 on (P15 is the exception, whose C is the register pair E14 +builds). The claim "even phase's C comes from a `ld.global.u32`" holds for +P14…P38. + +### E37 — s15297–s15504: pack → 12 guarded plane-arena stores → B/C for P38 + +208 statements; the only `st.global` in the entry (12 of them, all here). + +**(a) requantise, s15297–s15332.** 12 groups of `2 cvt + 1 mov.b32` → the 12 +b32 `%r481…%r492` (phase 37's D). + +**(b) plane-arena scatter, s15333–s15482.** + +``` +s15333 L36645: ld.param.u64 %rd571, [%rd7+48] // = param_0+48 +s15336 L36650: shr.u32 %r493, %r18989, 2 // g = laneid>>2 +s15337 L36651: and.b32 %r494, %r18989, 3 // t = laneid&3 +s15340 L36654: add.s32 %r19271, %r480, %r19269 // y = %r480 + (laneid>>5) +s15346 L36660: add.s32 %r19277, %r1, %r19270 // x = %r1 + (g&7) +s15351 L36665: shl.b32 %r19278, %r19277, 3 // x<<3 +s15352 L36666: mad.lo.s32 %r495, %r7, %r19271, %r19278 +s15354 L36668: selp.b32 %r496, -1, %r19279, %p1 +s15359 L36674: st.global.u32 [%rd573], %r481 +``` + +Stride register `%r7 = 8·ex` (s14). Each store is `idx = 8·ex·y + 8·x + d`, +`d = t` or `t|4`, guarded by +`(y<0)|(y≥ey)|(laneid>63)|(x<0)|(x≥ex)` (s15341–s15350, L36655–L36664); a guard +failure stores `-1` as the index, which the following `setp.lt.s32` + `bra` +turns into "skip the store". + +Store values, bases and column offsets (`g = laneid>>2`, `t = laneid&3`, +`%r480 = %r2 + 2·tid.z` at s11653/L24950, `%r8 = ey·8·ex`): + +| store | stmt | value | index base | d | +|---|---|---|---|---| +| 1 | s15359 | `%r481` | `idx1` | `t` | +| 2 | s15368 | `%r482` | `idx1` | `t\|4` | +| 3 | s15401 | `%r483` | `idx2` | `t` | +| 4 | s15409 | `%r484` | `idx2` | `t\|4` | +| 5 | s15419 | `%r485` | `idx1 + %r8` | `t` | +| 6 | s15427 | `%r486` | `idx1 + %r8` | `t\|4` | +| 7 | s15437 | `%r487` | `idx2 + %r8` | `t` | +| 8 | s15445 | `%r488` | `idx2 + %r8` | `t\|4` | +| 9 | s15455 | `%r489` | `idx1 + 2·%r8` | `t` | +| 10 | s15463 | `%r490` | `idx1 + 2·%r8` | `t\|4` | +| 11 | s15473 | `%r491` | `idx2 + 2·%r8` | `t` | +| 12 | s15481 | `%r492` | `idx2 + 2·%r8` | `t\|4` | + +with the two bases built as `mad.lo.s32 %rBASE, 8·ex, y, 8·x`: + +| base | stmt | y | x | +|---|---|---|---| +| `idx1 = %r495` | s15352, L36666 | `%r480 + (laneid>>5)` | `%r1 + (g&7)` | +| `idx2 = %r499` | s15394, L36712 | `%r19505 + ((g+8)>>3)` | `%r1 + ((g+8)&7)` | + +`%r19505` is a *second* row origin: +`s15370 mov.u32 %r19511, %ctaid.y` / `s15372 shl.b32 %r19509, %r19511, 3` / +`s15375 sub.s32 %r19506, %r19509, %r19510` / `s15376 add.s32 %r19505, %r19506, +%r19507` with `%r19507 = 2·tid.z` (s15373/s15374), i.e. +`ctaid.y·8 − origin_y + 2·tid.z` — so the two halves of this scatter start at +different rows. The `+%r8` (s15412 `mad.lo.s32 %r502, %r2148, %r19493, %r495`) +and `+2·%r8` (s15466 `mad.lo.s32 %r511, %r2148, %r19496, %r505`) forms then step +one and two rows further. + +**(c) next B/C, s15483–s15504.** + +``` +s15492 L36832: add.s64 %rd596, %rd600, 211200 +s15493 L36834: ld.weak.global.ca.v4.u32 { %r19307,…%r19310},[%rd596] +s15497 L36842: ld.weak.global.ca.v4.u32 { %r19315,…%r19318},[%rd598] +s15503 L36851: ld.global.u32 %r19329, [%rd604+212736] +s15504 L36852: ld.global.u32 %r19339, [%rd604+212752] +``` + +Three weight fragments at `W + {211200, 211712, 212224}` → phase 38's B, two +`u32` at `W + ((laneid&3)·4 &12) + {212736, 212752}` → phase 38's C bias. + +### E38 — s15511–s15796: the final epilogue + +286 statements; it consumes phase 38's four D accumulators (`%r19360 %r19370 +%r19497 %r19498`) and writes the surface. + +**(a) staging, s15511–s15542.** + +``` +s15511 L36895: bar.sync 0 +s15522 L36908: st.shared.u32 [%r520], %r19360 +s15526 L36913: st.shared.u32 [%r520+16], %r19370 +s15539 L36927: st.shared.u32 [%r522], %r19361 +s15541 L36930: st.shared.u32 [%r522+16], %r19371 +``` + +Four guarded stores of the phase-38 D pairs into shared, indexed from +`%r518 = laneid>>2`, `%r519 = laneid&3` and `%tid.z`. + +**(b) coordinates and bounds check, s15543–s15570.** + +``` +s15551 L36941: mov.u32 %r19403, %tid.x +s15559 L36949: add.s32 %r525, %r1, %r523 // x +s15560 L36950: add.s32 %r526, %r19512, %r524 // y +s15565 L36955: ld.param.v2.u32 {%r19418, %r19419}, [%rd634] +s15570 L36960: @%p412 bra $L__BB1_486 +``` + +**(c) row max over 5 shared values, s15571–s15591.** + +``` +s15577 L36968: ld.shared.u32 %r19421, [%r19470] +s15583 L36974: ld.shared.u32 %r19442, [%r19470+16] +s15585 L36977: max.f16x2 %r19420,%r19421,%r19422 +s15590 L36994: max.f16 %rs4961,%rs4958,%rs4963 +s15592 L36999: sub.f16x2 %r19429,%r19421,%r19443 +``` + +Five `u32` (= 10 f16) per row, reduced in registers — **no warp shuffle**. + +**(d) softmax, s15592–s15676.** + +``` +s15595 L37007: mul.ftz.f32 %f905, %f865, 0f3FB8AA3B // * log2e +s15596 L37008: ex2.approx.ftz.f32 %f867, %f905 +s15651 L37126: add.ftz.f32 %f922, %f920, %f882 // running row sum +s15653 L37128: div.approx.ftz.f32 %f883, %f904, %f922 // 1/rowsum, %f904 = 1.0 +``` + +`y = 2^((x−max)·log2e)`, `p = y·(1/Σy)` in f16, five f16x2 registers. + +**(e) 3×3 colour texture, s15677–s15758.** + +``` +s15677 L37176: ld.param.v2.f32 {%f924, %f925}, [%rd635+136] +s15683 L37182: ld.param.u64 %rd622, [%rd635+88] +s15685 L37185: tex.base.2d.v4.f16.f32 {%rs4986,%rs4987,%rs4988,%rs4989}, [%rd606, {%f884,%f885}] +s15687 L37189: fma.rn.f16 %rs4990,%rs4986,%rs5000,%rs4983 +``` + +`%rd635 = param_0` (s15571), so the colour texture handle is **`param_0+88`** +and the coordinate scales are **`param_0+136`**. Nine +`tex.base.2d.v4.f16.f32` (s15685, 15697, 15709, 15721, 15726, 15732, 15744, +15750, 15755) cover the 3×3 neighbourhood of clamped `(x−1, x, x+1) × +(y−1, y, y+1)`, accumulated into 3 channels with `fma.rn.f16`. + +**(f) the two integer-coordinate textures, s15759–s15762.** + +``` +s15759 L37357: ld.param.u64 %rd624, [%rd635+96] +s15760 L37359: tex.base.2d.v4.f16.s32 {%rs5130,%rs5131,%rs5132,%rs5133}, [%rd624, {%r525,%r526}] +s15761 L37361: ld.param.u64 %rd626, [%rd635+104] +s15762 L37363: tex.base.2d.v4.f16.s32 {%rs5134,%rs5135,%rs5136,%rs5137}, [%rd626, {%r525,%r526}] +``` + +**These are the `+96` / `+104` texture reads the brief asks about** — handles at +`param_0+96` and `param_0+104`, sampled at the *integer* pixel coordinate +`(%r525, %r526)`. + +**(g) combine, sigmoid gate, surface store, s15763–s15796.** + +``` +s15763 L37366: cvt.f32.f16 %f902, %rs5138 +s15764 L37369: mul.ftz.f32 %f935, %f902, 0fBFB8AA3B +s15765 L37370: ex2.approx.ftz.f32 %f936, %f935 +s15766 L37371: add.ftz.f32 %f937, %f936, 0f3F800000 +s15767 L37372: div.approx.ftz.f32 %f903, %f904, %f937 // 1/(1+2^(-log2e·v)) +s15770 L37382: sub.f16 %rs5141,%rs5140,%rs5139 // 1 - sigmoid +s15771 L37386: mul.f16 %rs5144,%rs5118,%rs5139 // acc * sigmoid +s15772 L37390: fma.rn.f16 %rs5187,%rs5130,%rs5141,%rs5144// + tex96 * (1-sig) +s15777 L37410: set.nan.f16.f16 %rs5165,%rs5134,%rs5134 // + tex104 unless NaN +s15793 L37449: mov.u16 %rs5186, 0 +s15794 L37451: sust.b.2d.v4.b16.zero [%rd629, {%r19489,%r526}], {%rs5187,%rs5188,%rs5189,%rs5186} +``` + +`%rd629 = param_0+112` (s15582). The store column is `%r525·8` +(s15792 `shl.b32 %r19489, %r525, 3`), the row `%r526`; the fourth channel is +the zero literal, so this is a **3-channel write into a 4-channel surface**. +The `set.nan`/`bra` triad (s15777–s15790) adds the `+104` read only when it is +not NaN. + +**Inputs:** the 4 returned D registers, `param_0+{48,88,96,104,112,136}`, the +shared scratch, constants `0f3FB8AA3B`, `0fBFB8AA3B`, `0f3F800000`. +**Outputs:** none (the kernel returns, s15796). + +--- + +## 4. Texture reads, surface writes, and the `+24` input + +| what | where | +|---|---| +| `param_0+8` — input feature plane arena, read by phase 1's A loads | prologue s66…s451 (60 `ld.global`) | +| `param_0+24` — the patch-gather source E1 reads | s2288 (`ld.param.u64 %rd2, [%rd7+24]`) and the 24 `ld.global.v2.u16` at s2444…s5593 | +| `param_0+48` — the plane arena E37 scatters phase 37's output to | s15333, 12 `st.global.u32` at s15359…s15481 | +| `param_0+88` — the colour texture handle | s15683, 9 `tex.base.2d.v4.f16.f32` at s15685…s15755 | +| `param_0+96` — texture handle #2 (integer coords) | s15759/s15760 | +| `param_0+104` — texture handle #3 (integer coords) | s15761/s15762 | +| `param_0+112` — the output surface | s15582, `sust.b.2d.v4.b16.zero` s15794 | +| `param_0+136` — two f32 texture coordinate scales | s15677 | + +**The skip input at `+24` supplies the patch-gather source.** E1 reads it once +per lane per stencil position and never writes it; the buffer is addressed in +4-byte elements (one f16x2 = 2 channels) with index +`clamp(row)·8·ex + clamp(col)·8 + clamp(t,0,7)`: + +``` +s2318 L4671: mad.lo.s32 %r3078, %r3068, %r7, %r3077 // clamp_row*(8*ex) + clamp_col*8 +s2440 L4800: add.s32 %r19540, %r2996, %r2992 // + clamp(t, - , 7) +s2442 L4803: mul.wide.u32 %rd191, %r19540, 4 +s2444 L4805: ld.global.v2.u16 {%rs314, %rs315}, [%rd192] +``` + +The same index form and the same 24-gather shape as the sibling kernel's §3/E1. + +**The surface writes** are `param_0+112` (E38, s15794), a 4-channel b16 surface +written with 3 live channels. The **plane-arena writes** are E37's 12 +`st.global.u32` to `param_0+48` (s15359…s15481). + +**Nothing reads `param_0+48` back** in this entry: `param_0+48` is the source of +exactly one `ld.param` (s15333) and never the base of a load. Likewise the +texture handles at `+88/+96/+104` are only ever `tex.*` operands. + +## 5. The phase table, M/N/K checked + +`rr_layer_spec.py dec2`'s phase table with `M/16 · N/8 · K/32 == mma` evaluated +on every row: + +| # | stmts | M | N | K | mma | M/16·N/8·K/32 | holds? | weight bytes (rel. `W`) | bias bytes | +|---|---|---|---|---|---|---|---|---|---| +| 1 | s452–s595 | 192 | 384 | 128 | 144 | 12·48·4 = 2304 | **no** | 0…11788 (+12288·`tid.z`) | 49152…49328 (+192·`tid.z`) | +| 2 | s7089–s7112 | 96 | 32 | 32 | 24 | 6·4·1 = 24 | yes | 50112…50636 | – | +| 3 | s7120–s7143 | 96 | 32 | 32 | 24 | 24 | yes | 53184…53708 | – | +| 4 | s7151–s7174 | 96 | 32 | 32 | 24 | 24 | yes | 51136…51660 | – | +| 5 | s7182–s7205 | 96 | 32 | 32 | 24 | 24 | yes | 54208…54732 | – | +| 6 | s7213–s7236 | 96 | 32 | 32 | 24 | 24 | yes | 52160…52684 | – | +| 7 | s7244–s7267 | 96 | 32 | 32 | 24 | 24 | yes | 55232…55756 | – | +| 8 | s7439–s7486 | 64 | 96 | 32 | 48 | 4·12·1 = 48 | yes | **none** | 56256…68044 | +| 9 | s11330–s11377 | 192 | 96 | 96 | 48 | 12·12·3 = 432 | **no** | **none** | – | +| 10 | s11547–s11558 | 16 | 96 | 32 | 12 | 1·12·1 = 12 | yes | 68544…71116 | – | +| 11 | s11578–s11589 | 16 | 96 | 32 | 12 | 12 | yes | 90048…92620 | – | +| 12 | s11609–s11620 | 16 | 96 | 32 | 12 | 12 | yes | 111552…114124 | – | +| 13 | s11640–s11651 | 16 | 96 | 32 | 12 | 12 | yes | 133056…135628 | – | +| 14 | s12288–s12299 | 48 | 96 | 96 | 12 | 3·12·3 = 108 | **no** | 136512…139084 | 139584…139632 | +| 15 | s12557–s12568 | 16 | 96 | 32 | 12 | 12 | yes | 139648…142220 | – | +| 16 | s12629–s12640 | 48 | 96 | 96 | 12 | 108 | **no** | 142912…145484 | 145984…146032 | +| 17 | s12805–s12816 | 16 | 96 | 32 | 12 | 12 | yes | 146048…148620 | – | +| 18 | s12877–s12888 | 48 | 96 | 96 | 12 | 108 | **no** | 149120…151692 | 152192…152240 | +| 19 | s13053–s13064 | 16 | 96 | 32 | 12 | 12 | yes | 152256…154828 | – | +| 20 | s13125–s13136 | 48 | 96 | 96 | 12 | 108 | **no** | 155328…157900 | 158400…158448 | +| 21 | s13301–s13312 | 16 | 96 | 32 | 12 | 12 | yes | 158464…161036 | – | +| 22 | s13373–s13384 | 48 | 96 | 96 | 12 | 108 | **no** | 161536…164108 | 164608…164656 | +| 23 | s13549–s13560 | 16 | 96 | 32 | 12 | 12 | yes | 164672…167244 | – | +| 24 | s13621–s13632 | 48 | 96 | 96 | 12 | 108 | **no** | 167744…170316 | 170816…170864 | +| 25 | s13797–s13808 | 16 | 96 | 32 | 12 | 12 | yes | 170880…173452 | – | +| 26 | s13869–s13880 | 48 | 96 | 96 | 12 | 108 | **no** | 173952…176524 | 177024…177072 | +| 27 | s14045–s14056 | 16 | 96 | 32 | 12 | 12 | yes | 177088…179660 | – | +| 28 | s14117–s14128 | 48 | 96 | 96 | 12 | 108 | **no** | 180160…182732 | 183232…183280 | +| 29 | s14293–s14304 | 16 | 96 | 32 | 12 | 12 | yes | 183296…185868 | – | +| 30 | s14365–s14376 | 48 | 96 | 96 | 12 | 108 | **no** | 186368…188940 | 189440…189488 | +| 31 | s14541–s14552 | 16 | 96 | 32 | 12 | 12 | yes | 189504…192076 | – | +| 32 | s14613–s14624 | 48 | 96 | 96 | 12 | 108 | **no** | 192576…195148 | 195648…195696 | +| 33 | s14789–s14800 | 16 | 96 | 32 | 12 | 12 | yes | 195712…198284 | – | +| 34 | s14861–s14872 | 48 | 96 | 96 | 12 | 108 | **no** | 198784…201356 | 201856…201904 | +| 35 | s15037–s15048 | 16 | 96 | 32 | 12 | 12 | yes | 201920…204492 | – | +| 36 | s15109–s15120 | 48 | 96 | 96 | 12 | 108 | **no** | 204992…207564 | 208064…208112 | +| 37 | s15285–s15296 | 16 | 96 | 32 | 12 | 12 | yes | 208128…210700 | – | +| 38 | s15505–s15510 | 48 | 48 | 96 | 6 | 3·6·3 = 54 | **no** | 211200…212236 | 212736…212752 | + +**Every phase whose `M/16·N/8·K/32` does not equal `mma` is one the tool also +marks `grid = band`**, and every phase that holds is marked `full`. The +mismatch factors are not constant (P1 ×16, P9 ×9, P14/…/P36 ×9, P38 ×9), so `M`, +`N` and `K` cannot all be taken at face value for those rows. For P14 the reason +is checkable and structural: + +``` +s12288 D=%r12342 A=%r12414 B=%r12293 C=bias@139584 (bo 136512) +s12290 D=%r12362 A=%r12434 B=%r12297 C=%r12342 (bo 137024) +``` + +— the same D accumulates products with B fragments from *different* 512-byte +blocks and two *different* A quads. Under the settled weight formula +(`n = 16·tt + 8·(b>>3) + (L>>2)`, verified on enc0) P14's six blocks span +`n = 0…95`, so `N = 96` is supported; then the 3-mma chains must be summing over +`M` or `K`, and neither is separately readable from the fragment structure. +See §7/U2. + +**Which phases read no weight operand:** **P8 and P9**. Both take `B` from +registers the preceding epilogue packed (E7 packs phases 3…7's D for P8's A and +B; E8 packs the probabilities and the transposed P7 for P9's A and B). Their +`bo` is `None` for every mma. + +**Weight image extent as the tool measures it:** the largest resolved offset is +**212752** (s15504, 4 bytes wide) ⇒ **212756 bytes** (1082 distinct slots). +Phase 1's B and C bias carry the only `tid.z` terms (`W + 12288·tid.z`, +`W + 192·tid.z`); with `tid.z ∈ {0,1}` (E38 rejects `tid.z > 1` at s15561 +`setp.gt.u32 %p406, %r19503, 1`) the extra 12288 bytes stay inside 212756. +**(INFERENCE** — the tool drops the `tid.z` term, so the per-window base cannot +be read off it directly.) + +## 6. The plane arena (param_0 + 48) and the per-launch tables + +* `param_0+8` is read 60 times in the prologue (s66…s451) as the **input feature + plane** that builds phase 1's 12 A fragments. +* `param_0+24` is the **patch-gather source** (see §4); it is read, never written. +* `param_0+48` is the **output plane arena**: written by E37's 12 + `st.global.u32` (s15359…s15481), never read. The entry has exactly 12 + `st.global` and no other global store. +* The only other `ld.param` sites are the 4 in the prologue (§1.1) and the 5 in + E38 (`[%rd635+88/96/104/112/136]`, s15683/15759/15761/15582/15677) plus + `[%rd7+48]` (s15333), `[%rd7+24]` (s2288) and the two `param_0+40` re-reads + (s15483/s15484). + +There is **no per-launch table generated into the plane arena by this kernel**: +the arena is only written (E37), and every table that looks like one +(`W + ((laneid<<2)&12) + {49920, 136128, 136320, 142720, …}`) lives in the +*weight image*, not the arena. + +## 7. Uncharacterised + +**U1. E9's residual registers.** The 24 registers that E9's per-column table +adds into (`%rs456/%rs459` and their siblings, s11473–s11544) have exactly one +textual definition each, at s5693/s5694 (L8430/L8434) inside **E1** — nothing +between s5694 and s11473 writes them (`grep -n '%rs456\b'` returns L8430, L8913, +L11184, L24297 only). So either the value is genuinely carried from E1's +sum-of-squares tree, or the printed PTX reuses a register name across two +disjoint live ranges without a rename. The two readings differ in what phase +10's C *is* (a table plus E1's partial sums, versus a table plus something +unnameable), so I will not guess. *Missing:* a shared-memory/register dump at +s11473, or the pre-rename SSA. + +**U2. The true `M/N/K` of the thirteen banded phases (P1, P9, P14, P16, …, +P36, P38).** For those rows `M/16·N/8·K/32 ≠ mma` (§5). `nA` counts distinct A +*register quads*, which can be either distinct `M`-tiles or distinct `K`-slices +of the same tile, and the accumulator chains mix distinct B operands, so the +two cannot be separated from the fragment structure. *Missing:* a run with a +weight-image dump, the `_prep` permutation, or the high-level layer definition. + +**U3. The identity of the 12288-byte score bias (P8's C).** E7 loads it as 24 +tiles × 512 bytes at `W + 56256`. Whether it is a relative position bias, a +learned score bias, or a per-lane constant cannot be decided from the PTX: it is +an opaque blob in a permuted weight image. *Missing:* the image's layout +description or the model's parameter names. + +**U4. The identity of the per-column tables.** `W+49920…50096` (E1 gain), +`W+136128…136304` (E9), `W+136320…136496` (E13 gain), `W+142720…142896` (E14) +are all read with the same `W + ((laneid<<2)&12) + off` pattern (12 words per +lane). Their *role* is computable (E1/E13: multiply the inverse RMS; E9/E14: +added to a residual before the next GEMM) but their *names* are not. The GEMM +biases at `+49152`, `+139584`, `+145984`, `+152192`, `+158400`, `+164608`, +`+170816`, `+177024`, `+183232`, `+189440`, `+195648`, `+201856`, `+208064`, +`+212736` are the same case. + +**U5. E1's patch-expand geometry.** As in the sibling kernel, the 36 guarded +`st.shared` are emitted as ~400 basic blocks with 413 labels and I could not +reduce the lane→(row,col) map to a closed form. Established: 34 `u32` + 2 +`v2.u16` patch stores, a second staging area of 6 `v4.u32` stores at +`smem + tid.z·{2048,3072} + {0,512,1024,6144,6656,7168}`, and the whole 9600-byte +shared allocation. *Missing:* the source-level patchify expression or a +shared-memory dump. + +**U6. Whether `param_0+8` is an input plane or a scratch table.** The prologue +reads it 60 times with 4-byte elements and never writes it, and E1 does not read +it (E1 reads `param_0+24`). So `+8` and `+24` are two different input buffers; +which one holds the noisy colour plane and which the feature planes cannot be +decided from the PTX. *Missing:* the host-side launch arguments. + +**U7. The `tid.z` strides.** Phase 1's B and bias carry `×12288` and `×192` +per-window strides and no later phase carries one. Whether the image is a +concatenation of per-window sub-images or `tid.z` selects a batch element whose +weights are interleaved cannot be decided here; consequently the "212756 bytes" +of §5 is a lower bound. + +**U8. The logical meaning of E38's final expression.** The tail computes +`out = acc·σ(v) + tex96·(1−σ(v)) + tex104` on the three channels gathered from +the 3×3 colour stencil and the two integer-coordinate textures. The PTX gives +the arithmetic exactly (§3/E38(g)) but not what model term it corresponds to. +*Missing:* the high-level source or a reference implementation. + +**U9. Why every even phase shares one A operand.** E13 emits two scaled copies +of phase 13's D (the normed packs `%r12414…` at s12252 and `%r18435…` at +s12158) and phases 14, 16, …, 36 all pack the second one. That makes the A +operands of those twelve GEMMs bit-identical; whether that is the intended +computation (one shared projection) or a consequence of a missed optimisation +cannot be decided from the PTX. *Missing:* the high-level layer definition. + +## 8. Quick acceptance index + +| requirement | where | +|---|---| +| every epilogue named and ranged | §2, §3 (E1…E38) | +| phase-1 epilogue's patch expand + norm | §3/E1 | +| the norm (`E1`, `E13`) | §3/E1, §3/E13 — raw sum of squares + 2⁻¹³, no mean, no 1/N | +| the attention (score, softmax, P·V) | §3/E7, E8, E9; §3/E9's table add | +| the activations | §3/E14 (materialises `%f861…%f864`), E16, E18, …, E36 | +| the patch expand | §3/E1 (36 `st.shared`), §7/U5 | +| the final epilogue, textures at +96/+104, surface | §3/E38, §4 | +| the texture reads at +96/+104 | §3/E38(f), s15760 / s15762 | +| the skip input at +24 | §3/E1 (s2288), §4 | +| the plane-arena writes | §3/E37 (s15359…s15481), §4, §6 | +| the phase table with M/N/K checked | §5 | +| weight image extent | §5 (212756 bytes, 1082 slots) | +| which phases read no weight | §5 (P8, P9) | +| uncharacterised | §7 | diff --git a/kernels/rr/rrswin_dec3.hip b/kernels/rr/rrswin_dec3.hip new file mode 100644 index 0000000..512fb2e --- /dev/null +++ b/kernels/rr/rrswin_dec3.hip @@ -0,0 +1,387 @@ +// Native replacement for the Ray Reconstruction denoiser's third Swin decoder, +// cuda_dldn_engine_swin_dec3_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: phases 1 is implemented; phases 2-48 are not. Phase 1 does NOT yet reproduce +// the oracle's payload: against the dec3 `p1` stage the frame-1 payload differs in +// every one of the 96 accumulators of every lane of all 64 slots, so this layer's +// image does not match the translated reference (arg112 differs, arg120 is still ok). +// The store plumbing itself is proven correct -- the `a` stage, which carries the same +// 60 A fragments and 16 seeds the cut hands over, is byte-identical (md5 +// 6711adc5517ea8d6ce16d908946189e4 both sides). What phase 1 still gets wrong is the +// mma's cross-lane structure: an m16n8k32 lane's B fragment holds one column's k +// slice, so D[row g][cols 2t,2t+1] needs a reduction across the eight column groups, +// not a butterfly within the four-lane quad. ZLUDA's fallback_mma_sync_aligned +// (zluda_ptx_impl.cpp:1226) does that with dpp and ds_bpermute; see the comment above +// phase1() for what has been established so far. Phases 2-48's accumulators are +// written back as lane-distinct placeholders, so the kernel runs and is served. +// +// The kernel is four waves per block (blockDim (32, 1, 4)); %tid.z is the slab index +// that scales the input stride, the weight-image stride and the bias stride. The PTX +// this file replaces is ~/.cache/d4r-rr-corpus/0020-PREPASS_ENTRYPOINT_NAME.ptx, whose +// entry opens at file line 1016 and whose mma region is statements s543-s19381 (file +// lines 1658-46565). +// +// kernels/rr/swin_dec3_recipe.py (D4R_RRSWIN_CUT, the default) keeps NVIDIA's texture +// prologue (file lines 1-1657) and surface epilogue (46566-end) and replaces the 1112 +// mma of the 48 phases with the call below. The accumulators cross the cut through +// shared memory, because ZLUDA lowers a multi-value C++ return to LLVM's function return +// type and never forms a callee-side .param-space object. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +// --------------------------------------------------------------------------- +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinDec3Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinDec3Params) == 144, "parameter block"); + +enum : int +{ + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // plane arena pointer (arg048) +}; + +#define DEVF __attribute__((device)) static inline +typedef uint32_t lds_u32 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// word v as the lane t^m of its group of four holds it, m = 0..3 +DEVF uint32_t bfly_m(uint32_t v, int m) +{ + return m == 0 ? v : (m == 1 ? bfly1_bits(v) : (m == 2 ? bfly2_bits(v) : bfly1_bits(bfly2_bits(v)))); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// The mma's fragment layouts, which are fixed by the instruction (they are not +// NVIDIA's choice, so they are the same for every layer): +// A reg q, byte j -> row g + 8*(q&1), k = 16*(q>>1) + 2t + (j&1) + 8*((j>>1)&1) +// B byte b -> column g, k = 16*(b>>3) + 2t + (b&1) + 8*((b>>1)&1) +// C/D reg 0 -> row g, columns 2t, 2t+1; reg 1 -> row g+8, same columns +// with g = laneid >> 2 and t = laneid & 3. A lane therefore holds 8 of the 32 k's of +// each of two rows, and 8 of the 32 k's of one column of the B fragment; the four +// lanes t = 0..3 hold the four disjoint eighths, so the two butterfly steps bring the +// other three in. Because both operands' k index depends on t in the same way, one +// butterfly index pairs an A byte with the B byte that sits at the same k. +// +// The 16 and the 8 are not interchangeable. ZLUDA splits NVIDIA's m16n8k32 e4m3 mma +// into two m16n8k16 f16 mmas (`e4m3_a_k16_fragment`, zluda_ptx_impl.cpp:1390): the +// first takes A registers {x, y} and B register x, the second takes {z, w} and B +// register y. So register q covers the k range 16*(q>>1), and inside a register the +// byte pair j >> 1 selects the +8 block. An earlier revision of this comment had the +// two swapped, which permuted the k's of both operands. +// +// That split is also why the rounding is not a single one at the end. The two halves +// are separate mma instructions, so `pack_f16_accumulator` rounds to f16 after the +// first half and again after the second: +// +// t = f16(dot(A[0..1], B[0..3]) + C) +// D = f16(dot(A[2..3], B[4..7]) + t) +// +// Each dot runs in f32 (ZLUDA's `dot_product`), and every e4m3 product +// is exact in f32, so a plain f32 accumulation of one half's k's reproduces it. + +// --------------------------------------------------------------------------- +// Phase 1 (file lines 1658-3334, 240 mma). +// +// The 240 mma are 24 groups of ten. Group g uses A fragments 5*(g/8) + i and B +// fragments 10*(g%8) + 2i + c, i = 0..4 (the k-slices, K = 160) and c in {0,1} (the +// two n-tiles of the group's B block), chained through C: the first step of each chain +// is seeded with bias[g%8][c], every later step with the previous step's f16 result. +// So the phase is 48 output tiles of 16x8 (3 m-blocks x 16 n-tiles) over K = 160. +// +// The weight image holds phase 1's B block at [0, 20480) relative to W + z*20480: +// forty 512-byte tiles, tile t = 5*(g%8) + i covering sixteen columns (n = 0..7 for +// c = 0, n = 8..15 for c = 1) and k = 0..31, one lane's 16 bytes at +16*laneid. That +// is the `ld.weak.global.ca.v4.u32 {..}, [rd9 + 512*t]` chain of the prologue with +// rd9 = W + z*20480 + 16*laneid (file line 1471). + +// one output tile: the two f16x2 pairs the mma writes, [m-block][n-tile][row half] +DEVF void phase1(const uint32_t as[60], const uint8_t* w, const uint32_t seeds[16], + int z, uint32_t lane, uint32_t d[3][16][2]) +{ +#pragma unroll + for (int nb = 0; nb < 8; ++nb) { +#pragma unroll + for (int c = 0; c < 2; ++c) { + const uint32_t seed = seeds[2 * nb + c]; +#pragma unroll + for (int mt = 0; mt < 3; ++mt) { + // C of the first k-step: the seed u32 duplicated into both f32 halves, + // i.e. the lane's two columns of both rows start at the same f16 pair + half_t prev[2][2]; + for (int col = 0; col < 2; ++col) { + const half_t v = col == 0 ? half_lo(seed) : half_hi(seed); + prev[0][col] = v; + prev[1][col] = v; + } +#pragma unroll + for (int i = 0; i < 5; ++i) { + const int f = 10 * nb + 2 * i + c; // B fragment index + const uint32_t* a = as + 4 * (5 * mt + i); + // tile f>>1, half f&1 (bytes 8..15 of the lane's 16), at +16*laneid + const uint8_t* tile = w + (uint32_t)z * 20480u + 512u * (uint32_t)(f >> 1) + + 16u * lane + 8u * (uint32_t)(f & 1); + const uint32_t b0 = *(const uint32_t*)(tile); + const uint32_t b1 = *(const uint32_t*)(tile + 4); + // ZLUDA runs this mma as two m16n8k16 f16 mmas, so each half's + // dot product is accumulated and then rounded to f16 on its own. + // A register q covers k + 16*(q>>1) and byte j within it selects + // the +8 block, so half kg uses A registers 2*kg+0 and 2*kg+1 and + // B bytes 4*kg..4*kg+3. + float acc[2][2]; +#pragma unroll + for (int col = 0; col < 2; ++col) { + acc[0][col] = (float)prev[0][col]; + acc[1][col] = (float)prev[1][col]; + } +#pragma unroll + for (int kg = 0; kg < 2; ++kg) { + float dot[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + // butterfly index m brings in the lane whose t is t^m, which + // holds the k's 2*(t^m), 2*(t^m)+1, 8+2*(t^m), 8+2*(t^m)+1 +#pragma unroll + for (int m = 0; m < 4; ++m) { + const uint32_t a0 = bfly_m(a[2 * kg + 0], m); // row g + const uint32_t a1 = bfly_m(a[2 * kg + 1], m); // row g+8 + const uint32_t bb = bfly_m(kg == 0 ? b0 : b1, m); +#pragma unroll + for (int j = 0; j < 4; ++j) { + const float bv = e4m3_to_f32((bb >> (8 * j)) & 0xffu); + dot[0][0] += e4m3_to_f32((a0 >> (8 * j)) & 0xffu) * bv; + dot[0][1] += e4m3_to_f32((a1 >> (8 * j)) & 0xffu) * bv; + } + } + // Both k16 halves accumulate into the same f32 accumulator and + // the pair rounds to f16 once. ZLUDA's scalar fallback rounds + // between the halves, but the gfx12 native-FP8 path the runtime + // actually takes does not -- it is two chained f32-accumulating + // WMMAs, exactly what the family's k32_e4m3() in tex_common.h + // reproduces. +#pragma unroll + for (int col = 0; col < 2; ++col) { + acc[0][col] += dot[0][col]; + acc[1][col] += dot[1][col]; + } + } +#pragma unroll + for (int col = 0; col < 2; ++col) { + prev[0][col] = (half_t)acc[0][col]; + prev[1][col] = (half_t)acc[1][col]; + } + } + d[mt][2 * nb + c][0] = pair_of(prev[0][0], prev[0][1]); + d[mt][2 * nb + c][1] = pair_of(prev[1][0], prev[1][1]); + } + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_dec3_recipe.py's oracle recipe: +// with D4R_RRSWIN_DEBUG_DEC3=p1 the same splice keeps NVIDIA's whole body and stores +// that stage's registers into the plane arena at +D4R_RRSWIN_DEBUG_BASE, which the +// kernel never otherwise writes, and the launch dump then holds the translated values +// for a block/lane. Built with -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, +// D4R_TEX_CFLAGS) and the same -DD4R_RRSWIN_DEBUG_BASE the oracle build used, this body +// stores the same registers of its own phase n in the same order, so the two dumps +// compare byte for byte. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 27000000 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t cx = __builtin_amdgcn_workgroup_id_x(); + const uint32_t cy = __builtin_amdgcn_workgroup_id_y(); + const uint32_t cz = __builtin_amdgcn_workitem_id_z(); + // the oracle's slots cover ctaid.x < 8, ctaid.y < 2 and all four waves of the block + if (cx >= 8u || cy >= 2u || cz >= 4u) { + return; + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot, swin_dec3_recipe.py's debug_slot: 32 lanes x n x 4 bytes, at + // least 8192, rounded up to a power of two (its splice forms block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + const uint64_t block = ((uint64_t)cy * 8ull + cx) * 4ull + cz; + // swin_dec3_recipe.py's DEBUG_BASE, which reads D4R_RRSWIN_DEBUG_BASE and defaults + // to the tail described there; pass the same value to both builds or the two sides + // store to different places. dec3's plane arena is the tail of the 65,945,600-byte + // scratch block all eleven denoiser layers share: arg048 is at block offset + // 35,799,040, so the arena is [35,799,040, 65,945,600) and the family default of + // 46,000,000 falls outside the block entirely. A payload must also clear the other + // layers' sub-buffers (the replay manifests list block offsets 0, 30146560, + // 35799040, 36387840, 36535040, 37683200, 39567360, 45219840 and 60293120) as well + // as dec3's own inputs at 37683200 and 39567360. + const uint64_t debug_base = D4R_RRSWIN_DEBUG_BASE; + uint32_t* dst = (uint32_t*)(arena + debug_base + block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. The fifteen 16-row A fragments arrive in the order the mma reads them +// (fragment f is the four consecutive registers %r+0..3 of A_BASES in +// swin_dec3_recipe.py), then phase 1's sixteen bias seeds (%r2453 %r2463 ... %r3163, +// read from W + z*256 + ((laneid<<2)&12) + 81920 + 16*i at file lines 1633-1648), the +// weight image and the parameter block. +// +// The four accumulators phase 48's epilogue reads cross the cut through the shared +// scratch, not `call.uni`'s return parameters: `scratch` is the base of the entry's +// only shared array (12800 bytes, dead across the cut -- E48 re-materialises it), and +// the four values sit 16 bytes apart per lane. +// +// Address space 3 (the shared scratch) explicitly: a generic store lowers to flat, +// which faults. +extern "C" __attribute__((device)) void d4r_swin_dec3( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t a24, uint32_t a25, uint32_t a26, uint32_t a27, + uint32_t a28, uint32_t a29, uint32_t a30, uint32_t a31, uint32_t a32, uint32_t a33, uint32_t a34, + uint32_t a35, uint32_t a36, uint32_t a37, uint32_t a38, uint32_t a39, uint32_t a40, uint32_t a41, + uint32_t a42, uint32_t a43, uint32_t a44, uint32_t a45, uint32_t a46, uint32_t a47, uint32_t a48, + uint32_t a49, uint32_t a50, uint32_t a51, uint32_t a52, uint32_t a53, uint32_t a54, uint32_t a55, + uint32_t a56, uint32_t a57, uint32_t a58, uint32_t a59, uint32_t c0, uint32_t c1, uint32_t c2, + uint32_t c3, uint32_t c4, uint32_t c5, uint32_t c6, uint32_t c7, uint32_t c8, uint32_t c9, + uint32_t c10, uint32_t c11, uint32_t c12, uint32_t c13, uint32_t c14, uint32_t c15, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[60] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, + a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, + a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, a47, + a48, a49, a50, a51, a52, a53, a54, a55, a56, a57, a58, a59}; + const uint32_t seeds[16] = {c0, c1, c2, c3, c4, c5, c6, c7, + c8, c9, c10, c11, c12, c13, c14, c15}; + // The epilogue's four accumulators: %r26071, %r26072, %r26081 and %r26082 -- phase + // 48's two mma D pairs. Address space 3 explicitly: a generic store lowers to flat, + // which faults. + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + 4 * (uint32_t)lane_id(); + const uint32_t lane = lane_id(); + const int z = (int)__builtin_amdgcn_workitem_id_z(); + + // ---- phase 1 ----------------------------------------------------------- + uint32_t d1[3][16][2]; // [m-block][n-tile][row half]: f16 pair + phase1(as1, w, seeds, z, lane, d1); +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + // the oracle's stage p1: the 48 chain finals in mma order (group major, the two + // n-tiles of the group minor), each the (row g, row g+8) pair the mma writes + uint32_t regs[96]; + int i = 0; + for (int g = 0; g < 24; ++g) { + for (int c = 0; c < 2; ++c) { + regs[i++] = d1[g / 8][2 * (g % 8) + c][0]; + regs[i++] = d1[g / 8][2 * (g % 8) + c][1]; + } + } + debug_store(prm, regs, 96); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 100 + { + // the oracle's stage a: the A fragments and C seeds as the mma reads them + uint32_t regs[76]; + for (int i = 0; i < 60; ++i) { + regs[i] = as1[i]; + } + for (int i = 0; i < 16; ++i) { + regs[60 + i] = seeds[i]; + } + debug_store(prm, regs, 76); + } +#endif + + // ---- handing the accumulators back ------------------------------------ + // %r26071/%r26072 and %r26081/%r26082 are phase 48's two mma D pairs (E48 stores + // them into the shared array at (48*y + 6*x) and softmaxes five taps of it). + // Phase 48 is not implemented yet; until it is, fill the four slots with + // lane-distinct values so the read-back path is observable without wild magnitudes. + for (int i = 0; i < 4; ++i) { + out[i] = (uint32_t)lane + 32u * (uint32_t)i; + } +} + +// --------------------------------------------------------------------------- +// Weight image layout of phase 1 (byte offsets from the PTX's own loads; the phase +// reads [0, 20480) of W + z*20480, forty 512-byte tiles): +// tile t = 5*(g%8) + i, half 0 = n 0..7 (c = 0), half 1 = n 8..15 (c = 1), k = 0..31 +// byte j of a lane's 16-byte tile -> (k, n) at +// base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// with base = W + z*20480 + 512*t + 16*laneid + 8*(f&1). phase1() reads that layout +// directly through the lane's own two registers instead of recomputing the address. +// +// Fragment maps (fixed by the mma instruction, see the comment above phase 1): +// A reg r, byte j -> row g + 8*(r&1), k = 8*(r>>1) + 2t + (j&1) + 16*((j>>1)&1) +// B byte b -> column g, k = 8*(b>>3) + 2t + (b&1) + 16*((b>>1)&1) +// C/D reg 0 -> row g, cols 2t, 2t+1; reg 1 -> row g+8, same cols +// A plain f32 dot product over K plus C, rounded to f16 once, reproduces the +// translated kernel's output exactly, so the phases need no operand-layout gymnastics +// and no WMMA intrinsics: every GEMM here is exact in f32 before the f16 rounding. \ No newline at end of file diff --git a/kernels/rr/rrswin_dec3_epilogues.md b/kernels/rr/rrswin_dec3_epilogues.md new file mode 100644 index 0000000..ba1de7a --- /dev/null +++ b/kernels/rr/rrswin_dec3_epilogues.md @@ -0,0 +1,818 @@ +# `cuda_dldn_engine_swin_dec3_kernel` — the epilogues of phases 1…48 + +Companion to `kernels/rr/rr_layer_spec.py dec3`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0020-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec3_kernel` (the entry opens at file line 1016, its body +holds statements s1…s19663, and s19663 / L47124 is the `ret`). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` is + the physical line** of the same instruction in the corpus file, so every claim + can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. A phase's *prologue* (its weight loads and, for the + register-fed phases, its operand construction) is written at the tail of the + previous epilogue, so a few loads attributed here actually serve the next phase; + each is named in place. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_dec3_kernel_param_0+40]` (s8) then + `cvta.to.global.u64 %rd50, %rd2` (s9). Every `ld.weak.global.ca.v4.u32` in an + epilogue reads `W + 16*laneid + imm`, and every bias/table row is read with the + pattern `W + ((laneid<<2)&12) + imm` (s523–s526 is the canonical construction). +* `S` denotes the plane arena: `ld.param.u64 %rd763, [%rd8+48]` (s19164) then + `cvta.to.global.u64 %rd5, %rd763` (s19165). This is the entry's **only** read + of `param_0+48`. +* `SM` denotes the 12800-byte shared array + `_ZZ33cuda_dldn_engine_swin_dec3_kernel33DldnEngineSwinEncParamsStructBaseE4smem` + (declared at file line 1027); it is materialised by `mov.u32` into a register at + s954, s972, s1700, s1746, s19355 and others. +* `%r9 = %tid.z` (s433) is the **slab index**; it scales the input-buffer stride + (×20480, s434), the shared-tile stride (×2048 via `<<11`, s9018; ×16 at s1709), + the weight-image stride (×24576: `%r25647 = %r9*12288` s9101 then `*2` s9102), + the bias stride (×256: `%r3569 = %r9<<7` s519) and ×512 (s13548). dec3 has **no + guard** on `%r9`; only a derived test `setp.gt.u32 %p499, %r186, 31` with + `%r186 = %r9<<4` (s9075) restricts one store group. +* The C/D register layout and the weight-addressing formula are the settled family + ones: `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, + `g = laneid>>2`, `t = laneid&3`; A `reg0 = row g, k = 2t+(j&1)+16*((j>>1)&1)`, + `reg1 = row g+8 same k`, `reg2 = row g, k+8`, `reg3 = row g+8, k+8`. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `param+0`, extents `(ex, ey)` | `ld.param.v2.u32 {%r3347, %r3348}, [param_0]` | s14 | +| `param+8`, the e4m3 feature buffer | `ld.param.u64 %rd51, [param_0+8]` → `cvta.to.global.u64 %rd52, %rd51` | s29–s30 | +| `param+24`, the f16 image buffer (**the skip input**) | `ld.param.u64 %rd3, [%rd1+-56]` → `cvta.to.global.u64 %rd4, %rd3`, where `%rd1 = param_0+80` | s4, s2780–s2781 | +| `param+40`, `W` (weight image) | `ld.param.u64 %rd2, [param_0+40]` → `cvta.to.global.u64 %rd50, %rd2` | s8–s9 | +| `param+48`, `S` (plane arena) | `ld.param.u64 %rd763, [%rd8+48]` → `cvta.to.global.u64 %rd5, %rd763` | s19164–s19165 | +| `param+80`, block origin `(ox, oy)` | `ld.param.v2.u16 {%rs344, %rs345}, [param_0+80]` | s5 | +| `param+88`, low-res feature **texture** | `ld.param.u64 %rd823, [%rd836+88]` with `%rd836 = param_0` | s19438, s19550 | +| `param+96`, **texture** added unconditionally | `ld.param.u64 %rd825, [%rd836+96]` | s19626 | +| `param+104`, **texture** added per-channel under a NaN guard | `ld.param.u64 %rd827, [%rd836+104]` | s19628 | +| `param+112`, output **surface** | `ld.param.u64 %rd830, [%rd836+112]` | s19449 | +| `param+136`, `(sx, sy)` pixel→uv scale | `ld.param.v2.f32 {%f1052, %f1053}, [%rd836+136]` | s19544 | +| `SM` (12800 B) | `mov.u32 %r3926, _ZZ33…E4smem` | s1746, s9554 etc. | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, W, %rd` | s438–s439 and every load block | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, W, %rd` | s523–s526 and copies | +| block origins `%r1`, `%r2` | `sub.s32 %r1, %r3342, %r3343` (s7) and `sub.s32 %r2, %r3346, %r3344` (s13); `%r3342 = ctaid.x<<3` (s3), `%r3346 = ctaid.y<<3` (s12) | s3, s7, s12–s13 | +| `%r7 = ex<<3`, `%r8 = ey*%r7` | s15, s16 | s15–s16 | + +The per-lane table pattern matters: those loads read +`W + ((laneid<<2) & 12) + off`, so **the four lanes with equal `laneid&3` read the +same 16-byte record and the four words of a group are picked by the `off` stride**. +Those tables are indexed by **column**, not by row (same conclusion as enc0 §1.1). + +### 1.2 Constants that survive between epilogues + +| register | first definition | literal | identity | +|---|---|---|---| +| `%f476` | s9601 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | score scale (f16 `0x2466`) | +| `%fd383` | s9605 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | clamp low | +| `%fd385` | s9610 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | clamp high | +| `%f478` | s9616 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | cubic coefficient | +| `%f480` | s9621 `mov.f32 %f480, 0f3FB00000` | 1.375 | cubic offset | +| `%fd1` | s7874 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | RMS-norm epsilon | +| `%f989` | s14672 `mov.f32 %f989, 0f3ED306EB` | 0.4121621549129486 | activation ramp | +| `%f990` | s14675 `mov.f32 %f990, 0f3DA60DD6` | 0.0810810774564743 | activation width | +| `%f991` | s14678 `mov.f32 %f991, 0f3F000000` | 0.5 | activation offset | +| `%f992` | s14681 `mov.f32 %f992, 0f40000000` | 2.0 | activation clamp | + +The softmax constants `%f476/%fd383/%fd385/%f478/%f480` are defined **once**, in +phase 10's epilogue (s9601–s9621), and re-read by `cvt.rn.f16.f32`/`cvt.rn.f16.f64` +in the same block. The activation constants `%f989…%f992` are defined **once** in +phase 16's epilogue (s14672–s14681, paired with +`s14673 cvt.rn.f16.f32 low, %f989`) and are then read back by the same +`cvt.rn.f16.f32 low, %f989…%f992` sequence in every later activation epilogue — +first occurrence of `0f3ED306EB` after s14672 is none; e.g. E18 does +`s15069 cvt.rn.f16.f32 low, %f989`, `s15071 …, %f990`, `s15073 …, %f991`, +`s15075 …, %f992`. + +`rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, +`div.approx.ftz.f32` are always wrapped as `cvt.f32.f16 → op → cvt.rn.f16.f32`, so +each step is rounded through f16. + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). Neither dec3 + nor its siblings ever use the `.relu` form: the string `satfinite.relu` does not + occur in the entry. +* `cvt.rn.f16x2.e4m3x2` — the inverse (unpack one e4m3 byte pair to an f16x2). + +## 2. Phase table summary + +From `rr_layer_spec.py dec3`: 48 phases, 1112 `mma`. The tool prints M and N from +the count of *distinct* A and B fragments, so the identity +`M/16 * N/8 * K/32 == mma` is the check that the phase really is a dense GEMM: + +* holds for phases 2–9, 12–15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, + 43, 45, 47 (all `dense=True` in the tool); +* **fails for 19 phases — 1, 11, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, + 40, 42, 44, 46, 48** (tool `dense=False`). Example: P16 prints M=64 N=128 K=128 + (`4*16*4 = 256`) against 16 `mma`; the B operand of P16 has 16 fragments but only + 4 of them are used per A fragment (the C-chain is a 4-step cascade, §3/E16). + +Weight-image extent: the largest byte the entry reads from `W` is the second of +phase 48's two C seeds, `W + ((laneid<<2)&12) + 316432` (s19373), i.e. the image is +**at least 316436 bytes**. Phase 1's B block occupies `[0, 20480)` (40 +`ld.weak.global.ca.v4.u32` at `+0…+19968`, s440–s518), the score bias +`[81920, 82160]` (s527–s542), and the last weight tile `[314368, 315904]` +(s19359–s19366). + +**Phases that read no weight operand at all: 10 and 11.** Phase 10's A and B both +come from e4m3 packs of phase 8's D (E9), and phase 11's B is the `movmatrix` +transpose of registers (E10); see §3/E9, E10. + +## 3. Summary of epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s783–s9138 | 8357 | requantise P1's D, scatter to `SM`, read back, blend the `param+24` image, inverse-std, requantise, stage for P2 | +| E2–E8 | 7 stmts each | 7 | next-B weight loads only (s9164–s9356) | +| E9 | s9381–s9551 | 171 | score-bias C-seed loads + 80 packs of P8's D → P10 A and B | +| E10 | s9600–s13442 | 3843 | softmax of the 64×96 score block, V-transpose, pack | +| E11 | s13491–s13689 | 199 | stage P·V, P12 A from `SM`, next-B loads, column table + skip → P12 C | +| E12–E14 | 23 stmts each | 23 | P13/P14/P15 A from `SM` + next-B loads (s13706–s13806) | +| E15 | s13823–s14654 | 832 | RMS norm (², sum, rsqrt, gain) + packs + next B/C | +| E16 | s14671–s14959 | 289 | clamped cubic activation + column-bias add + packs + next B | +| E17 | s14976–s15051 | 76 | 32 packs → P18 A, next-B, next-C bias | +| E18 | s15068–s15235 | 168 | activation + packs + next B (no table add) | +| E19 | s15252–s15327 | 76 | 32 packs → P20 A, next-B, next-C bias | +| E20–E46 | 168/76 alternating | | the E18/E19 pair repeated for P20…P46 | +| E47 | s19116–s19373 | 258 | pack → plane-arena scatter (`param+48`) → next B/C | +| E48 | s19382–s19662 | 281 | `SM` stage, softmax over 5 taps, 3×3 texture gather, aux textures, surface write | + +--- + +## 4. The epilogues + +### E1 — s783–s9138: patch expand, image blend, inverse standard deviation + +This is 42.5 % of the entry. It is one long pipeline; the sub-ranges below are +maximal runs of one kind of work, all verified with the lineariser. + +Evidence: + +``` +s783 L3338 cvt.rn.satfinite.e4m3x2.f16x2 %rs248, %r924 +s787 L3349 mov.b32 %r10, {%rs250, %rs251} +s956 L3705 st.shared.v2.u16 [%r3583], {%rs248, %rs249} +s974 L3725 st.shared.u32 [%r3591+1600], %r10 +s1704 L4548 bar.sync 0 +s1748 L4601 ld.shared.v2.u16 {%rs346, %rs347}, [%r3927] +s2780 L5874 ld.param.u64 %rd3, [%rd1+-56] +s2936 L6041 ld.global.v2.u16 {%rs410, %rs411}, [%rd215] +s7176 L10529 cvt.rn.f16x2.e4m3x2 %r7510, %rs410 +s7307 L10916 add.f16 %rs600,%rs601,%rs602 +s7562 L11555 mul.f16 %rs984,%rs600,%rs600 +s7817 L12370 shfl.sync.bfly.b32 (first of 8) +s7874 L12518 mov.f64 %fd1, 0d3F20000000000000 +s8072 L13108 rsqrt.approx.ftz.f32 fl, fl +s8586 L13941 ld.global.v2.u16 {%rs2599, %rs2600}, [%rd283+82960] +s9018 L15205 shl.b32 %r8105, %r9, 11 +s9035 L15240 st.shared.v4.u32 [%r8109], {%r8113, %r8112, %r8111, %r8110} +s9099 L15355 st.shared.v4.u32 [%r8133+9728], {%r8149, %r8148, %r8147, %r8146} +s9104 L15361 bar.sync 0 +s9109 L15368 ld.shared.v4.u32 {%r25650, %r25651, %r25652, %r25653}, [%r25649] +s9137 L15399 ld.weak.global.ca.v4.u32 { %r8152,%r8153,%r8154,%r8155},[%rd284] +``` + +| range | stmts | what | operations (count) | +|---|---|---|---| +| s783–s924 | 142 | requantise **phase 1's D** pairs to e4m3 and pack them | 96 `cvt.rn.satfinite.e4m3x2.f16x2`, 46 `mov.b32` → `%r10…%r55`, plus the loose halves `%rs248/%rs249` (s783/s784) and `%rs342/%rs343` (s923/s924) | +| s925–s1703 | 779 | guarded scatter of the packed words into `SM` | 46 `st.shared.u32`, 2 `st.shared.v2.u16` | +| s1704 | 1 | `bar.sync 0` (L4548) | — | +| s1705–s2779 | 1075 | read back a window from `SM` | 32 `ld.shared.v2.u16` (s1748…s2779) | +| s2780–s2781 | 2 | **the `param+24` buffer pointer** | `ld.param.u64 %rd3, [%rd1+-56]`, `cvta` | +| s2782–s7175 | 4394 | clamped-coordinate gather from the `param+24` buffer | 32 `ld.global.v2.u16` (s2936…s7175) | +| s7176–s7304 | 129 | dequantise both sources | 128 `cvt.rn.f16x2.e4m3x2` → `%r7510…%r7637` | +| s7305–s7560 | 256 | blend staged value + image value | 260 `add.f16` → `%rs600, %rs603, %rs606 …` | +| s7561 | 1 | `bar.sync 0` (L11553) | — | +| s7562–s8067 | 506 | squares + in-lane sums | 384 `mul.f16`, 68 `add.f16x2`, 8 `shfl.sync.bfly.b32` (s7817…s7870) | +| s8068–s8580 | 513 | inverse standard deviation | 128 `rsqrt.approx.ftz.f32` (s8072…s8577) with 128 `cvt.f32.f16` / 128 `cvt.rn.f16.f32` | +| s8581–s8601 | 21 | per-column gain read | 16 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {82944…83184}` | +| s8602–s9034 | 433 | normalise and combine | `mul.f16` (e.g. s8795 `mul.f16 %rs2149,%rs600,%rs1765`) | +| s9035–s9099 | 65 | requantise and stage for phase 2 | 8 `st.shared.v4.u32` | +| s9104 | 1 | `bar.sync 0` (L15361) | — | +| s9106–s9133 | 28 | phase 2's A fragments | 24 `ld.shared.v4.u32` → `%r25650…%r25745` | +| s9134–s9138 | 5 | phase 2's B | 1 `ld.weak.global.ca.v4.u32` at `W + z*24576 + 83200 + 16*laneid` | + +**The scatter (s925–s1703).** The 48 stores are guarded by +`setp.gt.u32 %p, row, 9` / `…, col, 9` (s945, s947, s963, s965 …) and the store +index is `40*row + 4*col + t` bytes into a plane whose base is `{0, 1600, 3200, +4800, 6400, 8000, 9600, 11200}` — **8 planes of 1600 bytes = 12800 bytes, exactly +the whole shared array**. The plane offsets appear literally at s974 (`+1600`), +s1032 (`+3200`), s1050 (`+4800`), s1096 (`+6400`), s1114 (`+8000`), s1160 +(`+9600`), s1178 (`+11200`). `row` and `col` are not the natural coordinates of +`laneid`: they come out of a golden-ratio multiply, e.g. s929–s936 +`mul.wide.u32 %rd195, %r3340, -1431655765` / `shr.u64 %rd196, %rd195, 35` / +`mul.wide.u32 %rd197, %r56, -1431655765` / `shr.u64 %rd198, %rd197, 34`, i.e. the +emitted PTX walks the 10×10 grid in a permuted lane order. + +**The `param+24` gather (s2782–s7175).** `%rd1` is `param_0+80` (s4), so `%rd1-56` +is `param_0+24`; `%rd4 = cvta.to.global.u64(%rd3)` (s2781). Each of the 32 loads +computes a **clamped halo coordinate** from the block origin and `ex`/`ey`: the +pattern `add.s32 %r4243, %r2, %r403` / `abs.s32 %r4244, %r4243` / +`shl.b32 %r4245, %r3348, 1` / `sub.s32 %r4246, %r4245, %r4244` / +`add.s32 %r4247, %r4246, -2` / `min.s32 %r4248, %r4244, %r4247` / +`min.u32 %r4250, %r4249, %r4248` (s2793–s2800) mirrors the prologue's `A`-gather +(s42–s57) with a different row stride. The interior branch builds the index with +`shl.b32 %r4373, %r4372, 3` (s2956) then +`mad.lo.s32 %r4374, %r4364, %r7, %r4373` (s2957), where `%r7 = ex<<3` (s15), so the +buffer row stride is **8 u32 = 8 e4m3-words per image row**; one of the boundary +branches instead uses `shl.b32 %r4189, %r4188, 3` (s2906) with a literal 8. +The load itself is `mul.wide.u32 %rd214, %r26257, 4` / +`add.s64 %rd215, %rd4, %rd214` / `ld.global.v2.u16 {%rs410, %rs411}, [%rd215]` +(s2934–s2936), i.e. **one u32 (two f16) per image column position**, four columns +per lane group selected by `min.u32 %r4194, %r4193, 7` (s2911). + +**The blend (s7305–s7560).** The staged values coming out of `SM` are combined +with the buffer values: `mov.b32 {%rs601, %rs604}, %r7510` / +`mov.b32 {%rs602, %rs605}, %r7574` / `add.f16 %rs600,%rs601,%rs602` / +`add.f16 %rs603,%rs604,%rs605` (s7305–s7308). The results `%rs600…%rs957` +(**32 f16 pairs per lane**) are the layer's **skip/residual term**; they are read +much later, at s13595 (`add.f16 %rs4255,%rs6116,%rs600`) inside E11 and at s8795 +(`mul.f16 %rs2149,%rs600,%rs1765`). + +**The inverse-std block (s7561–s8580).** 384 `mul.f16` square the residual +(`mul.f16 %rs984,%rs600,%rs600`, s7563), the `add.f16x2`/`add.f16` tree folds +them, 8 `shfl.sync.bfly.b32` (s7817…s7870) sum across the four lanes of a row +segment, the constant `2⁻¹³` is added (s7874–s7875) and 128 +`rsqrt.approx.ftz.f32` (s8072…s8577) invert. The gain table is read at +`W + ((laneid<<2)&12) + {82944, 82960, … 83184}` (s8586–s8601, 16 loads, 16-byte +stride, last at 82944). So E1 computes, per output element, + +``` +acc = staged_SM_value + param24_buffer_value +inv = rsqrt.approx(f16(sum_lane(acc^2) + 2^-13)) +out = (acc * gain[col]) * inv // the mul.f16 at s8795 +``` + +**What is staged for phase 2 (s9035–s9133).** `%r8105 = %r9<<11` (s9018) and +`%r8107 = SM + %r8105` (s9019); the 8 `st.shared.v4.u32` write at +`SM + z*2048 + 16*laneid + {0,512,1024,1536}` for every `z` and at +`+{8192,8704,9216,9728}` only when `%r186 = z<<4` is `<= 31` (s9075–s9076), i.e. +only `z ∈ {0,1}`. After `bar.sync` (s9104) the 24 `ld.shared.v4.u32` at +`SM + 16*laneid + 512*i` (s9109–s9133) become **phase 2's A** `%r25650…%r25745`, +and the final `ld.weak.global.ca.v4.u32` (s9137) is phase 2's B. + +### E2–E8 — s9164…s9356: next-B weight loads only + +Each of these is exactly 7 statements: one `mov.u32 %laneid`-style setup, two +`add.s64` and two `ld.weak.global.ca.v4.u32` (4 fragments = 16 B registers), plus +the label. Example, E7 (s9318–s9324): + +``` +s9320 ld.weak.global.ca.v4.u32 { … }, [%rd, 177408+…]× // two 512-byte-strided loads +``` + +The B blocks, read verbatim off the phase table (the tool's `weight bytes` column +minus its usual +12 on the upper end), are `83200/83712` (P2), `87296/87808` (P3), +`84224/84736` (P4), `88320/88832` (P5), `85248/85760` (P6), `89344/89856` (P7), +`86272/86784` (P8), `90368/90880` (P9) — each read as `W + z*24576 + 16*laneid` plus +`{0, 512}`. Note the interleave: the even phases walk `83200, 84224, 85248, 86272` +and the odd phases `87296, 88320, 89344, 90368`, so the file's phase order is +(k0n0, k0n1, k1n0, k1n1, …) with the two n-groups stored contiguously. + +### E9 — s9381–s9551: score-bias seeds and 80 packs of phase 8's D + +171 statements, 24 weight loads + 80 packs. + +``` +s9381 L16841 mov.u32 %r10143, %laneid +s9384 L16845 add.s64 %rd300, %rd631, 8192 +s9385 L16847 ld.weak.global.ca.v4.u32 { %r10144,%r10145,%r10146,%r10147},[%rd300] +s9432 L16943 cvt.rn.satfinite.e4m3x2.f16x2 … // first of 80 packs +s9502 L17126 … // last pack group +``` + +* **24 loads** at `W + z*24576 + 16*laneid + 8192 + 512*i`, `i = 0…23` + (s9385…s9500) → **phase 10's C seeds** `%r10144…` (96 registers = 24 C pairs). + The byte block is `[8192, 20480)` inside the phase-2…9 weight group. Note this + is a different *kind* of C operand from phase 1's: phase 1 seeds each mma with a + single u32 duplicated into both halves (`{%r2453, %r2453}`, s543), loaded as 16 + `ld.global.u32` at `W + z*256 + ((laneid<<2)&12) + {81920…82160}` (s527–s542), + whereas phase 10 takes 24 full 512-byte tiles. +* **80 packs** whose sources are **phase 8's D** (`%r9654…%r9885`), not phase 9's: + `%r10686 = (pack(r9654), pack(r9674))` (s9434), `%r10696 = (pack(r9655), + pack(r9675))` (s9437), … They split into phase 10's A fragments + (`%r10432…%r10795`, 16 registers) and B fragments (`%r10686…%r10797`, 24 + registers = 12 fragments). Phase 9's own D (`%r9903…%r10134`) is not read here; + it reaches E10's `movmatrix` block instead (see E10). + +**The C-seed layout.** The four C registers of one mma are the four u32 of one +16-byte lane slot, and + +``` +C(m, n) = load_tile(4*(n>>1) + m) + 4*(n&1) [register index within the block] +byte = base + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1) +``` + +so the bias tile index runs `4*(n>>1) + m` (512-byte stride) over 4 m-tiles and 6 +`(n>>1)` groups = 24 tiles = 12288 bytes. Verified against phase 10's operands: +s9552 `C={%r10144,%r10145}`, s9553 `C={%r10152,%r10153}`, …, and the first block's +`%r10144` is the load at `+8192` (s9385) while `%r10152` is the load at `+8704` +(s9387). + +### E10 — s9600–s13442: softmax of the 64×96 score block, V-transpose, pack + +**Phase 10** = 48 `mma` of 64×96 with C = the 24 bias pairs (E9). The epilogue has +**no memory access at all** (0 `ld.*`, 0 `st.*`) and no `bar.sync`. + +``` +s9601 L17560 mov.f32 %f476, 0f3C8CCB50 +s9604 L17568 mul.f16x2 %r10802,%r10320,%r10801 +s9609 L17582 max.f16x2 %r10805,%r10802,%r10807 +s9614 L17596 min.f16x2 %r10808,%r10805,%r10810 +s9620 L17614 fma.rn.f16x2 %r10813,%r10808,%r10811,%r10816 +s9625 L17628 fma.rn.f16x2 %r10817,%r10808,%r10813,%r10820 +s9626 L17631 shl.b32 %r25746, %r10817, 5 +s9627 L17632 and.b32 %r12722, %r25746, 2145419232 // 0x7FE07FE0 +s11804 L24428 shfl.sync.bfly.b32 (first of 16) +s11813 L24452 add.f16 (first of 8) +s11934 L24754 rcp.approx.ftz.f32 (first of 192) +s12701 L25999 mul.f16 (first of 192) +s13179 L27053 movmatrix.sync.trans.aligned.m8n8.b16 %r13326, %r9903 (first of 48) +s13227 L27197 cvt.rn.satfinite.e4m3x2.f16x2 (first of 144 packs) +``` + +Sub-sections: + +| range | what | +|---|---| +| s9600–s11717 | 96 per-element groups: scale, clamp, cubic, exponent extract | +| s11718–s11801 | in-lane partial-sum trees (104 `add.f16x2`) | +| s11802–s11821 | 16 `shfl.sync.bfly.b32` → 8 row sums | +| s11822–s12700 | 192 `rcp.approx.ftz.f32` (s11934…) → 96 reciprocals | +| s12701–s13178 | 192 `mul.f16` → 96 probabilities | +| s13179–s13226 | 48 `movmatrix` transposing **phase 9's D** | +| s13227–s13442 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs | + +**(a) per-element exponent.** For each of the 96 f16x2 D registers, per half (an +f16 `x`): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) // s9604,s9609,s9614 +t = f16(m*(-m) + 0.92724609375) // s9620 +u = f16(m*t + 1.375) = f16(1.375 + m*(0.92724609375 - m²)) // s9625 +expval = f16 from bits ((bits(u)<<5) & 0x7FE07FE0) // 2^(32·frac(u) − 15) +``` + +This is **not `exp` and not `exp2(x·log2e)`**: the exponent is the cubic +`32*(0.375 + 0.92724609375·m − m³)` quantised to a 6-bit significand. The clamp +bounds are the guard: `d/dm[0.92724609375·m − m³]` vanishes at +`m = √(0.92724609375/3) = 0.55615…`, exactly the clamp, so the exponent saturates +at the top. + +**(b)/(c) row sums.** In-lane `add.f16x2` trees, then eight times: add the two +partials, butterfly over lane bits 0 and 1, `add.f16` the halves, broadcast. The +shuffles use the operands `%r11301 = 1` and `%r11310 = 2`. + +**(d)/(e) probabilities.** `rcp.approx.ftz.f32` (each as +`cvt.f32.f16 → rcp → cvt.rn.f16.f32`) on the 8 row sums, then +`p = expval * (1/rowsum)` with 192 `mul.f16`, so `Σ_j p_ij = 1` up to the +`rcp.approx` error. + +**(f) V-transpose.** 48 `movmatrix.sync.trans.aligned.m8n8.b16` on **phase 9's** +48 D registers. (The first is `s13179 L27053`.) + +**(g) packs.** 144 packs → phase 11's 12 A fragments (the probabilities) and 12 B +fragments (the transposed V). E11's A operand list (`%r13638…%r14041`, 48 +registers) and B operand list (`%r13932…%r14043`, 24 registers) confirm both. + +**There is no row maximum anywhere in this epilogue** — `max.f16x2` (96×) and +`min.f16x2` (96×) are the clamp of (a), and the only shuffles are the 16 +`shfl.sync.bfly` above. Contrast E48, which does have a real row max. + +### E11 — s13491–s13689: stage P·V, seed phase 12 + +199 statements. + +``` +s13491 L28036 bar.sync 0 +s13495 L28043 cvt.rn.satfinite.e4m3x2.f16x2 … // first of 32 packs +s13507 L28070 st.shared.v4.u32 [%r25875], {%r25879, %r25878, %r25877, %r25876} +s13547 L28158 bar.sync 0 +s13548 L28159 shl.b32 %r25892, %r9, 9 // z*512 +s13553 L28166 ld.shared.v4.u32 {%r25896, %r25897, %r25898, %r25899}, [%r25895] +s13558 L28174 ld.weak.global.ca.v4.u32 { %r14081,%r14082,%r14083,%r14084},[%rd324] +s13578 L28211 ld.global.v2.u16 {%rs6086, %rs6087}, [%rd637+181520] +s13594 L28228 add.f16 %rs4258,%rs6117,%rs603 +s13595 L28232 add.f16 %rs4255,%rs6116,%rs600 +``` + +* s13491 `bar.sync`; then 32 `cvt.rn.satfinite.e4m3x2.f16x2` packing phase 11's D + (`%r13606, %r13666, %r13646, %r13846, …`) and 4 (or 5, when the extra store group + runs) `st.shared.v4.u32` into `SM + z*2048 + 16*laneid` at `+{0,512,1024,1536}` + (s13507, s13520, s13533, s13546); +* s13547 `bar.sync`; s13548–s13549 `%r25893 = SM + z*512`; +* s13553 `ld.shared.v4.u32` at `SM + z*512 + 16*laneid` → **phase 12's A fragment + #0** (`%r25896…%r25899`); +* s13558–s13572, **8 weight loads** at `W + 16*laneid + {103680, 104192, 105216, + 105728, 106240, 106752, 107264}`… → phase 12's B (16 fragments = 32 registers); +* s13578–s13593, **16 table loads** at `W + ((laneid<<2)&12) + {181504, 181520, … + 181744}` (16-byte stride) → 32 f16 per lane = a per-column table; +* s13594–s13689, **64 `add.f16`** → 32 b32 `%r14122…%r14273` = **phase 12's C + seeds**, exactly `table[col] + residual`, e.g. s13595 + `add.f16 %rs4255,%rs6116,%rs600` where `%rs600` is the **E1 residual**. + +So `phase 12: D = A·B + (skip_residual + column_table)`. + +### E12–E14 — s13706–s13806: A from `SM` + next-B, three times + +23 statements each, one `ld.shared.v4.u32` (one A fragment: `%r25903…%r25906` in +E12, `%r25909…%r25912` in E13, `%r25915…%r25918` in E14) plus 8 +`ld.weak.global.ca.v4.u32` for the next phase's B (16 fragments = 32 registers, +e.g. `%r14276…%r14307`). The shared base is the same `SM + z*512 + 16*laneid`. + +Together with E11, this supplies the four A k-fragments of phases 12–15, which are +one GEMM 16×128×128 split across four `mma` phases chained through C +(P12 C = the E11 seeds; P13 C = P12's D; P14 C = P13's D; P15 C = P14's D — the +operand sets in §2's summary table). + +### E15 — s13823–s14654: RMS norm before the MLP + +832 statements, no stores. + +``` +s13825 L29094 mov.b32 {%rs5256, %rs5259}, %r14696 // first of 302 +s13826 L29096 mul.f16 %rs4450,%rs5259,%rs5259 // first of 192 squares +s13987 L29541 shfl.sync.bfly.b32 (first of 4) +s14018 L29618 cvt.rn.f16.f64 %rs4645, %fd1 // eps = 2^-13 +s14118 L29915 rsqrt.approx.ftz.f32 fl, fl // first of 64 +s14371 L30325 ld.global.v2.u16 {%rs6118, %rs6119}, [%rd646+181776] // first of 16 gain loads +s14583 L30924 ld.weak.global.ca.v4.u32 … // first of 8 next-B loads (182016+512*i) +s14603 L30961 ld.global.u32 %r15124, [%rd651+186112] // phase 16's C bias words +s14607 L31227 cvt.rn.satfinite.e4m3x2.f16x2 … // first of 32 packs +``` + +| range | stmts | op | +|---|---|---| +| s13823–s14010 | 188 | 192 `mul.f16` — squares of phase 12–15's D halves | +| s14011–s14017 | 7 | `add.f16` / `add.f16x2` in-lane pairwise sums | +| s13981–s14009 | — | 9 `mov.u32` lane-shift setup, 4 `or.b32`, 4 `shfl.sync.bfly.b32` (s13987…) | +| s14116–s14135 | — | 64 `cvt.f32.f16` → 64 `rsqrt.approx.ftz.f32` (s14118) → 64 `cvt.rn.f16.f32` | +| s14371–s14386 | 16 | gain loads `W + ((laneid<<2)&12) + {…}` (16 loads, 16-byte stride) | +| s14583–s14606 | 24 | 8 `ld.weak.global.ca.v4.u32` (phase 16's B, `182016 + 512*i`, s14583–s14597) then 4 `ld.global.u32` at `186112/186128/186144/186160` (phase 16's C bias, s14603–s14606) | +| s14607–s14653 | 47 | 32 packs → phase 16's A | + +**What it computes.** For each row a lane holds: +``` +sumsq[row] = Σ_c x[row,c]² (f16, in-lane tree + 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2^-13))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` +with **no mean subtraction and no `1/N`** — the quantity is the raw sum of squares +plus `2^-13`. The eps is materialised at s14018 (`cvt.rn.f16.f64 %rs…, %fd1`, and +`%fd1 = 0d3F20000000000000` at s7874). The gain is the **same shape of table as +E1's** (`W + ((laneid<<2)&12) + off`) and the norm's bias is not added here: it is +folded into phase 16's C operand, loaded by the 4 `ld.global.u32` at s14603. + +### E16 — s14671–s14959: clamped cubic activation + column bias + +289 statements. + +``` +s14671 L31190 mov.u32 %r15275, %laneid +s14672 L31192 mov.f32 %f989, 0f3ED306EB +s14673 L31195 cvt.rn.f16.f32 low, %f989 // first of 32 constant→f16 converts +s14684 L31221 neg.f16x2 %r15280,%r15279 // first of 8 +s14685 L31225 max.f16x2 … // first of 8 +s14686 L31229 min.f16x2 … // first of 8 +s14687 L31233 abs.f16x2 … // first of 8 +s14688 L31237 mul.f16x2 %r15290,%r15277,%r15288 // first of 24 +s14689 L31241 sub.f16x2 … // first of 8 +s14691 L31249 add.f16x2 … // first of 8 +s14814 L31680 add.s64 %rd653, %rd2, %rd652 // column-table addressing +s14816 L31683 ld.weak.global.ca.v4.u32 { %r15509,%r15510,%r15511,%r15512},[%rd364] // first of 8, 186176+512*i +s14836 L31720 ld.global.v2.u16 {%rs6150, %rs6151}, [%rd656+190288] // first of 16 table loads +s14852 L31737 add.f16 %rs5257,%rs6181,%rs5259 // first of 64 bias adds +s14948 L32025 cvt.rn.satfinite.e4m3x2.f16x2 %rs5447, %r15418 +s14950 L32030 mov.b32 %r15702, {%rs5446, %rs5447} +``` + +Per element, over each of the 8 f16x2 groups of phase 16's D: + +``` +y = clamp(x, -2, +2) // neg/max/min, s14684–s14686 +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // abs/mul/sub/mul/add, s14687–s14691 +out = x * g // mul.f16x2, s14688/s14691 chain +``` + +`g` is a **cubic ramp, not a sigmoid**: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`; `g(1) = 0.831055` where `x·sigmoid(x) = +0.730957`. **Reproduce the formula, not SiLU/GELU.** + +Then (s14836–s14851) the 16 table loads +`ld.global.v2.u16 … [%rd656+190288]` (s14836, the first, at a 16-byte stride, so 32 +f16 per lane = a per-column table, using the same +`W + ((laneid<<2)&12) + off` pattern as E1/E11/E15) and 64 `add.f16` +(s14852–s14939) write the table over the activation **inputs**: +`s14940 add.f16 %rs5428,%rs6176,%rs5430` / `s14941 mov.b32 %r15699, {%rs5428, +%rs5431}` → `%r15699`, `%r15708`, `%r15709`, … are **phase 17's C seeds**. The +final 8 packs (s14948–s14959) build **phase 17's A**: `%r15702 = (pack(r15302), +pack(r15418))` (s14950), `%r15704 = (pack(r15331), pack(r15447))` (s14953), +`%r15703 = (pack(r15360), pack(r15476))` (s14956), `%r15705 = (pack(r15389), +pack(r15505))` (s14959). The 8 `ld.weak.global.ca.v4.u32` from s14816 are phase +17's B block `[186176, 190284)`: s14815 `add.s64 %rd364, %rd653, 186176`, then +`+512` per load up to `+189760` at s14829. + +### E17 — s14976–s15051: packs, then next B/C + +76 statements, identical form to E12–E14 plus packs: + +``` +s14980 L32171 ld.weak.global.ca.v4.u32 { %r15711,%r15712,%r15713,%r15714},[%rd37…] // first of 8 +s15000 L32208 ld.global.u32 %r15785, [%rd661+194624] // first of 4 next-C bias words +s15004 L32213 cvt.rn.satfinite.e4m3x2.f16x2 %rs5455, %r24985 // first of 32 packs +``` + +32 packs (16 b32) → **phase 18's A**; 8 `ld.weak.global.ca.v4.u32` → phase 18's B +block `[190528, 194636)`; 4 `ld.global.u32` at `W + ((laneid<<2)&12) + +{194624,194640,194656,194672}` → phase 18's C bias (s15000 is the first, at +`+194624`). + +### E18 — s15068–s15235: activation, no column bias + +168 statements, the E16 formula without the table add: + +``` +s15068 L32437 mov.u32 %r15936, %laneid +s15069 L32441 cvt.rn.f16.f32 low, %f989 // 32 constant→f16, reusing %f989…%f992 +s15077 L32464 neg.f16x2 %r15941,%r15940 +s15078 L32468 max.f16x2 %r15943,%r15836,%r15941 +s15079 L32472 min.f16x2 %r15946,%r15943,%r15940 +s15080 L32476 abs.f16x2 %r15949,%r15946 +s15081 L32480 mul.f16x2 %r15951,%r15938,%r15949 // first of 24 +s15209 L32926 ld.weak.global.ca.v4.u32 { %r16170,%r16171,%r16172,%r16173},[%rd38…] // 8 next-B loads +s15224 L32957 cvt.rn.satfinite.e4m3x2.f16x2 %rs5487, %r16079 // 8 packs → 1 A fragment +``` + +There is **no `ld.global.v2.u16`** in this epilogue, i.e. no per-column table add: +the residual for this branch is carried entirely by the C operand that E17 loaded. + +### E19 — s15252–s15327: packs, then next B/C + +76 statements, byte-identical in shape to E17: + +``` +s15256 L33103 ld.weak.global.ca.v4.u32 { %r16371,%r16372,%r16373,%r16374},[%rd388] // first of 8 +s15276 L33140 ld.global.u32 %r16445, [%rd668+202880] // first of 4 next-C bias words +s15280 L33145 cvt.rn.satfinite.e4m3x2.f16x2 %rs5495, %r24985 // first of 32 packs +``` + +The 8 weight loads are `W + z*24576 + 16*laneid + 198784 + 512*i`, i.e. **phase +20's B block** `[198784, 202892)`; the 4 `ld.global.u32` at +`202880/202896/202912/202928` are phase 20's C bias (`202880..202928`). + +**E20 … E46.** The pattern `(activation, no table) → (32 packs + next B/C)` +repeats with a period of two phases. Numbering the phases, not the epilogues: the +**even** phases 16, 18, …, 46 each have a 289/168/…-statement **activation** +epilogue; the **odd** phases 17, 19, …, 45 each have a 76-statement **pack** +epilogue. The occurrence of each is fixed by the classification the tool prints +(`… / after phase N … e4m3-pack:32@sNNNN` for odd N, `… normalise/pack` for even N). + +The per-phase B blocks advance by 4096/4160 alternately, i.e. **8256 bytes per +two-phase pair**: + +``` +P16 [182016,186124) P17 [186176,190284) P18 [190528,194636) P19 [194688,198796) +P20 [198784,202892) P21 [202944,207052) P22 [207040,211148) P23 [211200,215308) +P24 [215296,219404) P25 [219456,223564) P26 [223552,227660) P27 [227712,231820) +… P47 [310272,314380) P48 [314368,316428) +``` + +Each epilogue loads the block of the phase that *follows* it, and that phase's C +bias words live in the 64 bytes immediately above its B block (e.g. phase 18's C is +at `194624..194672`, loaded at s15000). Only **E16** has the column-table add +(`ld.global.v2.u16`); every other activation epilogue (E18, E20, …, E46) has none. + +#### Shape of the whole tail (E11–E48) + +``` +E11 stage P·V → SM; A12 = ld.shared(SM); C12 = E1_skip + table@181504 +P12..P15 one GEMM 16×128×128 in four k-chained phases → D15 +E15 RMS norm on D15 (eps 2^-13, gain@…), no mean + ├─ pack → P16 A (ld.shared) P16: C = norm-bias@(4 ld.global.u32) → activation (E16) + table → P17 C + │ pack → P17 A + ├─ P17: 16×128, C = E16 seeds, packs → P18 A (E17) + ├─ P18: activation on its own D (E18), packs → P19 A + └─ … 14 more (activation, pack) pairs, each with its own weight block +E47 pack → plane arena (`param+48`) +E48 SM stage, softmax over 5 taps, 3×3 texture gather, aux textures, surface write +``` + +### E47 — s19116–s19373: pack → plane-arena scatter → next B/C + +258 statements. + +``` +s19116 L46145 cvt.rn.satfinite.e4m3x2.f16x2 %rs6055, %r25470 // first of 32 packs +s19164 L46256 ld.param.u64 %rd763, [%rd8+48] // S = plane arena +s19165 L46257 cvta.to.global.u64 %rd5, %rd763 +s19167 L46261 shr.u32 %r639, %r25642, 2 // g = laneid>>2 +s19168 L46262 and.b32 %r640, %r25642, 3 // t = laneid&3 +s19170 L46264 and.b32 %r25951, %r639, 7 +s19171 L46265 add.s32 %r25952, %r622, %r25950 // y +s19183 L46277 mad.lo.s32 %r641, %r7, %r25952, %r25959 // idx +s19190 L46285 st.global.u32 [%rd765], %r623 // first of 16 stores +s19359 L46487 add.s64 %rd796, %rd801, 314368 +s19360 L46489 ld.weak.global.ca.v4.u32 { %r25994,%r25995,%r25996,%r25997},[%rd796] // next B +s19372 L46510 ld.global.u32 %r26020, [%rd805+316416] // next C seed +``` + +* 32 packs → 16 b32 `%r623…%r638`, which are simultaneously **phase 48's A + fragments** (see E48) — the same 16 registers are scattered to memory and fed to + the last GEMM. +* `S = cvta.to.global.u64(param_0+48)` (s19164–s19165) — the entry's only read of + `param_0+48`. +* **16 `st.global.u32`** (s19190…s19348), each guarded by + `setp.lt.s32 %p, y, 0` / `setp.ge.u32 %p, y, ey` / `setp.gt.u32 %p, laneid, 63` / + `setp.lt.s32 %p, x, 0` / `setp.ge.u32 %p, x, ex` combined with `or.pred` + (s19172–s19181) and a `selp.b32 %r642, -1, %r25960, %p1` + `setp.lt.s32 … -1` + + `bra` (s19185–s19187) that turns a guard failure into "skip the store". + + The store index is `idx = (8*ex)*y + 8*x + d` with `%r7 = ex<<3` (s15), + `y = %r622 + (laneid>>5)`, `x = %r1 + ((laneid>>2)&7)`, `d = t` (s19183–s19184) + — the same formula as enc0's E20 (§4 of the enc0 file). +* after the stores: 4 `ld.weak.global.ca.v4.u32` at + `W + 16*laneid + {314368, 314880, 315392, 315904}` (s19360–s19366) = phase 48's B + (8 fragments = 16 registers), and 2 `ld.global.u32` at + `W + ((laneid<<2)&12) + {316416, 316432}` (s19372–s19373) = phase 48's C seeds. + +### E48 — s19382–s19662: softmax over five taps, 3×3 texture gather, surface write + +281 statements; the entry's last statement is `s19663 L47124 ret`. + +``` +s19382 L46568 bar.sync 0 +s19387 L46575 add.s32 %r26096, %r670, %r26211 +s19393 L46581 st.shared.u32 [%r672], %r26071 +s19397 L46586 st.shared.u32 [%r672+16], %r26081 +s19414 L46606 mov.b64 %rd835, param_0 +s19432 L46624 ld.param.v2.u32 {%r26129, %r26130}, [%rd835] // ex, ey +s19438 L46631 mov.b64 %rd836, param_0 +s19449 L46642 ld.param.u64 %rd830, [%rd836+112] // output surface +s19452 L46646 max.f16x2 %r26131,%r26132,%r26133 // first of 4 +s19456 L46659 max.f16 %rs6182,%rs6183,%rs6184 +s19458 L46666 mov.b32 %r26154, {%rs6185, %rs6185} // broadcast row max +s19462 L46676 mul.ftz.f32 %f1033, %f993, 0f3FB8AA3B // ×log2e +s19463 L46677 ex2.approx.ftz.f32 %f995, %f1033 +s19519 L46796 mov.f32 %f1032, 0f3F800000 +s19520 L46797 div.approx.ftz.f32 %f1011, %f1032, %f1050 // 1/rowsum +s19544 L46845 ld.param.v2.f32 {%f1052, %f1053}, [%rd836+136] +s19546 L46847 fma.rn.ftz.f32 %f1012, %f1052, %f1051, %f1056 // sx*(i+0.5) +s19550 L46851 ld.param.u64 %rd823, [%rd836+88] // low-res texture +s19552 L46854 tex.base.2d.v4.f16.f32 {%rs6210,%rs6211,%rs6212,%rs6213}, [%rd807, {%f1012,%f1013}] +s19626 L47026 ld.param.u64 %rd825, [%rd836+96] +s19627 L47028 tex.base.2d.v4.f16.s32 {%rs6354,%rs6355,%rs6356,%rs6357}, [%rd825, {%r677,%r678}] +s19628 L47030 ld.param.u64 %rd827, [%rd836+104] +s19629 L47032 tex.base.2d.v4.f16.s32 {%rs6358,%rs6359,%rs6360,%rs6361}, [%rd827, {%r677,%r678}] +s19644 L47079 set.nan.f16.f16 %rs6389,%rs6358,%rs6358 +s19647 L47086 add.f16 %rs6411,%rs6411,%rs6358 // only if not NaN +s19659 L47117 shl.b32 %r26200, %r677, 3 // 8*x +s19661 L47120 sust.b.2d.v4.b16.zero [%rd830, {%r26200,%r678}], {%rs6411,%rs6412,%rs6413,%rs6410} +``` + +Sub-sections: + +| range | stmts | what | +|---|---|---| +| s19382–s19413 | 32 | `bar.sync` + stage phase 48's D into `SM` at `(48*y + 6*x)` slots | +| s19414–s19437 | 24 | `param_0` reload, `(ex, ey)` read, bounds guard (`tid.z > 1` or x/y out of range → skip to `$L__BB1_646`) | +| s19438–s19448 | 11 | surface pointer `param+112`, 5 `ld.shared.u32` reading **5 consecutive taps** | +| s19449–s19530 | 82 | row max over the 5 taps, `2^((v-max)·log2e)` softmax, `div.approx` reciprocal | +| s19531–s19543 | 13 | clamped coordinates `clamp(p-1, 1, ex-2)` / `clamp(p-1, 1, ey-2)` | +| s19544–s19549 | 6 | `param+136` scale pair → normalized `u = sx·(i+0.5)`, `v = sy·(j+0.5)` | +| s19550–s19625 | 76 | 9 `tex.base.2d.v4.f16.f32` at the 3×3 stencil of `param+88`, accumulated with `fma.rn.f16` (30 in total) | +| s19626–s19629 | 4 | `param+96` and `param+104` textures at the integer coordinate `(x, y)` | +| s19630–s19643 | 14 | `sigmoid`-like `div.approx` blend: `out = acc·σ + tex·(1-σ)` (e.g. s19638 `mul.f16 %rs6368,%rs6342,%rs6363`, s19639 `fma.rn.f16 %rs6411,%rs6354,%rs6365,%rs6368`) | +| s19644–s19658 | 15 | per-channel NaN guard on the `param+104` texture: `set.nan.f16.f16` → `setp.ne.s16` → `@p bra` → `add.f16` | +| s19659–s19661 | 3 | `8*x` and the `sust.b.2d.v4.b16.zero` surface write | + +**Where the +96/+104 reads go.** Both are `tex.base.2d.v4.f16.s32` reads at the +same integer coordinate `{%r677, %r678}` = `(x, y)` of the block: +`param+96`'s three channels `%rs6354/%rs6355/%rs6356` are added unconditionally +(s19639–s19643), while `param+104`'s three `%rs6358/%rs6359/%rs6360` are added +**per channel only when the channel is not NaN** (s19644–s19658). The surface +written is `param+112` (s19449), and the write lands at `(8·x, y)` (s19659–s19661), +tap `%rs6410 = 0` in the fourth channel. + +**What the +24 skip input supplies.** `param_0+24` (reached as `%rd1-56`, s2780) +supplies the f16 image values that E1 adds to the shared-staged features +(s7307 onward) to form the residual `%rs600…%rs957`. That residual is (i) the +`mul.f16` input at s8795 in E1's normalisation, and (ii) added to the per-column +table at `W+181504` in E11 (s13594–s13689) to seed phase 12's C operand. + +## 5. The plane-arena writes (`param_0+48`) + +`S = cvta.to.global.u64(%rd763)` with `%rd763 = ld.param.u64 [%rd8+48]` +(s19164–s19165) is the **only** occurrence of `param_0+48` in the entry. There are +exactly two store groups in the whole entry: + +**(i) E47, 16 × `st.global.u32 [%rd5 + 4*idx], v`.** Statement and value of each +store, in file order: + +| # | stmt | line | value | # | stmt | line | value | +|---|---|---|---|---|---|---|---| +| 1 | s19190 | L46285 | `%r623` | 9 | s19286 | L46397 | `%r631` | +| 2 | s19199 | L46296 | `%r624` | 10 | s19294 | L46407 | `%r632` | +| 3 | s19232 | L46331 | `%r625` | 11 | s19304 | L46419 | `%r633` | +| 4 | s19240 | L46341 | `%r626` | 12 | s19312 | L46429 | `%r634` | +| 5 | s19250 | L46353 | `%r627` | 13 | s19322 | L46441 | `%r635` | +| 6 | s19258 | L46363 | `%r628` | 14 | s19330 | L46451 | `%r636` | +| 7 | s19268 | L46375 | `%r629` | 15 | s19340 | L46463 | `%r637` | +| 8 | s19276 | L46385 | `%r630` | 16 | s19348 | L46473 | `%r638` | + +``` +idx = (8*ex)*y + 8*x + d, guard y >= 0, y < ey, laneid <= 63, x >= 0, x < ex +y = %r622 + (laneid>>5), x = %r1 + ((laneid>>2)&7), d = t (odd stores) | d = t|4 (even stores) +where t = laneid&3, ex = %r3347, ey = %r3348, %r1 = block origin x (s7), + %r622 = %r2 + 2*%r9 (s13823–s13824: `shl.b32 %r25919, %r9, 1` then + `add.s32 %r622, %r2, %r25919`), i.e. the y origin also carries the slab index. +``` + +(The 16 indices are all built from the single `%r641 = %r7*%r25952 + %r25959` +computed at s19183, with `%r25959 = x<<3` and the second of each pair differing by +`or.b32 %r643, %r640, 4`, s19192.) The stores write 4 bytes × 32 lanes × 16 = +2048 bytes per block of phase 47's requantised output. + +**(ii) E48, the shared staging** at s19393/s19397/s19410/s19412: `st.shared.u32` +into `SM`, not the arena. + +**What is written:** phase 47's requantised 16×128 output. **What reads it back:** +nothing inside this kernel — `param_0+48` is never the base of an `ld.*` in the +entry, and phase 48's A comes from registers (`%r623…%r638`, E47's own packs). +See §6. + +## 6. Uncharacterised + +**U1. The shared-memory layout of E1's first scatter.** The 48 stores write +`40*row + 4*col + t` bytes into one of 8 planes of 1600 bytes (offsets literal at +s974, s1032, s1050, s1096, s1114, s1160, s1178), with `row`/`col` produced by a +golden-ratio permutation of `laneid` and `%r9` (s929–s936). I did not reduce that +permutation to a closed form in `(laneid, %r9)`, so I cannot say which element of +the 96×128 tile each plane holds. *Missing:* either the layout of the producer's +`mma` D fragments in the destination tile, or a run with a shared-memory dump. + +**U2. The 12 `%r8xxx` gain/normalisation wiring inside E1.** E1 has 384 `mul.f16` +and 260 `add.f16` spread over s7305–s9034; I traced the first of each chain +(s7307, s7563, s8795) but not all 644. *Missing:* a dataflow dump of the f16 +halves. + +**U3. The identity of the per-column tables.** `W+181504` (E11), +`W+39296/39312/39328/39344` (E16), `W+82944…83184` (E1's gain), +`W+…` (E15's gain) are all read with the same `W + ((laneid<<2)&12) + off` pattern. +Their *role* is computable (E11: added to the skip before phase 12; E16: added +after the activation; E1/E15: multiply the inverse std) but their *names* are not. +The same is true of the GEMM biases at `81920…82160` (P1), `8192…20480` (P10), +`103680…107264`-adjacent words (P12), `316416/316432` (P48). *Missing:* the weight +image's layout description (the `_prep` permutation) or the model's parameter names. + +**U4. The identity of the 12288-byte score bias.** Phase 10 adds a 12288-byte f16 +table (`W + z*24576 + 8192 … +20480`) as its GEMM C operand, laid out as §4/E9 +describes. Whether it is a relative position bias, a learned score bias, or a +per-lane constant cannot be decided from the PTX. + +**U5. The geometry of the banded phases.** Nineteen phases print an M/N/K that +fails `M/16·N/8·K/32 == mma` (P1, 11, 16–46 even, 48). For P16/P18/…/P46 I traced +the cascade explicitly (D_m = A_m·B_m + D_{m-1} over the 4 A fragments, so the +*effective* per-phase shape is a 4-step prefix sum, not 64×128×128), and for P48 +likewise (4 A fragments, 8 mma). For **P1** (5-step cascades, 24 groups of 10) and +**P11** (48 mma, C set of 65 registers) I did not reduce the full (M,N,K) reading. +The epilogue contracts above do not depend on resolving this. + +**U6. The logical meaning of E48's blend.** E48 computes +`out = acc·σ(t) + tex96·(1-σ(t))`, plus `tex104` per channel under a NaN guard, and +writes the low-res feature `acc` obtained by a 3×3 `tex.base.2d.v4.f16.f32` gather +weighted by a 5-tap softmax. The PTX gives the arithmetic exactly but not which +model term this is. *Missing:* the high-level source or a reference implementation. + +**U7. `%r9`'s range.** dec3 has no guard on `%r9 = %tid.z` (s433), unlike dec4 +(`setp.gt.u32 %p3, %r9, 3`). Since `SM` is 12800 bytes and the E1 store bases step +by 2048, the usable `%r9` range is bounded by `z*2048 + 2032 < 12800`, i.e. +`z <= 5`, but nothing in the PTX states it. *Missing:* the launch configuration. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| patch expand | §4/E1 (s783–s9138), and phase 1 itself (§2) | +| the norms | E1's rsqrt block (s7562–s8580, eps s7874) and E15 (s13823–s14654, eps s14018) | +| the attention | E9 (score seeds + packs), E10 (softmax + movmatrix + packs), E11 (P·V staging) | +| the activations | E16, E18, …, E46 — the clamped cubic `x·(0.5 + y·(0.412109375 − 0.0810546875·|y|))`, `y = clamp(x,±2)`; constants s14672–s14681 | +| the per-launch table in the plane arena | §5, s19164/s19190–s19348 (`param_0+48`) | +| every epilogue of every phase | §3 summary table + §4 (E1–E48) | +| texture reads at +96/+104 and where the surface write goes | §4/E48, s19626–s19629 and s19449/s19661 | +| what the skip input at +24 supplies | §1.1 (s4, s2780) and §4/E1, E11 | +| phase table M/N/K arithmetic checked | §2 (19 phases fail; listed) | +| weight-image extent | §2 (≥ 316436 bytes; last read s19373) | +| phases with no weight operand | §2: 10 and 11 | +| uncharacterised | §6 | diff --git a/kernels/rr/rrswin_dec4.hip b/kernels/rr/rrswin_dec4.hip new file mode 100644 index 0000000..a9d7480 --- /dev/null +++ b/kernels/rr/rrswin_dec4.hip @@ -0,0 +1,410 @@ +// Native replacement for the Ray Reconstruction denoiser's last Swin decoder, +// cuda_dldn_engine_swin_dec4_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the mirror-cut frame is in place, builds, and *runs* (measured exit 0, +// after carrying the epilogue's six live registers across the cut -- see +// swin_dec4_recipe.py's RET_REGS). Phase 1 (the patch-expand GEMM, 300 mma in +// sixty independent five-step chains) is implemented, but it is NOT yet validated: +// the debug payload cannot be extracted from the launch dumps yet, because the +// bridge deduplicates param_0+48 against arg008's allocation and never writes that +// allocation out, so the oracle's store lands outside every dumped file. Phases +// 2-62 are unimplemented, so the six registers that cross the cut back are still +// lane-distinct placeholders and the layer's surface output does not match the +// translated kernel (compare_launch_dump: arg112 DIFFERS, arg120 ok). +// +// dec4 is the widest of the eleven layers: the attention/MLP width is 160 (dec3's +// is 128), so no count here is interchangeable with another layer's. It has 62 +// phases and 1606 mma against enc0's 22 and 536, and its E1 alone is 44% of the +// entry. +// +// The kernel is one warp per 8x8 token patch with eight waves per block, block z +// selecting the slab (%r9 = %tid.z, guarded to 0..3). The PTX this file replaces +// is kernels/extracted/rr/0019-PREPASS_ENTRYPOINT_NAME.ptx. +// +// kernels/tex/make_ptx.py's recipe (kernels/rr/swin_dec4_recipe.py) keeps +// NVIDIA's texture prologue (file lines 1-1706) and surface epilogue (from line +// 58080) and replaces the 1606 mma of the 62 phases (lines 1707-58079) with the +// call below. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. dec4's block is 144 bytes. +struct DldnSwinDec4Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinDec4Params) == 144, "parameter block"); + +enum : int +{ + kPlaneArg = 48, // plane arena the decoder writes (arg048), also the debug base's arena +}; + +// The shared scratch the six registers the surviving epilogue reads cross the cut +// through: the top 768 bytes of `SM` (16384 bytes), twenty-four bytes per lane, at +// 15616. See swin_dec4_recipe.py (RET_BASE, RET_REGS) for why the top of the array is +// free -- SM itself is *not* dead after the cut, E62 reads it back at line 58152, but +// its deepest reach is 6328. A base past 15616 is out of bounds of the array, and the +// compiler then proves the store undefined and drops the whole body, so this constant +// has to match the recipe's. +enum : int +{ + kRetBase = 15616, + kRetStride = 24, +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// The weight image is prepared: `NAME_prep` may permute it once, so the native side +// consumes it in the fragment order its own gemm wants rather than NVIDIA's. What +// follows is the mapping the *splice's* own reading of the image implies. +// +// Phase 1's B block is 25600 bytes: fifty 512-byte tiles at +// `W + z*25600 + 16*laneid + 512*i` (file lines 1478-1674), i.e. one tile per two +// B fragments, read as `ld.weak.global.ca.v4.u32` four b32 at a time. The hundred +// B fragments (%r1017..%r1216, two b32 each) are the mma's B operands in order. +// +// Within one 512-byte tile, byte j of a lane's sixteen holds the e4m3 for the +// (k, n) pair +// byte = 64*(n & 7) + 8*((n >> 3) & 1) + 16*((k >> 1) & 3) +// + 4*((k >> 3) & 1) + 2*((k >> 4) & 1) + (k & 1) +// and `16*laneid` is the tile's lane stride. VERIFIED: this is a bijection from the +// 512 (k, n) pairs of a tile onto the tile's 512 bytes, and it agrees with the +// fragment layout enc0's waddr() encodes for the same mma shape (checked over all +// 1024 pairs of a two-tile block), so the two layers' readers see one image. +// +// n here is the *tile-local* column: tile t covers n = 16*t .. 16*t+15, so a phase +// whose B block starts at `base` addresses column `n` of the phase at +// waddr(base, k, n) with n already phase-relative. +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 64u * (uint32_t)(n & 7) + 8u * (uint32_t)((n >> 3) & 1) + + 16u * (uint32_t)((k >> 1) & 3) + 4u * (uint32_t)((k >> 3) & 1) + + 2u * (uint32_t)((k >> 4) & 1) + (uint32_t)(k & 1); +} + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the mma's k-split needs. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// the low f16 of a packed pair +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// One mma.m16n8k32.row.col.f16.e4m3.e4m3.f16 step, the shape every phase of dec4 +// uses: sixteen rows, eight columns, K=32, e4m3 in, f16 out. +// +// `a` is the A fragment (four b32) in the hardware order enc0's comment documents: +// A reg 0 -> row g, k = 2t + (j&1) + 16*((j>>1)&1), byte j = 0..3 +// A reg 1 -> row g+8, same k +// A reg 2 -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// A reg 3 -> row g+8, same k +// and the B half that pairs with a0/a1 is b0, with a2/a3 is b1: +// B byte j (j<4) -> n = 16*tt + 8*(b>>3) + g, k = 2t + (j&1) + 16*((j>>1)&1) +// B byte j (j>=4) -> same n, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// with b the byte index within the lane's sixteen and tt the 512-byte tile. +// +// `bv[2][32]` is therefore the lane's own two columns of the eight, over all 32 k, +// read straight from the weight image; the four lanes that differ in t hold the four +// disjoint eighths of each row's k, so the A side needs both butterfly steps to see +// all 32 k for its own t. +// +// `d` receives the two b32 the mma writes: d[0] is (row g, cols 2t, 2t+1) and d[1] +// is (row g+8, the same two columns), matching the PTX's D-register order. +// +// `c0`/`c1` are the C operand's two b32 (or zero for an unseeded step). e4m3 x e4m3 +// products are exact and 32 of them sum exactly in f32, so the dot product is a plain +// f32 accumulation rounded to f16 once -- what the translated mma does. +DEVF void mma_step(const uint32_t* a, const float bv[2][32], uint32_t c0, uint32_t c1, + uint32_t d[2]) +{ + const int t = (int)(lane_id() & 3); + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + const uint32_t p0 = a[2 * reg + row]; + const uint32_t p[4] = {p0, bfly1_bits(p0), bfly2_bits(p0), bfly1_bits(bfly2_bits(p0))}; + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + const uint32_t c[2] = {c0, c1}; + for (int row = 0; row < 2; ++row) { + d[row] = pair_of((half_t)(acc[row][0] + h2f(c[row])), + (half_t)(acc[row][1] + h2f(c[row] >> 16))); + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/tex/make_ptx.py's debug recipe: with +// D4R_RRSWIN_DEBUG= (resolved from kernels/rr/swin_dec4_debug_stages.py) the +// same splice stores that stage's registers into the plane arena at +46,000,000, +// which the kernel never otherwise writes, and the launch dump then holds the +// translated values for a block/lane. Built with -DD4R_RRSWIN_DEBUG_STAGE= +// (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this body stores the same registers of +// its own phase n in the same order, so the two dumps compare byte for byte. +// +// The block index, the per-block slot and the lane stride all mirror +// make_ptx.py's swin_debug_block() exactly, including its 161-wide grid pitch and +// its skip of everything past the first 64 blocks. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +// The debug payload's byte offset into the plane arena. It must agree with +// D4R_RRSWIN_DEBUG_BASE, which make_ptx reads for the oracle splice. The default +// 46000000 is wrong for dec4: VERIFIED by storing param_0+48's value into a dumped +// argument, the arena is the 65,945,600-byte block at offset 39,567,360, so +// 39,567,360 + 46,000,000 runs 19.6 MB past the end of the block and the payload +// lands in memory no launch dump contains -- which is why every dec4 stage +// comparison first looked like a MATCH while comparing stale buffer content +// (the same window is byte-identical in the reference run, which stores nothing). +// 16 MiB leaves 64*slot bytes of room inside the block (the tail after the arena is +// 26,378,240) and clears arg008's own window at offset 2,282,752. +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 16777216 +#endif + +enum : int +{ + kDebugBase = D4R_RRSWIN_DEBUG_BASE, + kDebugBlocks = 64, + kDebugGridPitch = 161, +}; + +DEVF uint32_t debug_slot(int nregs) +{ + const uint32_t want = (uint32_t)nregs * 128u > 8192u ? (uint32_t)nregs * 128u : 8192u; + uint32_t slot = 1; + while (slot < want) { + slot <<= 1; + } + return slot; +} + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + kDebugGridPitch * __builtin_amdgcn_workgroup_id_y(); + if (block >= (uint32_t)kDebugBlocks) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + const uint32_t slot = debug_slot(n); + uint32_t* dst = (uint32_t*)(arena + (uint64_t)kDebugBase + + ((uint64_t)block * slot) + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// --------------------------------------------------------------------------- +// Phase 1: the patch-expand GEMM, the entry's first 300 mma. +// +// Shape: M = 240 (fifteen 16-row A fragments), N = 800 (a hundred 8-column B +// fragments), K = 160 (five k-steps), and 300 mma rather than the 7500 a dense +// 240x800x160 would need -- so this is a band, not a dense GEMM, and the tool's +// M/N columns are its "distinct fragment" counts rather than a real matrix shape. +// +// The mma order (VERIFIED by walking all 300 statements) is: sixty five-step chains, +// each seeded once and then accumulating through C. Statement i uses +// A fragment 5*(i/100) + (i/2)%5 +// B fragment i % 100 +// C the D pair of statement i-2, or the chain's seed when i%10 is 0 or 1 +// so chain (g, q, p) -- g = 0..2, q = 0..9, p = 0,1 -- runs the statements +// 100g + 10q + p, +2, +4, +6, +8, carries A fragment 5*g + step, and is seeded with +// the seed register at index 10*q + p of the twenty (3227, 3237, 3327, 3337, ...), +// three chains per seed, one per A group. The sixty chains are disjoint: their +// accumulators are %r(1218 + 10*i) with i = 100g + 10q + p + 8, so the chain's own +// statement order is also its accumulator order (g major, then q, then p) -- which is +// the order the oracle's p1 stage lists the sixty pairs in. +// +// The B block is [0, 25600) per slab: `W + z*25600 + 16*laneid + 512*i` for the +// hundred fragments, fifty 512-byte tiles, two fragments per tile. Fragment f lives +// at tile f/2 with `8*(f&1)` selecting which half, so its eight columns are +// n = 8*f .. 8*f+7 phase-relative -- which is exactly waddr()'s phase-relative n. +// +// The lane's two columns of fragment f are 2t and 2t+1, so bv[c][k] is read at +// n = 8*f + 2*t + c. +DEVF void phase1(const uint32_t* as, const uint8_t* w, const uint32_t* seeds, int z, + const uint8_t* prm) +{ + const int t = (int)(lane_id() & 3); + const int base = z * 25600; + uint32_t acc[60][2]; + + for (int chain = 0; chain < 60; ++chain) { + const int g = chain / 20; // the A group: statements 100g..100g+99 + const int sp = chain % 20; // 10*q + p: the seed index and the B fragment base + uint32_t c0 = seeds[sp]; + uint32_t c1 = c0; // PTX: {%r3227, %r3227} -- one u32 in both halves + for (int step = 0; step < 5; ++step) { + const int af = 5 * g + step; + const int bf = sp + 2 * step; + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * bf + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + mma_step(&as[4 * af], bv, c0, c1, acc[chain]); + c0 = acc[chain][0]; + c1 = acc[chain][1]; + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + // the oracle's p1 stage: the sixty chain-final D pairs in mma statement + // order, each as the (row g, row g+8) pair its mma wrote + uint32_t regs[120]; + for (int c = 0; c < 60; ++c) { + regs[2 * c] = acc[c][0]; + regs[2 * c + 1] = acc[c][1]; + } + debug_store(prm, regs, 120); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 2 + { + // the oracle's p1a stage: the fifteen A fragments, four b32 each, in the + // first mma's operand order -- the sixty registers the splice hands over + uint32_t regs[60]; + for (int i = 0; i < 60; ++i) { + regs[i] = as[i]; + } + debug_store(prm, regs, 60); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 3 + { + // the oracle's p1s stage: the twenty bias seeds in chain-root order + uint32_t regs[20]; + for (int i = 0; i < 20; ++i) { + regs[i] = seeds[i]; + } + debug_store(prm, regs, 20); + } +#endif +} + +// --------------------------------------------------------------------------- +// Mirror cut. dec4's first phase reads its A operands from the e4m3 feature buffer +// in the prologue (param+8, a clamped halo gather, file lines 1063-1468), so its +// fifteen 16-row fragments arrive here already in registers: %r2130..%r2213, +// %r3130..%r3213 and %r4130..%r4213, four b32 each in the first mma's operand +// order. Then phase 1's twenty bias seeds, the weight image (arg040) and the +// parameter block; see kernels/rr/swin_dec4_recipe.py for the register lists and +// the file-line evidence behind each. +// +// The four accumulators phase 62 leaves live across the cut (%r34761, %r34762, +// %r34771, %r34772, read back out of `SM` by E62's softmax at line 58152) cross it +// through shared memory, not `call.uni`'s return parameters: ZLUDA lowers those to the +// function's LLVM return type (emit.rs's emit_call makes one value, or a struct for +// several, and distributes them with LLVMBuildExtractValue), so there is no +// .param-space object and no pointer is formed -- the callee reads 0x0 in all four +// slots. `scratch` is the base of `SM` (16384 bytes), whose top 128 bytes no +// ld.shared/st.shared in the entry can reach. +extern "C" __attribute__((device)) void d4r_swin_dec4( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t a24, uint32_t a25, uint32_t a26, uint32_t a27, + uint32_t a28, uint32_t a29, uint32_t a30, uint32_t a31, uint32_t a32, uint32_t a33, uint32_t a34, + uint32_t a35, uint32_t a36, uint32_t a37, uint32_t a38, uint32_t a39, uint32_t a40, uint32_t a41, + uint32_t a42, uint32_t a43, uint32_t a44, uint32_t a45, uint32_t a46, uint32_t a47, uint32_t a48, + uint32_t a49, uint32_t a50, uint32_t a51, uint32_t a52, uint32_t a53, uint32_t a54, uint32_t a55, + uint32_t a56, uint32_t a57, uint32_t a58, uint32_t a59, + uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3, uint32_t b4, uint32_t b5, uint32_t b6, + uint32_t b7, uint32_t b8, uint32_t b9, uint32_t b10, uint32_t b11, uint32_t b12, uint32_t b13, + uint32_t b14, uint32_t b15, uint32_t b16, uint32_t b17, uint32_t b18, uint32_t b19, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[60] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, + a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, + a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, a47, + a48, a49, a50, a51, a52, a53, a54, a55, a56, a57, a58, a59}; + const uint32_t seeds[20] = {b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, + b10, b11, b12, b13, b14, b15, b16, b17, b18, b19}; + // the slab index: %r9 = %tid.z, guarded to 0..3 by the prologue's `setp.gt.u32` + const int z = (int)__builtin_amdgcn_workitem_id_z(); + // Address space 3 (the shared scratch) explicitly: a generic store lowers to flat, + // which faults. The splice reads the same six words back at SM + 15616 + 24*laneid + // (swin_dec4_recipe.py's RET_BASE/RET_STRIDE). + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + + kRetBase / 4 + (uint32_t)lane_id() * (kRetStride / 4); + + // ---- phase 1 ----------------------------------------------------------- + phase1(as1, w, seeds, z, prm); + + // ---- phases 2-62: not implemented yet ---------------------------------- + // The three D pairs the epilogue reads (%r34761/62, %r34771/72, %r34888/89) are + // still placeholders. Fill them with lane-distinct values so the read-back path is + // observable without producing wild magnitudes. Every one of the six must be + // written: a register PTX leaves undefined is poison to ZLUDA's optimizer, and one + // such survivor folds the whole entry to `unreachable` (measured: HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION). + for (int i = 0; i < 6; ++i) { + out[i] = (uint32_t)lane_id() + 32u * (uint32_t)i; + } +} diff --git a/kernels/rr/rrswin_dec4_epilogues.md b/kernels/rr/rrswin_dec4_epilogues.md new file mode 100644 index 0000000..ea29883 --- /dev/null +++ b/kernels/rr/rrswin_dec4_epilogues.md @@ -0,0 +1,673 @@ +# `cuda_dldn_engine_swin_dec4_kernel` — the epilogues of phases 1…62 + +Companion to `kernels/rr/rr_layer_spec.py dec4`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0019-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec4_kernel` (the entry opens at file line 1016, its body +holds statements s1…s24447, and s24447 is the `ret`). + +dec4 is the widest of the eleven Swin layers: its attention/MLP width is 160 where +dec3's is 128, so every count below is *not* interchangeable with dec3's. Where a +region is the same code as dec3's, that is stated and the shared evidence is cited +on dec4's own statements. + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents; **`LNNNNN` is the physical line** of the same instruction, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. (Example anchors: + phase 1's 300 `mma` occupy only L1707–L3799, and s871 = L3807.) +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`; a phase's own weight loads live in the previous + epilogue, and are named in place. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_dec4_kernel_param_0+40]` (s9) then + `cvta.to.global.u64 %rd3, %rd2` (s10). Every `ld.weak.global.ca.v4.u32` reads + `W + 16*laneid + imm`; tables and biases use + `W + ((laneid<<2)&12) + imm` (canonical construction s16157–s16161). +* `S` denotes the plane arena: `ld.param.u64 %rd1050, [%rd1+-32]` (s23917) then + `cvta.to.global.u64 %rd5, %rd1050` (s23918), with `%rd1 = param_0+80` (s4), so + `%rd1-32` is **`param_0+48`**. This is the entry's only read of `param_0+48`. +* `SM` denotes the 16384-byte shared array + `_ZZ33cuda_dldn_engine_swin_dec4_kernel33DldnEngineSwinEncParamsStructBaseE4smem` + (materialised by `mov.u32` at s11611 and others). +* `%r9 = %tid.z` (s19) is the **slab index**, and dec4 **guards it to 0…3**: + `s20 setp.gt.u32 %p3, %r9, 3` / `s21 @%p3 bra $L__BB1_121`. It scales the input + buffer ×25600 (s438), a second input stride ×160 (s543), ×40 (s1052), the shared + tile ×16 (s2301), ×2560 (s11503), ×2048 (`<<11`, s16069), ×512 (`<<9`, s16128) + and the phase-2…11 weight group ×27648 (`%r16781 = %r9*13824` s11607, + `%rd381 = %r16781*2` s11608, consumed at s11645 `add.s64 %rd383, %rd2, %rd381`). +* Register conventions are the settled family ones: `C/D reg0` = (row g, cols + 2t,2t+1), `reg1` = (row g+8, same cols), `g = laneid>>2` (s37/s38), `t = laneid&3`. +* Anything I could not pin down from the PTX is in §6. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `param+0`, extents `(ex, ey)` | `ld.param.v2.u32 {%r1013, %r1014}, [param_0]` | s15 | +| `param+8`, the e4m3 feature buffer | `ld.param.u64 %rd60, [%rd1+-72]` → `cvta.to.global.u64 %rd61, %rd60` | s34–s35 | +| `param+24`, the f16 image buffer (**the skip input**) | `ld.param.u64 %rd253, [%rd1+-56]` → `cvta.to.global.u64 %rd4, %rd253` | s3640–s3641 | +| `param+40`, `W` (weight image) | `ld.param.u64 %rd2, [param_0+40]` → `cvta.to.global.u64 %rd3, %rd2` | s9–s10 | +| `param+48`, `S` (plane arena) | `ld.param.u64 %rd1050, [%rd1+-32]` → `cvta.to.global.u64 %rd5, %rd1050` | s23917–s23918 | +| `param+80`, block origin `(ox, oy)` | `ld.param.v2.u16 {%rs222, %rs223}, [param_0+80]` | s5 | +| `param+88`, low-res feature **texture** | `ld.param.u64 %rd1117, [%rd1129+8]` with `%rd1129 = param_0+80` (s24223) | s24334 | +| `param+96`, **texture** added unconditionally | `ld.param.u64 %rd1119, [%rd1129+16]` | s24410 | +| `param+104`, **texture** added under a NaN guard | `ld.param.u64 %rd1121, [%rd1129+24]` | s24412 | +| `param+112`, output **surface** | `ld.param.u64 %rd1123, [%rd1129+32]` | s24233 | +| `param+136`, `(sx, sy)` pixel→uv scale | `ld.param.v2.f32 {%f1180, %f1181}, [%rd1129+56]` | s24328 | +| `SM` (16384 B) | `mov.u32 %r16783, _ZZ33…E4smem` | s11611 | +| per-lane weight address | `mul.wide.u32 %rd382, %laneid, 16` + `add.s64 %rd384, %rd383, %rd382` | s11644–s11646 | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, W, %rd` | s16157–s16161 | +| block origins | `%r1 = ctaid.x<<3 − ox` (s7), `%r2 = %r1 − 1` (s8), `%r3 = ctaid.y<<3 − oy` (s14), `%r6 = %r3 − 1` (s16) | s7–s16 | +| `%r7 = ex<<3`, `%r8 = ey*%r7` | s17–s18 | s17–s18 | + +The `param+80`-relative form is worth stressing: dec4 keeps `%rd1127` and `%rd1129` +(both `= %rd1128/%rd1130 + 80`, s24198 / s24223) and then reads the decoder +parameters as `[%rd1127-80]` (= `param+0`), `[%rd1129+8]`, `[%rd1129+16]`, +`[%rd1129+24]`, `[%rd1129+32]`, `[%rd1129+56]`. So **`+96` and `+104` are exactly +`%rd1129+16` and `%rd1129+24`** (s24410 / s24412). + +### 1.2 Constants + +| register | first definition | literal | identity | +|---|---|---|---| +| `%f476` | s12177 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | score scale | +| `%fd383` | s12181 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | clamp low | +| `%fd385` | s12186 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | clamp high | +| `%f478` | s12192 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | cubic coefficient | +| `%f480` | s12197 `mov.f32 %f480, 0f3FB00000` | 1.375 | cubic offset | +| `%fd1` | s10075 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | norm epsilon in E1 | +| `%fd386` | s16920 `mov.f64 %fd386, 0d3F20000000000000` | 2⁻¹³ | norm epsilon in E21 | +| `%f1117` | s17741 `mov.f32 %f1117, 0f3ED306EB` | 0.4121621549129486 | activation ramp | +| `%f1118` | s17744 `mov.f32 %f1118, 0f3DA60DD6` | 0.0810810774564743 | activation width | +| `%f1119` | s17747 `mov.f32 %f1119, 0f3F000000` | 0.5 | activation offset | +| `%f1120` | s17750 `mov.f32 %f1120, 0f40000000` | 2.0 | activation clamp | + +`0f3FB8AA3B` (log2e) occurs 9 times in the final epilogue, first at s24246; the +negated form `0fBFB8AA3B` once at s24415; `0f3F800000` (1.0) at s24251's +`add.ftz.f32`. Neither layer ever uses the `.relu` requantiser: the string +`satfinite.relu` does not occur. + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — requantisation. +* `cvt.rn.f16x2.e4m3x2` — the inverse unpack (one e4m3 byte pair → f16x2). + +## 2. Phase table summary + +From `rr_layer_spec.py dec4`: **62 phases, 1606 `mma`, 24447 statements**. + +The tool prints M and N from the number of *distinct* A and B fragments, so the +identity `M/16 * N/8 * K/32 == mma` is the dense-GEMM check: + +* holds for phases 2–12, 14–21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, + 49, 51, 53, 55, 57, 59, 61; +* **fails for 23 phases — 1, 13, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, + 46, 48, 50, 52, 54, 56, 58, 60, 62.** For the even phases 22…60 the tool prints + M=80 N=160 K=160 (`5*20*5 = 500`) against 20 `mma`: those phases are 5-step + cascades, not dense GEMMs (see E22). For **P62** it prints M=80 N=80 K=160 + against 10 `mma`; P62 is a 5-fragment cascade (A = `%r938…%r957`) as §4/E62 + describes. + +Weight-image extent: the largest byte read from `W` is phase 62's second C seed at +`W + ((laneid<<2)&12) + 534800`, i.e. the image is **at least 534804 bytes**. +Phase 1's B block is `[0, 25600)`, phase 1's C seeds are `[102400, 102704]`, the +score bias (phase 12's C) is `[114240, 126028)`, the per-slab copy of the phase-2…11 +weight group starts at `104000 + z*27648`, and phase 62's last weight tile is +`[532224, 534796)`. + +**Phases that read no weight operand at all: 12 and 13.** Phase 12's A and B both +come from e4m3 packs of phase 10's D (E11), and phase 13's B is the `movmatrix` +transpose of registers (E12); see §4/E11, E12. + +## 3. Summary of epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s871–s11653 | 10783 | requantise P1's D, scatter to `SM`, read back, blend `param+24`, inverse-std, requantise, stage for P2 | +| E2–E10 | 7 stmts each | 7 | next-B weight loads only (s11678–s11900) | +| E11 | s11957–s12127 | 171 | score-bias C-seed loads + 80 packs of P10's D → P12 A and B | +| E12 | s12176–s16019 | 3844 | softmax of the 64×96 score block, V-transpose, pack | +| E13 | s16068–s16341 | 274 | stage P·V, P14 A from `SM`, next-B loads, column table + skip → P14 C | +| E14–E20 | 27 stmts each | 27 | P15…P21 A from `SM` + next-B loads (s16362–s16670) | +| E21 | s16691–s17719 | 1029 | RMS norm (², sum, rsqrt, gain) + packs + next B/C | +| E22 | s17740–s18060 | 321 | clamped cubic activation + column-bias add + packs + next B | +| E23 | s18081–s18172 | 92 | 40 packs → P24 A, next-B, next-C bias | +| E24…E60 | 172/92 alternating | | E22/E23 repeated for P24…P60 | +| E61 | s23857–s24154 | 298 | pack → plane-arena scatter (`param+48`) → next B/C | +| E62 | s24165–s24446 | 282 | `SM` stage, softmax over 5 taps, 3×3 texture gather, aux textures, surface write | + +--- + +## 4. The epilogues + +### E1 — s871–s11653: patch expand, image blend, inverse standard deviation + +10783 statements (44 % of the entry), the same pipeline as dec3's E1 with every +count scaled by 160/128 = 1.25. + +Evidence: + +``` +s871 L3807 cvt.rn.satfinite.e4m3x2.f16x2 %rs226, %r1298 +s875 L3818 mov.b32 %r10, {%rs228, %rs229} +s1090 L4268 st.shared.v2.u16 [%r4580], {%rs226, %rs227} +s1117 L4297 st.shared.u32 [%r4593], %r10 +s2295 L5592 bar.sync 0 +s2340 L5647 ld.shared.v2.u16 {%rs346, %rs347}, [%r5246] +s3640 L7252 ld.param.u64 %rd253, [%rd1+-56] +s3794 L7417 ld.global.v2.u16 {%rs426, %rs427}, [%rd255] +s9055 L12990 cvt.rn.f16x2.e4m3x2 %r9582, %rs426 +s9217 L13472 add.f16 … // first of 324 +s10018 L15459 shfl.sync.bfly.b32 %r9963,%r9959,%r10029,%r9966,%r10040 +s10075 L15607 mov.f64 %fd1, 0d3F20000000000000 +s10321 L16341 rsqrt.approx.ftz.f32 fl, fl +s10963 L17382 ld.global.v2.u16 {%rs3159, %rs3160}, [%rd336+103696] +s11503 L18962 mul.lo.s32 %r936, %r9, 2560 +s11521 L18998 st.shared.v4.u32 [%r10307], {%r10311, %r10310, %r10309, %r10308} +s11606 L19151 bar.sync 0 +s11613 L19160 ld.shared.v4.u32 {%r16785, %r16786, %r16787, %r16788}, [%r16784] +s11651 L19201 ld.weak.global.ca.v4.u32 { %r10356,%r10357,%r10358,%r10359},[%rd337] +``` + +| range | stmts | what | operations (count) | +|---|---|---|---| +| s871–s1048 | 178 | requantise **phase 1's D** and pack | 120 `cvt.rn.satfinite.e4m3x2.f16x2`, 58 `mov.b32` → `%r10…%r67` | +| s1049–s1089 | 41 | lane / `%r9` → shared-index setup for the first store | `mov.u32 %r4338, %laneid` (s1049), `mul.wide.u32 %rd204, %r4338, -1431655765` (s1051) | +| s1090–s2295 | 1206 | guarded scatter into `SM`, one basic block per store | **58 `st.shared.u32`** + 2 `st.shared.v2.u16` | +| s2295 | 1 | `bar.sync 0` (L5592) | — | +| s2296–s3639 | 1344 | read back a window from `SM` (5-way switch per load) | **40 `ld.shared.v2.u16`** (s2340…s3639) | +| s3640–s3641 | 2 | **the `param+24` buffer pointer** | `ld.param.u64 %rd253, [%rd1+-56]`, `cvta` | +| s3642–s9054 | 5413 | clamped-coordinate gather from the `param+24` buffer | **40 `ld.global.v2.u16`** (s3794…s9054) | +| s9055–s9214 | 160 | dequantise both sources | 160 `cvt.rn.f16x2.e4m3x2` → `%r9582…%r9741` | +| s9215–s10017 | 803 | blend + reduction tree | 480 `mul.f16`, 324 `add.f16`, 84 `add.f16x2` | +| s10018–s10074 | 57 | cross-lane sums | **8 `shfl.sync.bfly.b32`** (s10018…s10071) | +| s10075–s10076 | 2 | epsilon `2⁻¹³` | `mov.f64 %fd1, 0d3F20000000000000` (s10075) | +| s10077–s10320 | 244 | epsilon add + packing of the sums | 160 `add.f16`, 81 `mov.b32` | +| s10321–s10956 | 636 | inverse standard deviation | **160 `rsqrt.approx.ftz.f32`** (s10321…s10954) | +| s10957–s10982 | 26 | per-column gain read | **20 `ld.global.v2.u16`** at `W + ((laneid<<2)&12) + {103680…103984}` (s10963…s10982) | +| s10983–s11502 | 520 | normalise and combine | 320 `mul.f16`, 160 `mov.b32`, 40 `cvt.rn.satfinite.e4m3x2.f16x2` | +| s11503–s11605 | 103 | requantise and stage for phase 2 | **10 `st.shared.v4.u32`** | +| s11606 | 1 | `bar.sync 0` (L19151) | — | +| s11607–s11642 | 36 | phase 2's A fragments | **30 `ld.shared.v4.u32`** → `%r16785…%r16904` | +| s11643–s11653 | 11 | phase 2's B | 2 `ld.weak.global.ca.v4.u32` at `W + z*27648 + 16*laneid + {104000, 104512}` | + +**The scatter (s1090–s2295).** The 60 stores are guarded (`setp.gt.u32 %p, …, 9` +at s1052 and its siblings) and the index is +`byte = 4 * ( (col & 3) | (40*row + 400*(col>>2)) )` into `SM` +(`shr.u32 %r4584, %r79, 2` / `mul.lo.s32 %r4585, %r4584, 400` / +`mad.lo.s32 %r4586, %r80, 40, %r4585` / `shl.b32 %r4587, %r81, 2` / +`add.s32 %r4588, %r4587, %r4586` / `and.b32 %r4589, %r79, 3` / +`or.b32 %r4590, %r4589, %r4588` — s1107–s1113). So dec4 writes **10-by-10 +sub-blocks of 400 bytes** and 58 distinct `(row, col)` triples, versus dec3's +literal `+{0,1600,…,11200}` plane offsets. As in dec3 the `(row, col)` order is a +permutation of `laneid` derived with the golden-ratio multiplier +(`mul.wide.u32 %rd204, %r4338, -1431655765`, s1051). The store count differs from +dec3's 48 because dec4's phase 1 produces 800 columns instead of 640. + +**The `param+24` gather (s3642–s9054).** `%rd1-56` is `param_0+24` (s4, s3640); +`%rd4 = cvta.to.global.u64(%rd253)` (s3641). Each of the 40 loads computes a +clamped halo index and issues +`mul.wide.u32 %rd254, %r34933, 4` / `add.s64 %rd255, %rd4, %rd254` / +`ld.global.v2.u16 {%rs426, %rs427}, [%rd255]` (s3792–s3794). The gather's +interior index is `clamped_row * %r7 + 8*clamped_col + min(laneid&3, 7)`, i.e. the +same **8-u32-per-image-row f16 buffer** as dec3's (§4/E1 of `rrswin_dec3_epilogues.md`). + +**The inverse-std block.** The residual `add.f16` fold (first at s9217) yields a +value that is squared (`mul.f16`, s9620ff), reduced in-lane, summed with the +two-step butterfly `shfl.sync.bfly` (s10018, s10071), offset by `2⁻¹³` (s10075) and +inverted by 160 `rsqrt.approx.ftz.f32` (s10321…s10954). The gain table is 20 +`ld.global.v2.u16` at `W + ((laneid<<2)&12) + {103680…103984}` (s10963…s10982) — +40 f16 per lane = 160 columns. + +**Staging for phase 2.** `%r936 = %r9*2560` (s11503); the 10 `st.shared.v4.u32` +write at `SM + z*2048 + 16*laneid + {0,512,1024,1536}` (s11521, s11533, s11545, +s11557) and at `+{10240,10752,11264,11776,12288}` in a second group guarded by +`setp.gt.u32 %p626, %r10328, 31` with `%r10328 = %r9<<4` (s11574–s11575), i.e. only +`z ∈ {0,1}`. After `bar.sync` (s11606) the **30 `ld.shared.v4.u32`** at +`SM + 16*laneid + 512*i` (s11613…s11642) become **phase 2's A** +`%r16785…%r16904` (30 A fragments = 6 m-tiles × 5 k-steps), and the 2 +`ld.weak.global.ca.v4.u32` at s11651/s11653 are phase 2's B. + +### E2–E10 — s11678…s11900: next-B weight loads only + +Seven statements each, exactly dec3's E2–E8 shape: 8 B fragments (16 registers) per +phase, read as `W + z*27648 + 16*laneid + base + 512*i`. The bases are +`104000` (P2), `109120` (P3), `105024` (P4), `110144` (P5), `106048` (P6), +`111168` (P7), `107072` (P8), `112192` (P9), `108096` (P10), `113216` (P11) — the +even phases walk `104000, 105024, 106048, 107072, 108096` and the odd phases +`109120, 110144, 111168, 112192, 113216`, i.e. **five k-group pairs** (dec3 had +four), so phases 2–11 together form one **96×64×160** GEMM split into ten +`96×32×32` phases chained through C (verified from the operand sets: P2/P3 use A +fragment set 0, P4/P5 set 1, P6/P7 set 2, P8/P9 set 3, P10/P11 set 4; P2/P3 have +C = the single zero register `%r16707` while P4…P11 take the previous phase's D). + +### E11 — s11957–s12127: score-bias seeds and 80 packs of phase 10's D + +171 statements, 24 weight loads + 80 packs — the dec3 E9 design with the wider N. + +``` +s11961 L21128 ld.weak.global.ca.v4.u32 { … }, [%rd…] // first of 24 +s12008 L21313 cvt.rn.satfinite.e4m3x2.f16x2 … // first of 80 packs +``` + +* **24 loads** at `W + z*27648 + 16*laneid + 114240 + 512*i`, `i = 0…23` + (s11960 `add.s64 %rd357, %rd404, 114240` with `%rd404 = %rd383 + 16*laneid`, + `%rd383 = W + z*27648`; s11961 the first load, s11962 the next at `+114752`) → + **phase 12's C seeds** (96 registers = 24 C pairs). The block is + `[114240, 126028)`. Note this is a different *kind* of C operand from phase 1's: + phase 1 seeds each mma with a single u32 duplicated into both halves + (`{%r…, %r…}`), loaded as **20** `ld.global.u32` at + `[%rd203 + {102400, 102416, …, 102704}]` (s551–s570), whereas phase 12 takes 24 + full 512-byte tiles. +* **80 packs** whose sources are **phase 10's D**, not phase 11's; they split into + phase 12's A fragments (`%r13134…%r13497`, 16 registers) and B fragments + (`%r13388…%r13499`, 24 registers = 12 fragments). Phase 11's own D reaches + E12's `movmatrix` block instead. +* The C-seed layout is the same as dec3's §4/E9: + `byte = base + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1)`, so the tile index runs + over 4 m-tiles and 6 `(n>>1)` groups = 24 tiles = 12288 bytes. + +### E12 — s12176–s16019: softmax of the 64×96 score block, V-transpose, pack + +**Phase 12** = 48 `mma` of 64×96 with C = the 24 bias pairs (E11). The epilogue has +**no memory access at all** (0 `ld.*`, 0 `st.*`) and no `bar.sync`. Its op +histogram is byte-for-byte dec3's E10: 1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 +`cvt.rn.f16.f64`, 192 each of `fma.rn.f16x2` / `cvt.f32.f16` / +`rcp.approx.ftz.f32` / `mul.f16`, 144 packs, 112 `shl.b32`, 104 `add.f16x2`, +96 each of `mul.f16x2` / `max.f16x2` / `min.f16x2` / `neg.f16x2` / `and.b32`, +48 `movmatrix`, 16 `shfl.sync.bfly.b32`, 8 `add.f16`. + +``` +s12177 L21724 mov.f32 %f476, 0f3C8CCB50 +s12178 L21727 cvt.rn.f16.f32 low, %f476 +s12182 L21737 cvt.rn.f16.f64 %rs3280, %fd383 +s14381 L28593 shfl.sync.bfly.b32 %r15668,%r15664,%r15820,%r15671,%r15831 // first of 16 +s14511 L28919 rcp.approx.ftz.f32 fl, fl // first of 192 +s15278 L30164 mul.f16 %rs4074,%rs4075,%rs4076 // first of 192 +s15756 L31218 movmatrix.sync.trans.aligned.m8n8.b16 %r16028, %r12605 // first of 48 +s15804 L31362 cvt.rn.satfinite.e4m3x2.f16x2 %rs4648, %r16036 // first of 144 packs +``` + +Sub-sections (the same partitioning dec3's §4/E10 documents): + +| range | what | +|---|---| +| s12176–s14293 | 96 per-element groups: scale, clamp, cubic, exponent extract (all 96 `max.f16x2` ≤ s14278, `min.f16x2` ≤ s14282, `neg.f16x2` ≤ s14283, `and.b32` ≤ s14293) | +| s14294–s14508 | in-lane partial sums and the butterfly: 104 `add.f16x2` (s14294–s14503), 16 `add.s32` (s14378–s14500), 16 `or.b32` (s14379–s14501), **16 `shfl.sync.bfly.b32`** (s14381–s14502) → 8 row sums, 8 `add.f16` (s14390–s14505) | +| s14509–s15277 | 192 `cvt.f32.f16` (s14509–s15270) → **192 `rcp.approx.ftz.f32`** (s14511–s15272) → 192 `cvt.rn.f16.f32` (…s15274) = 96 reciprocals | +| s15278–s15755 | **192 `mul.f16`** (s15278–s15754) → 96 probabilities | +| s15756–s15803 | 48 `movmatrix` transposing **phase 11's D** | +| s15804–s16019 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs (s15804–s16018) | + +(The boundaries above are the runs between the first/last occurrence of each op, +verified with the lineariser; the exponent region's end is fixed by the last +`and.b32` at s14293 and the sum region's by the first `add.f16x2` at s14294.) + +Per element the exponent is the clamped cubic of dec3's §4/E10: + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +t = f16(m*(-m) + 0.92724609375) +u = f16(m*t + 1.375) +expval = f16 from bits ((bits(u)<<5) & 0x7FE07FE0) +``` + +and **there is no row maximum**: `max.f16x2` (96×) and `min.f16x2` (96×) are the +clamp, and the only warp shuffles are the 16 `shfl.sync.bfly` above. Contrast E62, +which does compute a real row max over 5 taps. + +### E13 — s16068–s16341: stage P·V, seed phase 14 + +274 statements. + +``` +s16068 L32201 bar.sync 0 +s16069 L32202 shl.b32 %r17033, %r9, 11 +s16070 L32203 add.s32 %r17034, %r16783, %r17033 +s16074 L32210 cvt.rn.satfinite.e4m3x2.f16x2 %rs4792, %r16368 // first of 32 packs +s16086 L32237 st.shared.v4.u32 [%r17036], {%r17040, %r17039, %r17038, %r17037} +s16128 L32328 shl.b32 %r34545, %r9, 9 +s16133 L32335 ld.shared.v4.u32 {%r34550, %r34551, %r34552, %r34553}, [%r34549] +s16138 L32343 ld.weak.global.ca.v4.u32 { %r17055,%r17056,%r17057,%r17058},[%rd405] +s16162 L32388 ld.global.v2.u16 {%rs7270, %rs7271}, [%rd889+325200] // first of 20 +s16183 L32410 add.f16 %rs4826,%rs7309,%rs4828 // first of 80 +``` + +* s16068 `bar.sync`; s16069–s16073 build `%r17036 = SM + z*2048 + 16*laneid`; +* 32 `cvt.rn.satfinite.e4m3x2.f16x2` packing phase 13's D and 4 + `st.shared.v4.u32` at `SM + z*2048 + 16*laneid + {0,512,1024,1536}` + (s16086, s16100, s16114, s16127); +* s16128–s16132 `%r34549 = SM + z*512 + 16*laneid`; s16133 + `ld.shared.v4.u32` → **phase 14's A fragment #0** (`%r34550…%r34553`); +* s16137–s16156 **10 weight loads** at `W + 16*laneid + {126528, 127040, 128064, + 128576, 129088, 129600, 130112, 130624, 131136}` → phase 14's B (20 fragments = + 40 registers); +* s16161–s16181 **20 table loads** at `W + ((laneid<<2)&12) + {325184, 325200, … + 325488}` (16-byte stride) → 40 f16 per lane = a per-column table; +* s16182–s16341 **80 `add.f16`** → 40 b32 `%r17104, %r17105, …` = **phase 14's C + seeds**, exactly `table[col] + residual` (s16183 `add.f16 %rs4826,%rs7309,%rs4828` + where the second operand is the E1 residual register). + +So `phase 14: D = A·B + (skip_residual + column_table)`. + +### E14–E20 — s16362–s16670: A from `SM` + next-B, seven times + +27 statements each: one `ld.shared.v4.u32` (one A fragment, `%r34557…%r34560` in +E14, then `%r34563…`, `%r34569…`, `%r34575…`, `%r34581…`, `%r34587…`, `%r34593…`), +10 `ld.weak.global.ca.v4.u32` (the next phase's B, 20 fragments = 40 registers) and +the address arithmetic. Example, E14 (s16362–s16388): `s16365 ld.shared.v4.u32`, +`s16370 ld.weak.global.ca.v4.u32` (first of 10). + +Together with E13 this supplies the A k-fragments of phases 14–21, which are one +GEMM **16×160×256** split across eight `mma` phases chained through C (P15 C = P14's +D, …, P21 C = P20's D). The B blocks are `126528` (P14), `154176` (P15), `181824` +(P16), `209472` (P17), `237120` (P18), `264768` (P19), `292416` (P20), `320064` +(P21). + +### E21 — s16691–s17719: RMS norm before the MLP + +1029 statements, no stores. The dec3 E15 design scaled by 160/128. + +``` +s16691 L34285 shl.b32 %r34597, %r9, 1 +s16693 L34287 mov.b32 {%rs6072, %rs6075}, %r18790 // first of 302 +s16694 L34289 mul.f16 %rs5066,%rs6075,%rs6075 // first of 240 squares +s16895 L34846 shfl.sync.bfly.b32 %r19103,%r19099,%r15820,%r19106,%r15831 // first of 4 +s16920 L34912 mov.f64 %fd386, 0d3F20000000000000 // eps = 2^-13 +s16921 L34914 cvt.rn.f16.f64 %rs5309, %fd386 +s17046 L35286 rsqrt.approx.ftz.f32 fl, fl // first of 80 +s17368 L35807 ld.global.v2.u16 {%rs7310, %rs7311}, [%rd906+325520] // first of 20 gain loads +s17632 L36554 ld.weak.global.ca.v4.u32 { %r19224,%r19225,%r19226,%r19227},[%rd485] // first of 10 next-B +s17656 L36599 ld.global.u32 %r19314, [%rd911+330944] // first of 4 next-C bias words +s17660 L36604 cvt.rn.satfinite.e4m3x2.f16x2 %rs6031, %r33783 // first of 40 packs +``` + +| range | stmts | op | +|---|---|---| +| s16691–s16903 | 213 | lane/origin setup and 160 `mul.f16` squares (the remaining 80 of the 240 are in the normalise) | +| s16853–s17040 | 188 | in-lane/butterfly sums: 42 `add.f16x2` (s16853–s16917), 4 `or.b32` (s16894–s16915), **4 `shfl.sync.bfly.b32`** (s16895–s16916), 82 `add.f16` (s16904–s17040) | +| s16920–s16921 | 2 | eps `2⁻¹³` in `%fd386` (`cvt.rn.f16.f64 %rs5309, %fd386` at s16921) | +| s17044–s17361 | 318 | 80 `cvt.f32.f16` (s17044–s17357) → **80 `rsqrt.approx.ftz.f32`** (s17046–s17359) → 80 `cvt.rn.f16.f32` (s17048–s17361) | +| s17368–s17387 | 20 | gain loads `W + ((laneid<<2)&12) + {325504…325808}` (`+325504` appears last, `+325520` first) | +| s17632–s17659 | 28 | 10 `ld.weak.global.ca.v4.u32` (phase 22's B, `320064 + 512*i`, s17632–s17650) then 4 `ld.global.u32` at `330944/330960/330976/330992` (phase 22's C bias word, s17656–s17659) | +| s17660–s17718 | 59 | 40 packs → phase 22's A | + +**What it computes** — the same expression as dec3's §4/E15: +``` +sumsq[row] = Σ_c x[row,c]² (f16, in-lane tree + 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2⁻¹³))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` +with **no mean subtraction and no `1/N`**, and the gain is a per-column table read +with the `W + ((laneid<<2)&12) + off` pattern. The norm's bias is not added here: +it is phase 22's C seed, loaded at s17656. + +### E22 — s17740–s18060: clamped cubic activation + column bias + +321 statements. + +``` +s17740 L36884 mov.u32 %r19505, %laneid +s17741 L36886 mov.f32 %f1117, 0f3ED306EB +s17744 L36893 mov.f32 %f1118, 0f3DA60DD6 +s17747 L36900 mov.f32 %f1119, 0f3F000000 +s17750 L36907 mov.f32 %f1120, 0f40000000 +s17753 L36915 neg.f16x2 %r19510,%r19509 // first of 8 +s17754 max.f16x2 … // first of 8 +s17755 min.f16x2 … // first of 8 +s17756 abs.f16x2 … // first of 8 +s17757 L36931 mul.f16x2 %r19520,%r19507,%r19518 // first of 24 +s17758 sub.f16x2 … // first of 8 +s17760 add.f16x2 … // first of 8 +s17883 add.s64 … // column-table addressing +s17885 L37377 ld.weak.global.ca.v4.u32 … // first of 10 next-B loads +s17909 L37422 ld.global.v2.u16 {%rs7350, %rs7351}, [%rd916+336144] // first of 20 table loads +s17929 L37469 add.f16 … // first of 80 bias adds +s18049 L37803 cvt.rn.satfinite.e4m3x2.f16x2 %rs6311, %r19648 // first of 8 packs +``` + +Per element, over each of the 8 f16x2 groups of phase 22's D: + +``` +y = clamp(x, -2, +2) // neg/max/min, s17753–s17755 +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // abs/mul/sub/mul/add, s17756–s17760 +out = x * g +``` + +`g` is a **cubic ramp, not a sigmoid**: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`. **Reproduce the formula, not SiLU/GELU.** +The constants `%f1117…%f1120` are defined here and are re-read as +`cvt.rn.f16.f32 low, %f1117…%f1120` by every later activation epilogue. + +Then 20 table loads (s17909 = `+336144`) and 80 `add.f16` (s17929–s18047) write the +table over the activation **inputs**, producing **phase 23's C seeds**; the final 8 +packs (s18049…) build **phase 23's A** (one 4-register fragment); and the 10 +`ld.weak.global.ca.v4.u32` from s17885 are phase 23's B block `[331008, 336128)`. + +### E23 — s18081–s18172: packs, then next B/C + +92 statements: + +``` +s18081 L37971 mov.u32 %r19988, %laneid +s18085 L37979 ld.weak.global.ca.v4.u32 … // first of 10 next-B loads +s18109 L38022 ld.global.u32 %r20079, [%rd921+341568] // first of 4 next-C bias words +s18113 L38027 cvt.rn.satfinite.e4m3x2.f16x2 %rs6319, %r33783 // first of 40 packs +``` + +40 packs (20 b32) → **phase 24's A**; 10 `ld.weak.global.ca.v4.u32` → phase 24's B +`[336448, 341568)`; 4 `ld.global.u32` at `341568/341584/341600/341616` → phase 24's +C bias. + +### E24 … E60 — the repeating MLP stack + +The pattern `(activation, first one with a table add) → (40 packs + next B/C)` +repeats with a period of two phases. Numbering the phases: the **even** phases 22, +24, …, 60 each have a 321/172-statement activation epilogue; the **odd** phases 23, +25, …, 59 each have a 92-statement pack epilogue. Verified op histograms: + +* P22 epi (s17740–s18060, 321): 80 `add.f16`, 76 `mov.b32`, 32 `cvt.rn.f16.f32`, + 24 `mul.f16x2`, 20 `ld.global.v2.u16`, 10 `ld.weak`, 8 each of + `neg/max/min/abs/sub/add.f16x2`, 8 packs. +* P23 epi (s18081–s18172, 92): 40 packs, 20 `mov.b32`, 10 `ld.weak`, 4 `ld.global.u32`. +* P24 epi (s18193–s18364, 172): 172 statements with 8 packs and 10 `ld.weak` and + **no** `ld.global.v2.u16`, i.e. no column table add — the residual is carried by + the C operand that E23 loaded. + +The B blocks advance 4128 bytes per phase: `336448` (P24), `341632` (P25), +`346752` (P26), `351936` (P27), `357056` (P28), … `521920` (P60), `527104` (P61), +`532224` (P62), and each phase's C bias words sit in the 48-byte window 48 bytes +below the next phase's B base (e.g. P24's C at `341568..341616`, loaded at s18109). + +### E61 — s23857–s24154: pack → plane-arena scatter → next B/C + +298 statements. + +``` +s23857 L57579 cvt.rn.satfinite.e4m3x2.f16x2 %rs7231, %r34324 // first of 40 packs +s23917 L57718 ld.param.u64 %rd1050, [%rd1+-32] // S = plane arena (param+48) +s23918 L57719 cvta.to.global.u64 %rd5, %rd1050 +s23920 L57723 shr.u32 %r958, %r34544, 2 // g = laneid>>2 +s23921 L57724 and.b32 %r959, %r34544, 3 // t = laneid&3 +s23924 L57727 add.s32 %r34630, %r937, %r34628 // y = %r937 + (laneid>>5) +s23930 L57733 add.s32 %r34631, %r1, %r34629 // x = %r1 + (g&7) +s23943 L57747 st.global.u32 [%rd1052], %r938 // first of 20 stores +s24139 L57579-… ld.weak.global.ca.v4.u32 // first of 5 next-B loads +s24153 ld.global.u32 … // first of 2 next-C seeds +``` + +* 40 packs → 20 b32 `%r938…%r957`, which are simultaneously **phase 62's A + fragments** — the same 20 registers are scattered to memory and fed to the last + GEMM. +* `S = cvta.to.global.u64(param_0+48)` via `%rd1-32` (s23917–s23918) — the entry's + only read of `param_0+48`. +* **20 `st.global.u32`** (first at s23943 with value `%r938`), each guarded by + `setp.lt.s32 %p, %r34630, 0` / `setp.ge.u32 %p, %r34630, %r1014` / + `setp.gt.u32 %p, %r34544, 63` combined with `or.pred` (s23925–s23929) and the + matching x guards, then a `selp.b32 …, -1, …, %p1` + `setp.lt.s32` + `bra` that + turns a guard failure into "skip the store". +* The index is `idx = (8*ex)*y + 8*x + d` with `%r7 = ex<<3` (s17), + `y = %r937 + (laneid>>5)` where **`%r937 = %r3 + 2*%r9`** (s16691–s16692), and + `x = %r1 + ((laneid>>2)&7)`, `d = t` (or `d = t|4`), exactly dec3's §5 formula. +* after the stores: 5 `ld.weak.global.ca.v4.u32` at + `W + 16*laneid + {532224, 532736, 533248, 533760, 534272}` (s24138–s24147, + `%r34660…%r34679`) = phase 62's B (10 fragments = 20 registers), then 2 + `ld.global.u32` at `W + ((laneid<<2)&12) + {534784, 534800}` (s24153–s24154, + `%r34690`/`%r34700`) = phase 62's C seeds. + +### E62 — s24165–s24446: softmax over five taps, 3×3 texture gather, surface write + +282 statements; the entry's last statement is the `ret`. + +``` +s24165 L58082 bar.sync 0 +s24170 L58089 shl.b32 %r997, %r34888, 4 +s24177 L58096 st.shared.u32 [%r998], %r34761 +s24181 L58101 st.shared.u32 [%r998+16], %r34771 +s24198 L58121 add.s64 %rd1127, %rd1128, 80 +s24209 L58132 add.s32 %r1003, %r1, %r1001 // x +s24210 L58133 add.s32 %r1004, %r3, %r1002 // y +s24215 L58138 ld.param.v2.u32 {%r34806, %r34807}, [%rd1127+-80] // ex, ey +s24223 L58147 add.s64 %rd1129, %rd1130, 80 +s24233 L58157 ld.param.u64 %rd1123, [%rd1129+32] // output surface (param+112) +s24246 L58191 (first of 12 mul.ftz.f32 by 0f3FB8AA3B) +s24247 L58192 ex2.approx.ftz.f32 +s24328 L58360 ld.param.v2.f32 {%f1180, %f1181}, [%rd1129+56] // param+136 scale pair +s24334 L58366 ld.param.u64 %rd1117, [%rd1129+8] // param+88 low-res texture +s24336 L58369 tex.base.2d.v4.f16.f32 {%rs7418,…,}, [%rd1101, {%f1140,%f1141}] +s24410 L58541 ld.param.u64 %rd1119, [%rd1129+16] // param+96 +s24411 L58543 tex.base.2d.v4.f16.s32 {%rs7562,…,}, [%rd1119, {%r1003,%r1004}] +s24412 L58545 ld.param.u64 %rd1121, [%rd1129+24] // param+104 +s24413 L58547 tex.base.2d.v4.f16.s32 {%rs7566,…,}, [%rd1121, {%r1003,%r1004}] +s24445 L58635 sust.b.2d.v4.b16.zero [%rd1123, {%r34877,%r1004}], {%rs7619,%rs7620,%rs7621,%rs7618} +``` + +Op histogram (s24165–s24446): 30 `fma.rn.f16`, 17 `mov.b32`, 16 `add.s32`, +13 `setp.lt.s32`, 12 each of `mul.ftz.f32` / `cvt.rn.f16.f32` / `selp.b32`, +10 each of `cvt.f32.f16` / `ex2.approx.ftz.f32` / `add.ftz.f32`, +9 `tex.base.2d.v4.f16.f32`, 8 `mov.u64`, 6 each of `mov.u32` / `and.b32` / +`shl.b32` / `bra` / `cvt.rn.f32.s32` / `fma.rn.ftz.f32`, 5 `ld.shared.u32`, +5 `sub.f16x2`, 5 `mul.f16x2`, and 1 `sust`. + +| range | stmts | what | +|---|---|---| +| s24165–s24197 | 33 | `bar.sync` (s24165) + stage phase 62's D into `SM` at `(48*y + 6*x)` slots (4 `st.shared.u32`, s24177–s24194) | +| s24198–s24227 | 30 | pointer setup: `%rd1127 = %rd1128 + 80` (s24198), second `bar.sync` (s24199), the integer coordinates `%r1003 = %r1+%r1001` / `%r1004 = %r3+%r1002` (s24209–s24210), `(ex, ey)` read from `%rd1127-80` (s24215), bounds guard (s24216–s24222), `%rd1129 = %rd1130 + 80` (s24223) | +| s24228–s24241 | 14 | surface pointer `param+112` = `[%rd1129+32]` (s24233), **5 `ld.shared.u32`** reading 5 consecutive taps (s24228–s24234), and the row max: 3 `max.f16x2` (s24236–s24238) + 2 `max.f16` (s24240–s24241) | +| s24233 / s24243–s24326 | — | surface pointer `param+112` (s24233); softmax: 5 `sub.f16x2` (s24243–s24295), 12 `mul.ftz.f32` (s24246–), 10 `ex2.approx.ftz.f32` (s24247–), `div.approx.ftz.f32` (s24304, s24418), 5 `mul.f16x2` (s24307–s24311), 3 `cvt.rn.f16.s32` (s24312–s24314), 12 `selp.b32` (s24319–) | +| s24327–s24333 | 7 | clamped coordinates `clamp(p-1, 1, ex-2)` / `clamp(p-1, 1, ey-2)` (6 `cvt.rn.f32.s32` s24327–, 6 `fma.rn.ftz.f32` s24330–, `ld.param.v2.f32` s24328) | +| s24334–s24410 | 77 | 9 `tex.base.2d.v4.f16.f32` (s24336–s24406) at the 3×3 stencil of `param+88`, accumulated with 30 `fma.rn.f16` (s24338–s24427) | +| s24411–s24413 | 3 | 2 `tex.base.2d.v4.f16.s32` at `param+96` (s24410–s24411) and `param+104` (s24412–s24413), both at `{%r1003, %r1004}` | +| s24414–s24444 | 31 | `sigmoid`-like blend (s24418 `div.approx`, s24421 `sub.f16`, 3 `mul.f16` s24422–s24426, 3 `fma.rn.f16`) then the per-channel NaN guard on `param+104`: 3 `set.nan.f16.f16` (s24428–s24438) → `setp.ne.s16` → `@p bra` → 3 `add.f16` (s24431–s24441) | +| s24445 | 1 | `sust.b.2d.v4.b16.zero` surface write | + +**Where the +96/+104 reads go.** `%rd1129+16` = `param+96` (s24410) and +`%rd1129+24` = `param+104` (s24412). Both are `tex.base.2d.v4.f16.s32` reads at the +same integer coordinate `{%r1003, %r1004}` = `(x, y)` (s24209–s24210); +`param+96`'s channels are added unconditionally, while `param+104`'s are added +**per channel only when the channel is not NaN** (`set.nan.f16.f16`). The surface +written is `%rd1123 = param+112` (s24233), and the write lands at +`(%r34877, %r1004)` with `0` in the fourth channel (s24445). + +**What the +24 skip input supplies.** `param_0+24` (reached as `%rd1-56`, s3640) +supplies the f16 image values that E1 adds to the shared-staged features (s9217 +onward) to form the residual. That residual is used in E1's own normalisation +(`mul.f16`) and is added to the per-column table at `W+325184` in E13 +(s16182–s16341) to seed phase 14's C operand. + +## 5. The plane-arena writes (`param_0+48`) + +`S = cvta.to.global.u64(%rd1050)` with `%rd1050 = ld.param.u64 [%rd1+-32]` +(s23917–s23918) is the **only** occurrence of `param_0+48` in the entry. There are +exactly two store groups in the whole entry: + +**(i) E61, 20 × `st.global.u32 [%rd1052 + …], v` — s23943 … s24129.** The first +is `s23943 L57747 st.global.u32 [%rd1052], %r938` and the last is +`s24129 L57971 st.global.u32 [%rd1090], %r957`; the values are `%r938…%r957` in +file order (the same 20 registers that become phase 62's A). Each is guarded as +described in §4/E61: + +``` +idx = (8*ex)*y + 8*x + d, guard y >= 0, y < ey, laneid <= 63, x >= 0, x < ex +y = %r937 + (laneid>>5), %r937 = %r3 + 2*%r9, x = %r1 + ((laneid>>2)&7), +d = t (first of each pair) | d = t|4, with t = laneid&3 +where ex = %r1013, ey = %r1014 (s15), %r1 = block origin x (s7), %r3 = block origin y (s14) +``` + +**(ii) E62, the shared staging** at s24177/s24181/s24190/s24194: `st.shared.u32` +into `SM`, not the arena. + +**What is written:** phase 61's requantised 16×160 output (20 u32 per lane). +**What reads it back:** nothing inside this kernel — `param_0+48` is never the base +of an `ld.*`, and phase 62's A comes from registers (`%r938…%r957`, E61's own +packs). See §6. + +## 6. Uncharacterised + +**U1. The shared-memory layout of E1's first scatter.** dec4 writes with +`byte = 4 * ((col&3) | (40*row + 400*(col>>2)))` (s1107–s1113) into a 16 KB array, +rather than dec3's literal `+{0,1600,…,11200}` plane offsets. I did not reduce the +`(row, col)` permutation of `laneid` (built with `mul.wide.u32 %rd204, %r4338, +-1431655765`, s1051) to a closed form, nor map each plane to a source element of the +800-column phase-1 output. *Missing:* a shared-memory dump or the producer's D +layout. + +**U2. `%r16781 = %r9*13824` (s11607) feeding `%rd381` (s11608).** `%rd381` is used +at s11645 as the slab term `W + z*27648` for phase 2's B. The *derivation* `13824*2` +looks like a per-slab stride expressed for a different tile width, so the constant +13824 is presumably the per-slab output-tile size divided by 2, but nothing in the +PTX states it. *Missing:* the weight-image layout description. + +**U3. The identity of the per-column tables.** `W+325184` (E13), `W+336144` (E22), +`W+103680…103984` (E1's gain), `W+325504…325808` (E21's gain) are all read with the +same `W + ((laneid<<2)&12) + off` pattern. Their *roles* are computable (E13: added +to the skip before phase 14; E22: added after the activation; E1/E21: multiply the +inverse std) but their *names* are not. The same is true of the GEMM biases at +`102400…102704` (P12), `126528`-adjacent words and `534784/534800` (P62). +*Missing:* the weight image's `_prep` permutation or the model's parameter names. + +**U4. The identity of the 12288-byte score bias.** Phase 12 adds a 12288-byte f16 +table (`W + z*27648 + 114240 … 126028`) as its GEMM C operand, laid out as §4/E11 +describes. Whether it is a relative position bias, a learned score bias, or a +per-lane constant cannot be decided from the PTX. + +**U5. The geometry of the banded phases.** Twenty-three phases print an M/N/K that +fails `M/16·N/8·K/32 == mma` (P1, 13, 22–60 even, 62). For the even phases +22…60 I verified the 5-step cascade shape (A = 5 fragments, B = 20 fragments, +`mma = 20 = 5*4` with the C-chain running over the A fragments), and for P62 +likewise (A = 5 fragments, B = 10 fragments, `mma = 10 = 5*2`). For **P1** +(300 mma, 100 B fragments, 250 distinct C/D pairs) and **P13** (48 mma, C set of 65 +registers) I did not reduce the full (M, N, K) reading. The epilogue contracts +above do not depend on resolving this. + +**U6. The logical meaning of E62's blend.** E62 computes a blend of a 3×3 +`tex.base.2d.v4.f16.f32` gather of `param+88` (weighted by a 5-tap softmax) with the +`param+96` texture and, per channel under a NaN guard, the `param+104` texture, then +writes `param+112` at `(8·x, y)`. The PTX gives the arithmetic exactly but not +which model term this is. *Missing:* the high-level source or a reference. + +**U7. The count of distinct input-buffer strides.** dec4's prologue/`E1` use +×25600 (s438), ×160 (s543) and ×40 (s1052) for `%r9` in addition to the shared and +weight strides. I did not determine which of the three addresses the prologue's +gather (`param+8`) versus E1's gather (`param+24`) versus some other buffer. +*Missing:* a mapping from `%r9` to buffer identity. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| patch expand | §4/E1 (s871–s11653) and phase 1 (§2) | +| the norms | E1's rsqrt block (s9215–s10956, eps s10075) and E21 (s16691–s17719, eps s16920) | +| the attention | E11 (score seeds + packs), E12 (softmax + `movmatrix` s15756–s15803 + packs), E13 (P·V staging) | +| the activations | E22, E24, …, E60 — the clamped cubic `x·(0.5 + y·(0.412109375 − 0.0810546875·|y|))`, `y = clamp(x,±2)`; constants s17741–s17750 | +| the per-launch table in the plane arena | §5, s23917/s23943ff (`param_0+48`) | +| every epilogue of every phase | §3 summary table + §4 (E1–E62) | +| texture reads at +96/+104 and where the surface write goes | §4/E62, s24410–s24413 and s24233/s24445 | +| what the skip input at +24 supplies | §1.1 (s3640) and §4/E1, E13 | +| phase table M/N/K arithmetic checked | §2 (23 phases fail; listed) | +| weight-image extent | §2 (≥ 534804 bytes; last read s24153 + 2 words) | +| phases with no weight operand | §2: 12 and 13 | +| uncharacterised | §6 | diff --git a/kernels/rr/rrswin_enc0.hip b/kernels/rr/rrswin_enc0.hip new file mode 100644 index 0000000..4a34e82 --- /dev/null +++ b/kernels/rr/rrswin_enc0.hip @@ -0,0 +1,1691 @@ +// Native replacement for the Ray Reconstruction denoiser's first Swin encoder, +// cuda_dldn_engine_swin_enc0_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: every phase of the kernel is implemented, in the PTX's own order. Each one is +// checked against the debug oracle (see "Ground truth" below) with its own oracle capture, +// and a stage counts as validated only when its whole payload region matches the +// translated kernel byte for byte. Phase 1's GEMM, its relu requantisation +// into phase 2's A operand, phase 2's GEMM, the LayerNorm tree (the sum-of-squares +// butterfly, the rsqrt and the activation gains) and the fused Q/V projection of phases 3 +// and 4; the first attention window in phases 5 to 7 (the 64x96 score with its position +// bias, the softmax and P*V, the output projection with the residual and the per-column +// table); the second window in phases 8 to 12 (two more projections off the same normed +// tile, its own score table at weight bytes 23744, its P*V, and the output projection that +// folds phase 7's accumulators in as its C operand); the MLP in phases 13 to 20 (E12's RMS +// norm, four parallel branches that share its tile and each with the clamped cubic +// activation, their running residual); and the merge in phases 21 and 22 (E20's plane-arena +// scatter and eight-pair lane merge, E21's surface scatter, phase 22's projection). +// +// The epilogue E22 stays NVIDIA's: it lives outside the cut and reads the eighteen values +// this body hands back (the parameter block's first word, %tid.x and phase 22's eight mma +// D pairs). +// +// The whole body costs about 6 ms per launch on an RX 9070 XT (gfx1201) with its results +// kept alive by a debug store; as served, where the optimiser drops them again, it is the +// kernel's dominant cost. +// +// --------------------------------------------------------------------------- +// The kernel is one warp per 8x8 token patch: grid (161, 93, 1), block (32, 1, 1), +// 14973 blocks, parameter block 1032 bytes. The PTX this file replaces is +// kernels/extracted/rr/0013-PREPASS_ENTRYPOINT_NAME.ptx. +// +// kernels/tex/make_ptx.py's recipe (D4R_RRSWIN_CUT=1) keeps NVIDIA's texture +// prologue (lines 1-3963) and surface epilogue (lines 44528-end) and replaces the +// 536 mma of the 22 phases with the call below. Without that variable the recipe +// replaces the whole body instead (a served stub). +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" +#ifdef D4R_RRSWIN_NATIVE_GEMM +#include "rrswin_engine.h" +#endif + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinEnc0Params +{ + uint8_t raw[1032]; +}; +static_assert(sizeof(DldnSwinEnc0Params) == 1032, "parameter block"); + +enum : int +{ + kOutPlane = 8, // plane arena the encoder writes (arg048) + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kSurfaceA = 112, // 1280x736x4 RGBA16F outputs (arg112/arg120) + kSurfaceB = 120, + kSurfaceHalf = 128, // 640x368x4 RGBA16F (arg128) + kSurfaceIn = 304, // 1280x720x4 RGBA16F, read-only (arg304) + kPlaneArg = 48, // plane arena pointer, as make_ptx.py's debug splice reads it +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +#ifdef D4R_RRSWIN_NATIVE_GEMM +// A token tile (512 bytes), two prepared weight tiles (1024 bytes), and their +// f16 result (1024 bytes) fit within the existing 3200-byte shared scratch. +DEVF void gemm_native_unbiased(const uint32_t* as, const uint32_t* bs, + int nmi, uint32_t scratch, lds_u32* out) +{ + lds_u8* const shared = (lds_u8*)(uintptr_t)scratch; + uint8_t* const image = (uint8_t*)shared; + uint8_t* const weights = (uint8_t*)(shared + 512); + __attribute__((address_space(3))) half_t* const result = + (__attribute__((address_space(3))) half_t*)(shared + 1536); + const uint32_t lane = lane_id(); +#pragma unroll + for (int tile = 0; tile < 2; ++tile) +#pragma unroll + for (int word = 0; word < 4; ++word) +#pragma unroll + for (int j = 0; j < 4; ++j) + { + const uint32_t n = 16 * tile + (lane >> 2) + 8 * (word >> 1); + const uint32_t k = 2 * (lane & 3) + (j & 1) + 16 * (j >> 1) + 8 * (word & 1); + weights[16 * (32 * (k >> 4) + n) + (k & 15)] = + (uint8_t)(bs[4 * tile + word] >> (8 * j)); + } + __builtin_amdgcn_wave_barrier(); +#pragma unroll + for (int mi = 0; mi < nmi; ++mi) + { + rrswin::swin_stage_fragment(image, 32, as + 4 * mi, 1); + __builtin_amdgcn_wave_barrier(); +#pragma unroll + for (int mt = 0; mt < 2; ++mt) + { + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)weights, 16 * mt, 32, image, 32, 0); +#pragma unroll + for (int i = 0; i < 8; ++i) + result[32 * (lane & 15) + 16 * mt + i + 8 * (lane >> 4)] = (half_t)c[i]; + } + __builtin_amdgcn_wave_barrier(); +#pragma unroll + for (int rh = 0; rh < 2; ++rh) +#pragma unroll + for (int nt = 0; nt < 4; ++nt) + { + const int at = 32 * ((lane >> 2) + 8 * rh) + 8 * nt + 2 * (lane & 3); + out[8 * mi + 2 * nt + rh] = rrswin::pair_of(result[at], result[at + 1]); + } + __builtin_amdgcn_wave_barrier(); + } +} +#endif + +#ifdef D4R_RRSWIN_PHASE8 +extern "C" __attribute__((device)) void d4r_swin_enc0_p8( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, + uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3, + uint32_t b4, uint32_t b5, uint32_t b6, uint32_t b7, uint32_t scratch) +{ + const uint32_t as[4] = {a0, a1, a2, a3}; + const uint32_t bs[8] = {b0, b1, b2, b3, b4, b5, b6, b7}; + // All WMMA reads finish before the lane-major return overwrites operand + // storage. The result matrix at +1536 remains disjoint from this return. + lds_u32* const out = (lds_u32*)(uintptr_t)(scratch + 32 * lane_id()); + gemm_native_unbiased(as, bs, 1, scratch, out); +} +#endif + +// --------------------------------------------------------------------------- +// The implemented phases, as byte offsets into arg040 (from the PTX's own loads; +// K=32 and N=32, so each reads two 512-byte weight tiles): +// P1 weights 4096, bias seeds handed in as b0..b3 (loaded from +5120..+5184) +// P2 weights 5184, f16 bias at 6208..6272, activation gains at 6272..6336 +// P3 weights 6336, no bias (the fused Q projection) +// P4 weights 7360, no bias (V) + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (VERIFIED on all 1024 (n, k) pairs of a tile; the 64*(n&7) term is what keeps +// columns 16..31 from silently reading as zero.) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +DEVF float bfly1(float v) +{ + return __builtin_bit_cast(float, bfly1_bits(__builtin_bit_cast(uint32_t, v))); +} + +DEVF float bfly2(float v) +{ + return __builtin_bit_cast(float, bfly2_bits(__builtin_bit_cast(uint32_t, v))); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +// add.f16x2 on a packed pair (the PTX's reduction and requantisation steps) +DEVF uint32_t pair_add(uint32_t a, uint32_t b) +{ + return __builtin_bit_cast(uint32_t, __builtin_bit_cast(hv2, a) + __builtin_bit_cast(hv2, b)); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// ZLUDA's relu_keep_nan_halves: a negative (or -0) half becomes +0, NaN is kept. +DEVF uint32_t relu_pair(uint32_t p) +{ + if ((p & 0x8000u) != 0 && (p & 0x7fffu) <= 0x7c00u) { + p &= 0xffff0000u; + } + if ((p & 0x80000000u) != 0 && ((p >> 16) & 0x7fffu) <= 0x7c00u) { + p &= 0x0000ffffu; + } + return p; +} + +// --------------------------------------------------------------------------- +// One GEMM: 96 rows (six m-tiles of 16) x 32 columns, K=32, f16 output. +// +// A lane's A registers hold, for each m-tile and each of its two rows, the eight +// e4m3 values of k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3) and of k + 8; the +// four lanes that differ in t hold the four disjoint eighths of the 32 k's, so two +// butterfly steps broadcast the other three eighths in. The B operand is read from +// the weight image (waddr) for the lane's own two columns of each n-tile. The dot +// product runs in f32 and is rounded to f16 once, which is what the translated mma +// does: e4m3 x e4m3 products are exact and 32 of them sum exactly in f32, so this +// reproduces the translated kernel bit for bit. +// +// Exactly one of the three C operands carries the bias: `wbias` (a byte pointer at the phase's +// bias offset, 16 bytes per n-tile), `seeds` (four already lane-indexed packed pairs, phase 1), +// or `cmat` (32 lane-indexed pairs indexed [4*m-tile + row][n-tile], phase 7, whose seed is +// or `cmat` (32 lane-indexed pairs indexed [4*m-tile + row][n-tile], phases 7 and 12-20, +// whose seed is the residual plus the per-column table and so differs per row). +// d is [m-tile][row half][n-tile], each entry the packed f16 pair for columns 2t, 2t+1; +// `nnt` is the number of n-tiles (four everywhere but phase 22's two). +DEVF void gemm(const uint32_t* as, const uint8_t* w, int base, const uint8_t* wbias, + const uint32_t* seeds, const uint32_t* cmat, int nmi, int t, + uint32_t d[6][2][4], int nnt = 4) +{ + for (int nt = 0; nt < nnt; ++nt) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + for (int mi = 0; mi < nmi; ++mi) { + uint32_t fixed = 0; + if (wbias != nullptr) { + fixed = *(const uint32_t*)(wbias + 16 * nt + 4 * t); + } else if (seeds != nullptr) { + fixed = seeds[nt]; + } + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + uint32_t p[4]; + p[0] = as[4 * mi + 2 * reg + row]; + p[1] = bfly1_bits(p[0]); + p[2] = bfly2_bits(p[0]); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + const uint32_t bias_pair = (cmat != nullptr) ? cmat[(4 * mi + row) * 4 + nt] : fixed; + d[mi][row][nt] = pair_of((half_t)(acc[row][0] + h2f(bias_pair)), + (half_t)(acc[row][1] + h2f(bias_pair >> 16))); + } + } + } +} + +// --------------------------------------------------------------------------- +// Phases 5-7: the window's self-attention and the output projection. Both operands of +// phase 5 come from phase 3's accumulators (rows 0..63 are the queries, rows 0..95 the keys +// -- the 8x8 token patch plus its 32-row halo), so A and B are built exactly the way the +// PTX's 24 packs build them: word 0 of a row packs n-tiles 0 and 2, word 1 packs 1 and 3, +// and the four lanes t=0..3 of a group hold the four disjoint eighths of the 32 k's, which +// the two butterfly steps bring together. Every e4m3 product is exact and a 32-term k +// slice sums exactly in f32, so the dot product is plain f32 accumulation rounded to f16 +// once -- what the translated mma does. + +// the f16 the PTX's literals carry: 0f3C8CCB50, 0dBFE1CC0000000000, 0f3F6D6000, 0f3FB00000 +DEVF half_t hf16(uint16_t bits) +{ + return __builtin_bit_cast(half_t, bits); +} + +DEVF hv2 hv2_of(uint32_t p) +{ + return __builtin_bit_cast(hv2, p); +} + +DEVF uint32_t u32_of(hv2 v) +{ + return __builtin_bit_cast(uint32_t, v); +} + +// ZLUDA's own rcp.approx.ftz.f32 helper: calling it is what makes the reciprocal bit-exact. +extern "C" __attribute__((device)) float __zluda_ptx_impl_rcp_approx_f32(float); + +// the e4m3 code of one f16 (cvt.rn.satfinite.e4m3x2.f16x2 of a pair of equal halves) +DEVF uint32_t q8(half_t v) +{ + return e4m3x2(pair_of(v, v)); +} + +// the f16 at (row, col) of a 96x32 block of packed pairs, col = 8*n-tile + 2t + c +DEVF half_t dcell(const uint32_t d[6][2][4], int row, int col) +{ + const uint32_t p = d[row >> 4][(row >> 3) & 1][col >> 3]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +// the lane's two e4m3-packed words for row r: word 0 packs n-tiles 0 and 2, word 1 tiles 1 and 3 +DEVF void row_words(const uint32_t d[6][2][4], int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// out[i][m]: word i as lane t^m holds it, which is what the mma pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + + +// word i at butterfly index m (0..3), without the dynamic index into the pair +DEVF uint32_t word_at(const uint32_t out[2][4], int i, int m) +{ + return m == 0 ? out[i][0] : (m == 1 ? out[i][1] : (m == 2 ? out[i][2] : out[i][3])); +} + +// the 32-term dot product of two packed operand word pairs, in the mma's own k order +DEVF float dot32(const uint32_t a[2][4], const uint32_t b[2][4]) +{ + float acc = 0.0f; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + acc += e4m3_to_f32((a[i][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((b[i][m] >> (8 * j)) & 0xffu); + } + } + } + return acc; +} + +// E5(a), one element: the scale, the clamp, the two clamped-cubic fma pairs and the trick +// that moves the mantissa into the exponent field ((u << 5) & 0x7FE07FE0 over the pair). +DEVF uint32_t expval_pair(uint32_t score) +{ + hv2 m = hv2_of(score) * __builtin_bit_cast(hv2, pair_of(hf16(0x2466), hf16(0x2466))); + m = __builtin_elementwise_max(m, __builtin_bit_cast(hv2, pair_of(hf16(0xb873), hf16(0xb873)))); + m = __builtin_elementwise_min(m, __builtin_bit_cast(hv2, pair_of(hf16(0x3873), hf16(0x3873)))); + const hv2 t = __builtin_elementwise_fma(m, -m, + __builtin_bit_cast(hv2, pair_of(hf16(0x3b6b), hf16(0x3b6b)))); + const uint32_t u = u32_of(__builtin_elementwise_fma(m, t, + __builtin_bit_cast(hv2, pair_of(hf16(0x3d80), hf16(0x3d80))))); + return (u << 5) & 0x7fe07fe0u; +} + +// E5(a)-(e), one row: the twelve exponent pairs, the in-lane sum tree +// (((e0+e2)+(e4+e6))+(e8+e10)) + (((e1+e3)+(e5+e7))+(e9+e11)), the two butterfly steps that +// finish the row's 96 columns, the two halves' add, the reciprocal and the twelve products. +DEVF void row_probs(const uint32_t d5[4][2][12], int mi, int rh, uint32_t prob[12]) +{ + hv2 ev[6], eo[6]; +#pragma unroll + for (int i = 0; i < 6; ++i) { + ev[i] = hv2_of(expval_pair(d5[mi][rh][2 * i])); + eo[i] = hv2_of(expval_pair(d5[mi][rh][2 * i + 1])); + } + const hv2 even = ((ev[0] + ev[1]) + (ev[2] + ev[3])) + (ev[4] + ev[5]); + const hv2 odd = ((eo[0] + eo[1]) + (eo[2] + eo[3])) + (eo[4] + eo[5]); + hv2 s = even + odd; + s = s + hv2_of(bfly1_bits(u32_of(s))); + s = s + hv2_of(bfly2_bits(u32_of(s))); + const uint32_t p = u32_of(s); + // the PTX broadcasts the f16 sum of the two halves (add.f16) and takes cvt.f32.f16 of it: + // the value, not its bits + const half_t r = (half_t)__zluda_ptx_impl_rcp_approx_f32((float)(half_lo(p) + half_hi(p))); + const uint32_t rcp = pair_of(r, r); +#pragma unroll + for (int i = 0; i < 6; ++i) { + prob[2 * i] = u32_of(ev[i] * hv2_of(rcp)); + prob[2 * i + 1] = u32_of(eo[i] * hv2_of(rcp)); + } +} + +// --------------------------------------------------------------------------- +// The two GEMMs the two attention windows share: the 64x96 score (phases 5 and 10) and +// the softmax plus P·V that follow it (phases 6 and 11). The second window repeats the +// first one's code with another weight base and another source accumulator, so each is +// one function. + +// The score block. A and B are both the one 96x32 accumulator `dq`: the lane's rows +// 16*mi + g + 8*row are the queries (the 8x8 token patch, 64 rows) and its rows +// 16*(nb>>1) + 8*(nb&1) + g the keys (the patch plus a 32-row halo, 96 rows), which is +// how the PTX's 24 packs build the two operands out of the same D. Every lane publishes +// its two key words per n-tile into `slot` (twelve n-tiles x 64 words = 3072 bytes, inside +// the dead input_tensor the cut hands over) and then forms the dots its own D registers +// hold: query row 16*mi + g + 8*row (the A side keeps the lane's own row group g) against +// key rows 16*(nb>>1) + 8*(nb&1) + 2t + c, published by the lanes 4*(2t + c) + 0..3. The +// C operand is the phase's 64x96 f16 position-bias table at `bias` (weight bytes 8384 or +// 23744): 24 tiles of 512 bytes and 16 per lane, the seed of (m-tile, n-tile) in tile +// mi + 4*(nb>>1) at word 2*(nb&1) + row of the lane's eight f16 (VERIFIED against the +// oracle's own C registers, debug stage 11 for phase 5 and 204 for phase 10). +// Every e4m3 product is exact and a 32-term k slice sums exactly in f32, so the dot +// product is plain f32 accumulation rounded to f16 once -- what the translated mma does. +// +// `cap`, when the debug stage asks for the published key words (203) or the C and B +// operand registers (204), receives them in the oracle's order. +DEVF void score_gemm(const uint32_t dq[6][2][4], const uint8_t* w, int bias, int t, int g, + int lane, lds_u32* slot, uint32_t* cap, uint32_t d[4][2][12]) +{ +#pragma unroll + for (int nb = 0; nb < 12; ++nb) { + uint32_t kw[2]; + row_words(dq, 16 * (nb >> 1) + 8 * (nb & 1) + g, kw); + slot[64 * nb + lane] = kw[0]; + slot[64 * nb + 32 + lane] = kw[1]; + } + __builtin_amdgcn_wave_barrier(); +#if D4R_RRSWIN_DEBUG_STAGE == 203 + if (cap != nullptr) { + for (int nb = 0; nb < 12; ++nb) { + cap[2 * nb] = slot[64 * nb + 4 * (2 * t)]; + cap[2 * nb + 1] = slot[64 * nb + 32 + 4 * (2 * t + 1)]; + } + } +#endif +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#if D4R_RRSWIN_DEBUG_STAGE == 204 + if (cap != nullptr) { + // the mma's A fragment: rows g and g+8 of m-tile mi, word 0 (k = 2t + (j&1) + + // 16*((j>>1)&1), i.e. n-tiles 0 and 2) then word 1 (n-tiles 1 and 3) + uint32_t q0[2], q1[2]; + row_words(dq, 16 * mi + g, q0); + row_words(dq, 16 * mi + g + 8, q1); + cap[4 * mi + 0] = q0[0]; + cap[4 * mi + 1] = q1[0]; + cap[4 * mi + 2] = q0[1]; + cap[4 * mi + 3] = q1[1]; + } +#endif + for (int row = 0; row < 2; ++row) { + uint32_t aw[2], a[2][4]; + row_words(dq, 16 * mi + g + 8 * row, aw); + bfly2x4(aw, a); + for (int nb = 0; nb < 12; ++nb) { + float s[2]; + for (int c = 0; c < 2; ++c) { + uint32_t kb[2][4]; +#pragma unroll + for (int i = 0; i < 2; ++i) { + // The mma's eight n-index rows are the key rows + // 16*(nb>>1) + 8*(nb&1) + n, and the lane's two D columns c = 0, 1 + // are n = 2*t + c: each half dots a *different* key row, not the two + // halves of one. Its B words are the four lanes 4*(2*t + c) + (t^m) + // of that row's group (the same butterfly the A side walks, on the + // row group the D column selects). +#pragma unroll + for (int m = 0; m < 4; ++m) { + kb[i][m] = slot[64 * nb + 32 * i + 4 * (2 * t + c) + (t ^ m)]; + } + } + s[c] = dot32(a, kb); + } + const uint32_t b = + *(const uint32_t*)(w + bias + 512 * (mi + 4 * (nb >> 1)) + + 16 * lane + 8 * (nb & 1) + 4 * row); + d[mi][row][nb] = pair_of((half_t)(s[0] + h2f(b)), + (half_t)(s[1] + h2f(b >> 16))); +#if D4R_RRSWIN_DEBUG_STAGE == 204 + if (cap != nullptr) { + // the position bias, the 24 tiles of four words after the A and B + cap[40 + 4 * (mi + 4 * (nb >> 1)) + 2 * (nb & 1) + row] = b; + } +#elif D4R_RRSWIN_DEBUG_STAGE == 211 + if (cap != nullptr) { + cap[4 * (mi + 4 * (nb >> 1)) + 2 * (nb & 1) + row] = b; + } +#endif + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 204 + if (cap != nullptr) { + // the twelve B fragment pairs, as the mma reads them: the lane's two packed words + // of the key row 16*(nb>>1) + 8*(nb&1) + g, which is what it published in `slot` + for (int nb = 0; nb < 12; ++nb) { + cap[16 + 2 * nb] = slot[64 * nb + lane]; + cap[16 + 2 * nb + 1] = slot[64 * nb + 32 + lane]; + } + } +#elif D4R_RRSWIN_DEBUG_STAGE == 211 + if (cap != nullptr) { + for (int nb = 0; nb < 12; ++nb) { + cap[96 + 2 * nb] = slot[64 * nb + lane]; + cap[96 + 2 * nb + 1] = slot[64 * nb + 32 + lane]; + } + } +#endif +} + +// E5 and E10 with the P·V of phases 6 and 11. row_probs() gives the twelve probability +// pairs of one row; k-step ks packs key columns {4ks, 4ks+2} -- the columns of prob[4ks] +// and prob[4ks+2], low half first -- into the fragment's first word and {4ks+1, 4ks+3} +// into its second. The lane's A fragment is its *own* two rows (16*mi + g and +// 16*mi + g + 8), so the D row it accumulates is its own g; what it lacks is V. The key +// rows 32*ks + kk live in the lanes whose g is kk % 8, and every lane needs all 96 of +// them, so V goes through the dead input_tensor as one e4m3 byte per element +// (96 x 32 = 3072 bytes) and each lane then walks the full k range. The P byte for key +// column kk is the one the lane with t = (kk%8)>>1 packs: word (kk>>3)&1, byte +// 2*(kk>>4) + (kk&1) -- the two butterfly steps of bfly2x4 bring the other three eighths +// in. Each k-step rounds to f16 before the next one adds to it, which is why the chain +// has three separate mma. +// +// `cap`, when the debug stage asks for the A fragments (201), receives the twelve packed +// word pairs in the oracle's order. +DEVF void pv_gemm(const uint32_t ds[4][2][12], const uint32_t dv[6][2][4], int t, int g, + lds_u8* vs, uint32_t* cap, uint32_t d[4][2][4]) +{ + __builtin_amdgcn_wave_barrier(); // the score GEMM's reads of `slot` are done +#pragma unroll + for (int mi4 = 0; mi4 < 6; ++mi4) { + for (int rh4 = 0; rh4 < 2; ++rh4) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + for (int c = 0; c < 2; ++c) { + const int r = 16 * mi4 + 8 * rh4 + g; + vs[r * 32 + 8 * nt + 2 * t + c] = + (uint8_t)q8(dcell(dv, r, 8 * nt + 2 * t + c)); + } + } + } + } + __builtin_amdgcn_wave_barrier(); + const lds_u8* const vp = vs; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int rh = 0; rh < 2; ++rh) { + uint32_t prob[12], aw[3][2]; + row_probs(ds, mi, rh, prob); +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + aw[ks][0] = e4m3x2(prob[4 * ks]) | (e4m3x2(prob[4 * ks + 2]) << 16); + aw[ks][1] = e4m3x2(prob[4 * ks + 1]) | (e4m3x2(prob[4 * ks + 3]) << 16); +#if D4R_RRSWIN_DEBUG_STAGE == 201 + if (cap != nullptr) { + cap[4 * (mi * 3 + ks) + rh] = aw[ks][0]; + cap[4 * (mi * 3 + ks) + 2 + rh] = aw[ks][1]; + } +#endif + } +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + half_t prev0 = hf16(0x0000), prev1 = hf16(0x0000); +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + uint32_t a[2][4]; + bfly2x4(aw[ks], a); + float acc0 = 0.0f, acc1 = 0.0f; +#pragma unroll + for (int kk = 0; kk < 32; ++kk) { + const float pv = e4m3_to_f32( + (word_at(a, (kk >> 3) & 1, t ^ ((kk >> 1) & 3)) + >> (8 * (2 * (kk >> 4) + (kk & 1)))) & 0xffu); + const int r = (32 * ks + kk) * 32 + 8 * nt + 2 * t; + acc0 += pv * e4m3_to_f32(vp[r]); + acc1 += pv * e4m3_to_f32(vp[r + 1]); + } + prev0 = (half_t)(acc0 + (float)prev0); + prev1 = (half_t)(acc1 + (float)prev1); + } + d[mi][rh][nt] = pair_of(prev0, prev1); + } + } + } +} + +// --------------------------------------------------------------------------- +// The MLP's epilogues and the two operand helpers every mma in the entry shares. + +// The sum-of-squares tree: the LayerNorm before phases 3 and 4 (PTX stmts 2399-3701) and +// E12's RMS norm before phase 13 (s12288-s13110), which are the same code with another +// gain table. Per row of the lane: the four n-tiles are squared and added as (n0+n2) then +// (n1+n3), both halves in f16; the butterfly finishes the sum over the row's 32 columns +// and the two halves are added with add.f16; +eps, rsqrt.approx.ftz.f32 and back to f16, +// times the activation gain of the column. The row's value times that factor is the A +// operand of the phase (cvt.rn.satfinite.e4m3x2.f16x2, no relu), packed as {n-tile 0, +// n-tile 2} into the k-group 0 register and {n-tile 1, n-tile 3} into k-group 1. There is +// no mean subtraction and no 1/N: the quantity is the raw sum of the 32 squares. +DEVF void norm_as(const uint32_t (*d)[2][4], const uint8_t* w, int gain, half_t eps, + int nmi, uint32_t as[24]) +{ +#pragma unroll + for (int mi = 0; mi < nmi; ++mi) { + for (int row = 0; row < 2; ++row) { + // the row's partial sums, packed for the two columns 2t and 2t+1 + uint32_t x = 0; + for (int c = 0; c < 2; ++c) { + half_t sq[4]; + for (int nt = 0; nt < 4; ++nt) { + const half_t v = + c == 0 ? half_lo(d[mi][row][nt]) : half_hi(d[mi][row][nt]); + sq[nt] = v * v; + } + const half_t s = (sq[0] + sq[2]) + (sq[1] + sq[3]); + x |= (uint32_t)__builtin_bit_cast(uint16_t, s) << (16 * c); + } + // the PTX's two shfl.sync.bfly steps over the four lanes that hold + // this row's 32 columns + x = pair_add(x, bfly1_bits(x)); + x = pair_add(x, bfly2_bits(x)); + const half_t sum = (half_t)(half_lo(x) + half_hi(x)); + const half_t r = (half_t)__builtin_amdgcn_rsqf((float)(sum + eps)); + const uint32_t* dr = d[mi][row]; + uint32_t p0 = 0; + uint32_t p1 = 0; + for (int nt = 0; nt < 4; ++nt) { + uint32_t prod = 0; + for (int c = 0; c < 2; ++c) { + const half_t g = __builtin_bit_cast(half_t, + *(const uint16_t*)(w + gain + 16 * nt + 4 * (lane_id() & 3) + 2 * c)); + const half_t v = (c == 0 ? half_lo(dr[nt]) : half_hi(dr[nt])) * (r * g); + prod |= (uint32_t)__builtin_bit_cast(uint16_t, v) << (16 * c); + } + const uint32_t code = e4m3x2(prod); + (nt & 1 ? p1 : p0) |= code << 16 * (nt >> 1); + } + as[4 * mi + row] = p0; + as[4 * mi + 2 + row] = p1; + } + } +} + +// E13/E15/E17/E19, one packed pair: the clamped cubic activation, in f16 throughout. The +// PTX's own sequence (s13997.. / s33795..) is +// y = max(x, -2); y = min(y, +2); a = abs(y) +// g = mid - slope * a; g = y * g; g = 0.5 + g; out = x * g +// so the *signed* clamped y is the multiplier and only the inner `slope * a` term takes the +// absolute value; using |y| throughout would make every negative input's gain 0.5 + |y|(...) +// instead of 0.5 - |y|(...) and shift all four branches' activations. +DEVF uint32_t act_pair(uint32_t x) +{ + const hv2 two = hv2_of(pair_of(hf16(0x4000), hf16(0x4000))); + const hv2 slope = hv2_of(pair_of(hf16(0x2d30), hf16(0x2d30))); + const hv2 mid = hv2_of(pair_of(hf16(0x3698), hf16(0x3698))); + const hv2 half0 = hv2_of(pair_of(hf16(0x3800), hf16(0x3800))); + hv2 y = __builtin_elementwise_max(hv2_of(x), -two); + y = __builtin_elementwise_min(y, two); + const hv2 a = __builtin_elementwise_max(y, -y); // abs.f16x2 + const hv2 g = half0 + y * (mid - slope * a); + return u32_of(hv2_of(x) * g); +} + +// E13/E15/E17/E19's pack: the activation of `d` requantised into the next phase's A operand. +// The A operand is four m-tiles of four registers: register 4*mi+row holds n-tiles 0 and 2, +// register 4*mi+2+row holds n-tiles 1 and 3, each as one e4m3x2 of the pair the mma reads. +DEVF void act_pack(const uint32_t d[4][2][4], uint32_t as[16]) +{ + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + const uint32_t a0 = e4m3x2(act_pair(d[mi][row][0])); + const uint32_t a1 = e4m3x2(act_pair(d[mi][row][1])); + const uint32_t a2 = e4m3x2(act_pair(d[mi][row][2])); + const uint32_t a3 = e4m3x2(act_pair(d[mi][row][3])); + as[4 * mi + row] = a0 | (a2 << 16); + as[4 * mi + 2 + row] = a1 | (a3 << 16); + } + } +} + +// The next phase's C seeds: the block's residual plus the per-column table at `tab` +// (eight f16 per lane, the lane's 8 columns of all four n-tiles), added in f16. +// Phase 14's residual is *phase 12's* accumulators -- the MLP adds its input block back, so +// the running residual enters phase 14, not phase 13's own first GEMM (VERIFIED against the +// oracle's own C registers, debug stage p14o: 1024/1024 over four blocks). +DEVF void tab_seed(const uint32_t d[4][2][4], const uint8_t* tab, int lane, uint32_t c[64]) +{ + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + for (int nt = 0; nt < 4; ++nt) { + const uint32_t r = d[mi][row][nt]; + const uint32_t tb = *(const uint32_t*)(tab + 16 * nt + ((lane << 2) & 12)); + c[(4 * mi + row) * 4 + nt] = pair_of( + (half_t)(half_lo(tb) + half_lo(r)), + (half_t)(half_hi(tb) + half_hi(r))); + } + } + } +} + +// The four B fragment pairs of a phase (a weight-image B), as the mma reads them: the +// lane's own two words of tile nt>>1 at byte offset 8*(nt&1), which is its column +// 8*nt + g (VERIFIED against the oracle's own B registers, debug stage p8o). +DEVF void bpair_regs(const uint8_t* w, int base, int lane, uint32_t regs[8]) +{ + for (int nt = 0; nt < 4; ++nt) { + const uint8_t* const p = w + base + 512 * (nt >> 1) + 16 * lane + 8 * (nt & 1); + regs[2 * nt] = *(const uint32_t*)p; + regs[2 * nt + 1] = *(const uint32_t*)(p + 4); + } +} + +// The four bias words of a phase, one per n-tile: the f16 pair of the lane's columns 2t +// and 2t+1, each replicated over the 16 rows of its tile and used by all four m-tiles. +DEVF void wbias_regs(const uint8_t* w, int base, int lane, uint32_t regs[4]) +{ + for (int nt = 0; nt < 4; ++nt) { + regs[nt] = *(const uint32_t*)(w + base + 16 * nt + ((lane << 2) & 12)); + } +} + +// A phase's C seeds in the oracle's register order: the mma run visits (m-tile, n-tile) +// with n-tile fastest, and each of its C pairs is the (row g, row g+8) pair. +DEVF void cseed_regs(const uint32_t c[64], uint32_t regs[32]) +{ + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + for (int row = 0; row < 2; ++row) { + regs[2 * (4 * mi + nt) + row] = c[(4 * mi + row) * 4 + nt]; + } + } + } +} + +// An accumulator block as a C operand: the mma's C pair for m-tile mi and n-tile nt is +// d[mi][row][nt] (VERIFIED for phase 12 against the oracle's own C registers, stage p12o). +DEVF void cres_regs(const uint32_t d[4][2][4], uint32_t c[64]) +{ + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + for (int row = 0; row < 2; ++row) { + c[(4 * mi + row) * 4 + nt] = d[mi][row][nt]; + } + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/tex/make_ptx.py's debug recipe: +// with D4R_RRSWIN_DEBUG=p1 (p2, p3, p4, or a) the same splice stores that stage's +// registers into the plane arena at +46,000,000, which the kernel never otherwise +// writes, and the launch dump then holds the translated values for a block/lane. +// Built with -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, +// D4R_TEX_CFLAGS), this body stores the same registers of its own phase n in the +// same order, so the two dumps compare byte for byte. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 161u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot, make_ptx.py's swin_debug_slot: 32 lanes x n x 4 bytes, at least 8192, + // rounded up to a power of two (the oracle's splice forms block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + 46000000ull + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// stage registers in the oracle's order: 24 mma, m-tile major, n-tile minor, each +// as the (row g, row g+8) pair the mma writes. +DEVF void stage_regs(const uint32_t d[6][2][4], uint32_t regs[48]) +{ + int i = 0; + for (int mi = 0; mi < 6; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// the same for the sixteen-mma phases: m-tile major, n-tile minor, the (row g, row g+8) +// pair each mma writes. +DEVF void stage_regs4(const uint32_t d[4][2][4], uint32_t regs[32]) +{ + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// The merge: E20's arena scatter and its eight shfl pairs, then phases 21 and 22. + +// two u16 into one b32 (the PTX's mov.b32 of two cvt results) +DEVF uint32_t pair16(uint16_t a, uint16_t b) +{ + return (uint32_t)a | ((uint32_t)b << 16); +} + +// E20(b): the sixteen guarded stores of phase 20's requantised output into the plane +// arena. The index is a word index, idx = 8*ex*y + 8*x + d, where (ex, ey) are the +// extents of the parameter block's first word pair, x0 = 8*ctaid.x - param[80] and +// y0 = 8*(ctaid.y + tid.y) - param[82] are the block origins (the PTX's s6 and s16), and +// the lane's cell is x = x0 + (g & 7) with g = laneid>>2 and t = laneid&3: the eight +// stores of one half walk the eight rows y0 + ((g + 8*j)>>3) = y0 + j and the two words +// d = t and t|4 of them. A store whose y or x falls outside the arena is skipped (the +// PTX turns its index into -1 and branches). +DEVF void arena_scatter(const uint8_t* prm, const uint32_t r[16], int lane) +{ + const uint32_t ex = *(const uint32_t*)prm; + const uint32_t ey = *(const uint32_t*)(prm + 4); + const int x0 = 8 * (int)__builtin_amdgcn_workgroup_id_x() + - (int)*(const uint16_t*)(prm + 80); + const int y0 = 8 * (int)(__builtin_amdgcn_workgroup_id_y() + + __builtin_amdgcn_workitem_id_y()) + - (int)*(const uint16_t*)(prm + 82); + uint8_t* const s = (uint8_t*)(uintptr_t)*(const uint64_t*)(prm + kPlaneArg); + const int x = x0 + ((lane >> 2) & 7); + const int t = lane & 3; + if ((unsigned)x >= ex) { + return; + } + const int stride = 8 * (int)ex; + for (int j = 0; j < 8; ++j) { + const int y = y0 + (((lane >> 2) + 8 * j) >> 3); + if ((unsigned)y >= ey) { + continue; + } + const int idx = stride * y + 8 * x; + *(uint32_t*)(s + 4 * (uint32_t)(idx + t)) = r[2 * j]; + *(uint32_t*)(s + 4 * (uint32_t)(idx + (t | 4))) = r[2 * j + 1]; + } +} + +// E20(c): the eight shfl pairs, all with delta 4, that re-pair the eight lanes of every +// group of eight. For a source pair (lo, hi) the lane keeps its own `lo` and its +// partner's `hi` when it is in the lower group of four (laneid & 4 == 0) and the other way +// round when it is in the upper one, so each destination ends up holding both members: +// d1 = (lane & 4) == 0 ? lo[lane] : hi[lane - 4] +// d2 = (lane & 4) == 0 ? lo[lane + 4] : hi[lane] +// The eight pairs are (%r262,%r266) (%r264,%r268) (%r263,%r267) (%r265,%r269) +// (%r270,%r274) (%r272,%r276) (%r271,%r275) (%r273,%r277) and their sixteen results are +// phase 21's four A fragments: %r17490..%r17493, %r17510..%r17513, %r17530..%r17533 and +// %r17550..%r17553, in that order. +// The partner values go through the shared scratch (sixteen words per lane, 512 of the +// 3200 bytes the cut hands over and dead by now) rather than through two more warp +// shuffles: the exchange is the same read of the same lane's value at the same point. +DEVF void merge_frag(const uint32_t r[16], uint32_t scratch, int lane, uint32_t a[16]) +{ + const int lo[8] = {0, 2, 1, 3, 8, 10, 9, 11}; + const int hi[8] = {4, 6, 5, 7, 12, 14, 13, 15}; + // where each pair's first and second result land, as indices into a[] + const int d1[8] = {0, 8, 2, 10, 1, 9, 3, 11}; + const int d2[8] = {4, 12, 6, 14, 5, 13, 7, 15}; + lds_u32* const s = (lds_u32*)(uintptr_t)scratch; +#pragma unroll + for (int i = 0; i < 16; ++i) { + s[16 * lane + i] = r[i]; + } + __builtin_amdgcn_wave_barrier(); + const int partner = lane ^ 4; + const bool up = (lane & 4) != 0; +#pragma unroll + for (int i = 0; i < 8; ++i) { + a[d1[i]] = up ? s[16 * partner + hi[i]] : r[lo[i]]; + a[d2[i]] = up ? s[16 * lane + hi[i]] : s[16 * partner + lo[i]]; + } +} + +// Phase 21: 16 rows x 64 columns contracting over K = 128 in four 32-wide steps. All 32 +// mma read the same four A fragments (one per k-step, the merged `a`), eight n-tiles' B +// fragment pairs from the weight image at 45696, and eight C words at 53888 (one per +// n-tile, replicated over the tile's 16 rows). The A operand's row is the lane's own g +// and its column index 2*(lane & 3), so the four eighths of every k slice come from the +// four lanes of the row group and the two butterfly steps bring them in; the B operand's +// column index is the lane's own g, so the output column 2t + c is the B column of the +// lanes whose g is 2t + c -- which the weight image already holds, and each k-step rounds +// to f16 before the next one adds to it. +DEVF void band21(const uint32_t a[16], const uint8_t* w, const uint8_t* cbias, int lane, + uint32_t d[8][2]) +{ + const int t = lane & 3; +#pragma unroll + for (int nt = 0; nt < 8; ++nt) { + half_t prev[2][2] = {{hf16(0x0000), hf16(0x0000)}, {hf16(0x0000), hf16(0x0000)}}; + const uint32_t cb = *(const uint32_t*)(cbias + 16 * nt + ((lane << 2) & 12)); +#pragma unroll + for (int ks = 0; ks < 4; ++ks) { + // the lane's own A fragment of this k-step, as the four lanes of its row group + // hold it: register o is row o&1, k slice o>>1 + uint32_t ar[2][2][4]; // [row][k slice][lane t^m] +#pragma unroll + for (int slice = 0; slice < 2; ++slice) { + for (int row = 0; row < 2; ++row) { + const uint32_t v = a[4 * ks + 2 * slice + row]; + ar[row][slice][0] = v; + ar[row][slice][1] = bfly1_bits(v); + ar[row][slice][2] = bfly2_bits(v); + ar[row][slice][3] = bfly1_bits(ar[row][slice][2]); + } + } +#pragma unroll + for (int c = 0; c < 2; ++c) { + // the B fragment pairs of the four lanes whose g is the D column 2t + c + const int gp = 2 * t + c; + uint32_t br[2][4]; // [k slice][lane m] +#pragma unroll + for (int m = 0; m < 4; ++m) { + const uint8_t* const p = w + 45696 + 512 * (ks + 4 * (nt >> 1)) + + 16 * (4 * gp + m) + 8 * (nt & 1); + br[0][m] = *(const uint32_t*)p; + br[1][m] = *(const uint32_t*)(p + 4); + } +#pragma unroll + for (int row = 0; row < 2; ++row) { + float s2 = 0.0f; +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int slice = 0; slice < 2; ++slice) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + s2 += e4m3_to_f32((ar[row][slice][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((br[slice][m] >> (8 * j)) & 0xffu); + } + } + } + prev[row][c] = (half_t)(s2 + (ks == 0 ? h2f(cb) : 0.0f) + + (float)prev[row][c]); + } + } + } + d[nt][0] = pair_of(prev[0][0], prev[0][1]); + d[nt][1] = pair_of(prev[1][0], prev[1][1]); + } +} + +// E21: phase 21's requantisation and its eight guarded stores into the buffer the +// parameter block holds at +56 -- not the plane arena. The extents come from the first +// word pair halved, the origin from %r1 and %r6 halved, and the two index bases are +// base1 = 8*(ex>>1)*y1 + 8*x1 with y1 = (%r6>>1) + ((g&1)<<1), +// x1 = (%r1>>1) + ((laneid>>3) & 3) +// base2 = 8*(ex>>1)*y2 + 8*x2 with y2 = y1 + 1, x2 = (%r1>>1) + ((g>>1) & 3) +// (the laneid>>5 term of y1 and the tile-bit test of the guard are both zero for a +// 32-lane block), each store landing at base + t or base + (t|4) words, the last four +// of them one row-stride further on. The sixteen payloads are phase 21's D registers in +// mma order, one e4m3x2 each: the first and the last two travel as v2.u16 and the middle +// twelve as six u32. +DEVF void surface_scatter21(const uint8_t* prm, const uint32_t d[8][2], int lane) +{ + const int r1 = 8 * (int)__builtin_amdgcn_workgroup_id_x() + - (int)*(const uint16_t*)(prm + 80); + const int r6 = 8 * (int)(__builtin_amdgcn_workgroup_id_y() + + __builtin_amdgcn_workitem_id_y()) + - (int)*(const uint16_t*)(prm + 82); + const int ex = (int)(*(const uint32_t*)prm >> 1); + const int ey = (int)(*(const uint32_t*)(prm + 4) >> 1); + const int g = lane >> 2; + const int t = lane & 3; + const int sx = 8 * ex; + const int y1 = (r6 >> 1) + ((g & 1) << 1); + const int y2 = y1 + 1; + const int x1 = (r1 >> 1) + ((lane >> 3) & 3); + const int x2 = (r1 >> 1) + ((g >> 1) & 3); + uint8_t* const dst = (uint8_t*)(uintptr_t)*(const uint64_t*)(prm + 56); + uint16_t q[16]; +#pragma unroll + for (int nt = 0; nt < 8; ++nt) { + for (int row = 0; row < 2; ++row) { + q[2 * nt + row] = (uint16_t)e4m3x2(d[nt][row]); + } + } + const int b1 = sx * y1 + 8 * x1; + const int b2 = sx * y2 + 8 * x2; + const int st = sx * ey; + const bool ok1 = (unsigned)y1 < (unsigned)ey && (unsigned)x1 < (unsigned)ex; + const bool ok2 = (unsigned)y2 < (unsigned)ey && (unsigned)x2 < (unsigned)ex; + if (ok1) { + *(uint32_t*)(dst + 4 * (uint32_t)(b1 + t)) = pair16(q[0], q[1]); + *(uint32_t*)(dst + 4 * (uint32_t)(b1 + (t | 4))) = pair16(q[2], q[3]); + } + if (ok2) { + *(uint32_t*)(dst + 4 * (uint32_t)(b2 + t)) = pair16(q[4], q[5]); + *(uint32_t*)(dst + 4 * (uint32_t)(b2 + (t | 4))) = pair16(q[6], q[7]); + } + if (ok1) { + *(uint32_t*)(dst + 4 * (uint32_t)(b1 + st + t)) = pair16(q[8], q[9]); + *(uint32_t*)(dst + 4 * (uint32_t)(b1 + st + (t | 4))) = pair16(q[10], q[11]); + } + if (ok2) { + *(uint32_t*)(dst + 4 * (uint32_t)(b2 + st + t)) = pair16(q[12], q[13]); + *(uint32_t*)(dst + 4 * (uint32_t)(b2 + st + (t | 4))) = pair16(q[14], q[15]); + } +} + + +// --------------------------------------------------------------------------- +// Mirror cut. The six 16-row fragments of the staged block input arrive in this +// order (the first mma's operand order, .f16.e4m3 fragments of 4 b32 each): +// f0 %r120 %r136 %r128 %r144 f3 %r216 %r232 %r224 %r240 +// f1 %r152 %r168 %r160 %r176 f4 %r246 %r257 %r253 %r1042 +// f2 %r184 %r200 %r192 %r208 f5 %r1079 %r1080 %r1081 %r1082 +// then phase 1's four bias C seeds (%r1086 %r1096 %r1106 %r1116, read from +// +5120/+5136/+5152/+5168), the weight image and the parameter block. +// +// The eighteen accumulators phase 22's epilogue reads cross the cut through shared memory, not +// `call.uni`'s return parameters: ZLUDA lowers those to the function's LLVM return type (emit.rs's +// emit_call makes one value, or an get_or_create_struct_type struct for several, and distributes +// them with LLVMBuildExtractValue), so there is no .param-space object and no pointer is formed -- +// the callee reads 0x0 in all eighteen slots, and an 18 x i32 C++ struct return is an sret pointer, +// a different LLVM signature that will not link. `scratch` is the base of the entry's `input_tensor` +// (.shared 3200 bytes, dead after the cut), 72 bytes apart per lane. +extern "C" __attribute__((device)) void d4r_swin_enc0( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[24] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23}; + const uint32_t seeds[4] = {b0, b1, b2, b3}; + // The epilogue's eighteen registers: %r17597, %r18203 (%tid.x) and phase 22's eight mma D pairs. + // Address space 3 (the shared scratch) explicitly: a generic store lowers to flat, which faults. + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + 18 * (uint32_t)lane_id(); + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + const int g = (int)(lane_id() >> 2); // ... and of its sixteen rows + const uint32_t lane = lane_id(); + const half_t eps = (half_t)0.0009765625f; // the tree's sum-of-squares epsilon + + // ---- phase 1 ----------------------------------------------------------- + uint32_t d1[6][2][4]; // [m-tile][row half][n-tile]: f16 pair + gemm(as1, w, 4096, nullptr, seeds, nullptr, 6, t, d1); +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + uint32_t regs[48]; + stage_regs(d1, regs); + debug_store(prm, regs, 48); + } +#endif + + // ---- phase 2, on phase 1's relu requantisation -------------------------- + // cvt.rn.satfinite.relu.e4m3x2.f16x2, packed by the epilogue as {n-tile 0, + // n-tile 2} into the k-group 0 register and {n-tile 1, n-tile 3} into k-group 1. + uint32_t as2[24]; + for (int mi = 0; mi < 6; ++mi) { + for (int row = 0; row < 2; ++row) { + const uint32_t* d = d1[mi][row]; + const uint32_t c0 = e4m3x2(relu_pair(d[0])) | (e4m3x2(relu_pair(d[2])) << 16); + const uint32_t c1 = e4m3x2(relu_pair(d[1])) | (e4m3x2(relu_pair(d[3])) << 16); + as2[4 * mi + row] = c0; + as2[4 * mi + 2 + row] = c1; + } + } + uint32_t d2[6][2][4]; + gemm(as2, w, 5184, w + 6208, nullptr, nullptr, 6, t, d2); +#if D4R_RRSWIN_DEBUG_STAGE == 2 + { + uint32_t regs[48]; + stage_regs(d2, regs); + debug_store(prm, regs, 48); + } +#endif + + // ---- the LayerNorm tree (PTX stmts 2399-3701) -------------------------- + // Per row: the four n-tiles are squared and added as (n0+n2) then (n1+n3), + // both halves in f16; the butterfly finishes the sum over the row's 32 + // columns and the two halves are added with add.f16; +2^-13, then + // rsqrt.approx.ftz.f32 and back to f16, times the activation gain of the + // column. The row's value times that factor is the A operand of phases 3 and + // 4 (cvt.rn.satfinite.e4m3x2.f16x2, no relu). + uint32_t as3[24]; + norm_as(d2, w, 6272, eps, 6, as3); + + // ---- phases 3 and 4, the fused Q/V projection, on that A operand ------- + uint32_t d3[6][2][4]; + uint32_t d4[6][2][4]; + gemm(as3, w, 6336, nullptr, nullptr, nullptr, 6, t, d3); + gemm(as3, w, 7360, nullptr, nullptr, nullptr, 6, t, d4); +#if D4R_RRSWIN_DEBUG_STAGE == 3 + { + uint32_t regs[48]; + stage_regs(d3, regs); + debug_store(prm, regs, 48); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 4 + { + uint32_t regs[48]; + stage_regs(d4, regs); + debug_store(prm, regs, 48); + } +#endif + + // ---- phases 5 to 7: the first window -------------------------------------- + // score_gemm() and pv_gemm() are the two GEMMs both windows run; see their comments + // for the fragment bookkeeping. The first window scores phase 3's accumulator against + // itself (A and B are both D3 -- the PTX's 24 B fragments are %r2932+10*tt, m-tile + // tt>>1, row half tt&1, VERIFIED against the oracle's own B registers) with the bias + // at weight byte 8384, and takes its V from phase 4's accumulator. +#if D4R_RRSWIN_DEBUG_STAGE == 201 || D4R_RRSWIN_DEBUG_STAGE == 203 \ + || D4R_RRSWIN_DEBUG_STAGE == 204 || D4R_RRSWIN_DEBUG_STAGE == 211 + uint32_t cap[136]; + uint32_t* const cp = cap; +#else + uint32_t* const cp = nullptr; +#endif + lds_u32* const slot = (lds_u32*)(uintptr_t)scratch; // twelve n-tiles x 64 words + uint32_t d5[4][2][12]; // [m-tile][row half][n-tile]: f16 pair + score_gemm(d3, w, 8384, t, g, (int)lane, slot, cp, d5); +#if D4R_RRSWIN_DEBUG_STAGE == 5 + { + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nb = 0; nb < 12; ++nb) { + regs[i++] = d5[mi][0][nb]; + regs[i++] = d5[mi][1][nb]; + } + } + debug_store(prm, regs, 96); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 203 + debug_store(prm, cp, 24); +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 204 + debug_store(prm, cp, 136); +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 211 + debug_store(prm, cp, 120); +#endif + + uint32_t d6[4][2][4]; + pv_gemm(d5, d4, t, g, (lds_u8*)(uintptr_t)scratch, cp, d6); +#if D4R_RRSWIN_DEBUG_STAGE == 6 + { + uint32_t regs[32]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d6[mi][0][nt]; + regs[i++] = d6[mi][1][nt]; + } + } + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 201 + debug_store(prm, cp, 48); +#endif + + // ---- E6 and phase 7, the first window's output projection ---------------- + // A is phase 6's D packed as before; C is phase 2's D plus the per-column table at + // weight bytes 37056..37120 (four words of eight f16, indexed by the 64-byte record + // each group of four lanes shares), taken from the d2 m-tile and n-tile the register + // order names: the mma's C pair for (m-tile mi, n-tile nt) is d2[mi][row][nt] -- the + // identity: phase 7's first four m-tiles are phase 2's rows 0..63 (VERIFIED, stage e6). + // Its output is also phase 12's C operand, so it has to exist before the second window. + uint32_t as7[16]; + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + as7[4 * mi + row] = e4m3x2(d6[mi][row][0]) | (e4m3x2(d6[mi][row][2]) << 16); + as7[4 * mi + 2 + row] = e4m3x2(d6[mi][row][1]) | (e4m3x2(d6[mi][row][3]) << 16); + } + } + uint32_t c7[64]; // [(4*m-tile + row)][n-tile] + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + const uint32_t tab = *(const uint32_t*)(w + 37056 + 16 * nt + ((lane << 2) & 12)); + for (int row = 0; row < 2; ++row) { + const uint32_t r = d2[mi][row][nt]; + c7[(4 * mi + row) * 4 + nt] = pair_of( + (half_t)(half_lo(tab) + half_lo(r)), (half_t)(half_hi(tab) + half_hi(r))); + } + } + } + uint32_t d7[4][2][4]; + gemm(as7, w, 20672, nullptr, nullptr, c7, 4, t, d7); +#if D4R_RRSWIN_DEBUG_STAGE == 202 + { + uint32_t regs[48]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int o = 0; o < 4; ++o) { + regs[i++] = as7[4 * mi + o]; + } + } + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = c7[(4 * mi + 0) * 4 + nt]; + regs[i++] = c7[(4 * mi + 1) * 4 + nt]; + } + } + debug_store(prm, regs, 48); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 7 + { + uint32_t regs[32]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d7[mi][0][nt]; + regs[i++] = d7[mi][1][nt]; + } + } + debug_store(prm, regs, 32); + } +#endif + + // ---- phases 8 and 9: the second window's two projections ----------------- + // The same LayerNorm tile as the A operand of phases 3 and 4 (all four mma read the + // registers %r6784+40*mi -- VERIFIED against the oracle's own A fragment registers, + // debug stage p8o) and no bias: the second window scores D8 against itself and takes + // its V from D9. E7 and E8 between them only load the two weight tiles this reads. + uint32_t d8[6][2][4]; + uint32_t d9[6][2][4]; + gemm(as3, w, 21696, nullptr, nullptr, nullptr, 6, t, d8); + gemm(as3, w, 22720, nullptr, nullptr, nullptr, 6, t, d9); +#if D4R_RRSWIN_DEBUG_STAGE == 8 + { + uint32_t regs[48]; + stage_regs(d8, regs); + debug_store(prm, regs, 48); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 9 + { + uint32_t regs[48]; + stage_regs(d9, regs); + debug_store(prm, regs, 48); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 108 + { + // phase 8's mma operands: the six A fragments (the LayerNorm tile) and the four + // B fragment pairs, which are the lane's own two words of tile nt>>1 at byte + // offset 8*(nt&1) -- its column 8*nt + g + uint32_t regs[32]; + for (int o = 0; o < 24; ++o) { + regs[o] = as3[o]; + } + for (int nt = 0; nt < 4; ++nt) { + const uint8_t* const p = w + 21696 + 512 * (nt >> 1) + 16 * lane + 8 * (nt & 1); + regs[24 + 2 * nt] = *(const uint32_t*)p; + regs[24 + 2 * nt + 1] = *(const uint32_t*)(p + 4); + } + debug_store(prm, regs, 32); + } +#endif + + // ---- phases 10 and 11, and E10: the second window's score and P·V -------- + // Identical to phases 5 and 6 with phase 8's accumulator in place of phase 3's and the + // bias at weight bytes 23744..35532 (the second 12288-byte table, same layout). + uint32_t d10[4][2][12]; + score_gemm(d8, w, 23744, t, g, (int)lane, slot, cp, d10); +#if D4R_RRSWIN_DEBUG_STAGE == 10 + { + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nb = 0; nb < 12; ++nb) { + regs[i++] = d10[mi][0][nb]; + regs[i++] = d10[mi][1][nb]; + } + } + debug_store(prm, regs, 96); + } +#endif + uint32_t d11[4][2][4]; + pv_gemm(d10, d9, t, g, (lds_u8*)(uintptr_t)scratch, cp, d11); +#if D4R_RRSWIN_DEBUG_STAGE == 11 + { + uint32_t regs[32]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d11[mi][0][nt]; + regs[i++] = d11[mi][1][nt]; + } + } + debug_store(prm, regs, 32); + } +#endif + + // ---- E11 and phase 12: the second window's output projection -------------- + // Unlike E6 there is no table: phase 11's output is requantised only, because the + // residual of the first window is phase 12's C operand (the mma's C pair for m-tile + // mi and n-tile nt is phase 7's D register pair %r6334+10*(4*mi+nt) -- VERIFIED + // against the oracle's own C registers, debug stage p12o). + uint32_t as12[16]; + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + as12[4 * mi + row] = e4m3x2(d11[mi][row][0]) | (e4m3x2(d11[mi][row][2]) << 16); + as12[4 * mi + 2 + row] = e4m3x2(d11[mi][row][1]) | (e4m3x2(d11[mi][row][3]) << 16); + } + } + uint32_t c12[64]; // [(4*m-tile + row)][n-tile]: phase 7's accumulators + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + for (int row = 0; row < 2; ++row) { + c12[(4 * mi + row) * 4 + nt] = d7[mi][row][nt]; + } + } + } + uint32_t d12[4][2][4]; + gemm(as12, w, 36032, nullptr, nullptr, c12, 4, t, d12); +#if D4R_RRSWIN_DEBUG_STAGE == 12 + { + uint32_t regs[32]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d12[mi][0][nt]; + regs[i++] = d12[mi][1][nt]; + } + } + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 112 + { + // phase 12's mma operands: the four A fragments, the four B fragment pairs and + // the 32 C seeds in the oracle's (m-tile, n-tile) pair order + uint32_t regs[56]; + for (int o = 0; o < 16; ++o) { + regs[o] = as12[o]; + } + bpair_regs(w, 36032, (int)lane, regs + 16); + cseed_regs(c12, regs + 24); + debug_store(prm, regs, 56); + } +#endif + + // ---- E12 and phases 13 to 20: the MLP ------------------------------------ + // E12's RMS norm is the same sum-of-squares tree as the LayerNorm above, on phase 12's + // accumulators and with the gain at weight bytes 37120..37184; its epsilon is E12's own + // add (%fd770 = 2^-13) and there is no mean subtraction and no 1/N. Its output is the + // shared A operand of the four branches: phases 13, 15, 17 and 19 all read the same + // sixteen registers (%r15389..%r15420, re-packed by E14, E16 and E18). + uint32_t asN[16]; + norm_as(d12, w, 37120, (half_t)0.0001220703125f, 4, asN); + + // ---- phase 13 and E13, the first branch ----------------------------------- + // A = the normed tile, B = the weights at 37184, C = the bias at 38208 (one word per + // n-tile, replicated over the 16 rows of its tile). E13 activates the result and adds + // the per-column table at 39296 to the activation's *input*, which is phase 14's C. + uint32_t d13[4][2][4]; + gemm(asN, w, 37184, w + 38208, nullptr, nullptr, 4, t, d13); +#if D4R_RRSWIN_DEBUG_STAGE == 13 + { + uint32_t regs[32]; + stage_regs4(d13, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 113 + { + uint32_t regs[28]; + for (int o = 0; o < 16; ++o) { + regs[o] = asN[o]; + } + bpair_regs(w, 37184, (int)lane, regs + 16); + wbias_regs(w, 38208, (int)lane, regs + 24); + debug_store(prm, regs, 28); + } +#endif + uint32_t as14[16]; + act_pack(d13, as14); + uint32_t c14[64]; + tab_seed(d12, w + 39296, (int)lane, c14); + uint32_t d14[4][2][4]; + gemm(as14, w, 38272, nullptr, nullptr, c14, 4, t, d14); +#if D4R_RRSWIN_DEBUG_STAGE == 14 + { + uint32_t regs[32]; + stage_regs4(d14, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 114 + { + uint32_t regs[56]; + for (int o = 0; o < 16; ++o) { + regs[o] = as14[o]; + } + bpair_regs(w, 38272, (int)lane, regs + 16); + cseed_regs(c14, regs + 24); + debug_store(prm, regs, 56); + } +#endif + + // ---- phases 15 and 16, the second branch --------------------------------- + // The same pair with the weights at 39360 and 40448 and the bias at 40384: no table + // add, and phase 16's C is branch one's accumulators. + uint32_t d15[4][2][4]; + gemm(asN, w, 39360, w + 40384, nullptr, nullptr, 4, t, d15); +#if D4R_RRSWIN_DEBUG_STAGE == 15 + { + uint32_t regs[32]; + stage_regs4(d15, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 115 + { + uint32_t regs[28]; + for (int o = 0; o < 16; ++o) { + regs[o] = asN[o]; + } + bpair_regs(w, 39360, (int)lane, regs + 16); + wbias_regs(w, 40384, (int)lane, regs + 24); + debug_store(prm, regs, 28); + } +#endif + uint32_t as16[16]; + act_pack(d15, as16); + uint32_t c16[64]; + cres_regs(d14, c16); + uint32_t d16[4][2][4]; + gemm(as16, w, 40448, nullptr, nullptr, c16, 4, t, d16); +#if D4R_RRSWIN_DEBUG_STAGE == 16 + { + uint32_t regs[32]; + stage_regs4(d16, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 116 + { + uint32_t regs[56]; + for (int o = 0; o < 16; ++o) { + regs[o] = as16[o]; + } + bpair_regs(w, 40448, (int)lane, regs + 16); + cseed_regs(c16, regs + 24); + debug_store(prm, regs, 56); + } +#endif + + // ---- phases 17 and 18, the third branch ---------------------------------- + uint32_t d17[4][2][4]; + gemm(asN, w, 41472, w + 42496, nullptr, nullptr, 4, t, d17); +#if D4R_RRSWIN_DEBUG_STAGE == 17 + { + uint32_t regs[32]; + stage_regs4(d17, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 117 + { + uint32_t regs[28]; + for (int o = 0; o < 16; ++o) { + regs[o] = asN[o]; + } + bpair_regs(w, 41472, (int)lane, regs + 16); + wbias_regs(w, 42496, (int)lane, regs + 24); + debug_store(prm, regs, 28); + } +#endif + uint32_t as18[16]; + act_pack(d17, as18); + uint32_t c18[64]; + cres_regs(d16, c18); + uint32_t d18[4][2][4]; + gemm(as18, w, 42560, nullptr, nullptr, c18, 4, t, d18); +#if D4R_RRSWIN_DEBUG_STAGE == 18 + { + uint32_t regs[32]; + stage_regs4(d18, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 118 + { + uint32_t regs[56]; + for (int o = 0; o < 16; ++o) { + regs[o] = as18[o]; + } + bpair_regs(w, 42560, (int)lane, regs + 16); + cseed_regs(c18, regs + 24); + debug_store(prm, regs, 56); + } +#endif + + // ---- phases 19 and 20, the fourth branch --------------------------------- + uint32_t d19[4][2][4]; + gemm(asN, w, 43584, w + 44608, nullptr, nullptr, 4, t, d19); +#if D4R_RRSWIN_DEBUG_STAGE == 19 + { + uint32_t regs[32]; + stage_regs4(d19, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 119 + { + uint32_t regs[28]; + for (int o = 0; o < 16; ++o) { + regs[o] = asN[o]; + } + bpair_regs(w, 43584, (int)lane, regs + 16); + wbias_regs(w, 44608, (int)lane, regs + 24); + debug_store(prm, regs, 28); + } +#endif + uint32_t as20[16]; + act_pack(d19, as20); + uint32_t c20[64]; + cres_regs(d18, c20); + uint32_t d20[4][2][4]; + gemm(as20, w, 44672, nullptr, nullptr, c20, 4, t, d20); + + // ---- E20 and phases 21 and 22: the merge --------------------------------- + // E20 requantises phase 20 into sixteen packed words (r20, the four A fragments of + // phase 22), scatters them into the plane arena, and merges the lanes of each group of + // eight back into phase 21's four A fragments. + uint32_t r20[16]; + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + const uint32_t a0 = e4m3x2(d20[mi][row][0]) | (e4m3x2(d20[mi][row][2]) << 16); + const uint32_t a1 = e4m3x2(d20[mi][row][1]) | (e4m3x2(d20[mi][row][3]) << 16); + r20[4 * mi + row] = a0; + r20[4 * mi + 2 + row] = a1; + } + } + arena_scatter(prm, r20, (int)lane); + uint32_t m21[16]; + merge_frag(r20, scratch, (int)lane, m21); + uint32_t d21[8][2]; + band21(m21, w, w + 53888, (int)lane, d21); + + // ---- E21 and phase 22 --------------------------------------------------- + // E21 requantises phase 21 and scatters it into the buffer at parameter block +56; + // phase 22 takes the sixteen words E20 packed as its A operand (four m-tiles, K=32) + // with the weights at 54016 and the two bias words at 54528. + surface_scatter21(prm, d21, (int)lane); + uint32_t d22[4][2][4]; + gemm(r20, w, 54016, w + 54528, nullptr, nullptr, 4, t, d22, 2); +#if D4R_RRSWIN_DEBUG_STAGE == 20 + { + uint32_t regs[32]; + stage_regs4(d20, regs); + debug_store(prm, regs, 32); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 21 + { + uint32_t regs[16]; + for (int nt = 0; nt < 8; ++nt) { + regs[2 * nt] = d21[nt][0]; + regs[2 * nt + 1] = d21[nt][1]; + } + debug_store(prm, regs, 16); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 22 + { + uint32_t regs[16]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 2; ++nt) { + regs[i++] = d22[mi][0][nt]; + regs[i++] = d22[mi][1][nt]; + } + } + debug_store(prm, regs, 16); + } +#endif + + // ---- handing the accumulators back ------------------------------------ + // %r17597 is param_0[0] (ld.param.v2.u32 at line 44316) and %r18203 is %tid.x + // (line 44456); both sit inside the cut, so the epilogue cannot recompute them. + // The other sixteen are phase 22's eight mma D pairs in mma order. + out[0] = *(const uint32_t*)prm; + out[1] = (uint32_t)__builtin_amdgcn_workitem_id_x(); + int i = 2; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 2; ++nt) { + out[i++] = d22[mi][0][nt]; + out[i++] = d22[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// Weight image layout of the 22 phases (byte ranges of arg040, from the PTX's own +// ld.weak.global loads; 512 bytes per B-fragment pair, K=32, N=32): +// P1 [4096,5120) bias 5120..5184 P12 [36032,37056) +// P2 [5184,6208) bias 6208..6272 P13 [37184,38208) bias 38208..38272 +// P3 [6336,7360) P14 [38272,39296) +// P4 [7360,8384) P15 [39360,40384) bias 40384..40448 +// P5 bias [8384,20672) (64x96 f16) P16 [40448,41472) +// P6 none (P V, B from mma output) P17 [41472,42496) bias 42496..42560 +// P7 [20672,21696) P18 [42560,43584) +// P8 [21696,22720) P19 [43584,44608) bias 44608..44672 +// P9 [22720,23744) P20 [44672,45696) +// P10 bias [23744,36032) (64x96 f16) P21 [45696,53888) bias 53888..54016 +// P11 none (P V) P22 [54016,54544) bias 54528..54560 +// +// Fragment maps (g = lane>>2, t = lane&3). The corrected full-lane phase-8 +// model matches all 3072 f16 outputs of captured block 0. The checked native +// pilot matches 196608 f16 outputs over 64 captured blocks. Its former +// mismatch came from invalid accumulator bounds and device/host block strides, +// not from the fragment map. The software fallback's different fragment +// convention is not the active gfx12 FP8 WMMA reference. +// The hardware order of an m16n8k32 .e4m3 fragment pair is *not* the order the +// PTX ISA figures suggest. NVIDIA's own epilogue (stmts 2256-2327) settles it: it +// builds phase 2's A operand as +// %r1207 = {cvt(%r877), cvt(%r897)} +// where %r877/%r897 are the D halves of mma rows 2231/2233, i.e. (row g, n-tile 0, +// cols 2t, 2t+1) and (row g, n-tile 2, cols 2t, 2t+1). So with the four bytes of +// an A register in memory order: +// A reg 0 -> row g, k = 2t + (j&1) + 16*((j>>1)&1) +// A reg 1 -> row g+8, same k +// A reg 2 -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// A reg 3 -> row g+8, same k +// and the B half that must pair with it (a0/a1 with b0, a2/a3 with b1) is +// B byte j (j<4) -> n = 16*tt + 8*(b>>3) + g, k = 2t + (j&1) + 16*((j>>1)&1) +// B byte j (j>=4) -> n = 16*tt + 8*(b>>3) + g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// with b the byte index within the lane's 16 and tt the 512-byte tile. Inverted, +// that is waddr() above. C/D: +// C/D reg 0 -> row g, cols t*2, t*2+1 +// C/D reg 1 -> row g+8, cols t*2, t*2+1 +// +// A plain f32 dot product over K plus C, rounded to f16 once, reproduces the +// translated kernel's phase-1 output exactly (96x32 elements, 4 blocks x 32 lanes, +// 0 mismatches out of 12288), so the phases need no operand-layout gymnastics and +// no WMMA intrinsics: every GEMM here is exact in f32 before the f16 rounding. +// The textbook order (reg 0 = row g, k = 4t..4t+3) also reproduces phase 1, but +// only because it is a self-consistent relabeling of k on *both* sides; it cannot +// be used for A operands that an epilogue produced, which arrive in the hardware +// order above. diff --git a/kernels/rr/rrswin_enc0_epilogues.md b/kernels/rr/rrswin_enc0_epilogues.md new file mode 100644 index 0000000..d3e54ff --- /dev/null +++ b/kernels/rr/rrswin_enc0_epilogues.md @@ -0,0 +1,1199 @@ +# `cuda_dldn_engine_swin_enc0_kernel` — the epilogues of phases 5…22 + +Companion to `kernels/rr/rr_layer_spec.py enc0`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0013-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc0_kernel`. + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. The phase table (`rr_layer_spec.py enc0`) gives the + ranges; this file names what each one *computes*. +* `W` denotes the prepared weight image: `ld.param.u64 %rd367, + [cuda_dldn_engine_swin_enc0_kernel_param_0+40]` (s2221) and + `cvta.to.global.u64 %rd2, %rd1` (s12, `%rd1` = the same `+40` load at s11). + Every `ld.weak.global.ca.v4.u32` in an epilogue reads `W + 16*laneid + imm`. + `S` denotes the plane arena: `ld.param.u64 %rd276, [%rd368+48]` (s16052). +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, + `g = laneid>>2`, `t = laneid&3`. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, 54560 bytes) | `ld.param.u64 %rd367, [param_0+40]` / `cvta.to.global.u64 %rd2, %rd1` | s2221 / s11 | +| `S` (plane arena) | `ld.param.u64 %rd276, [%rd368+48]` then `cvta.to.global.u64 %rd37, %rd276` | s16052–s16053 | +| `%rd368` | `mov.b64 %rd368, cuda_dldn_engine_swin_enc0_kernel_param_0` | s2220 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r364, %r365}, [param_0+0]` | s13 | +| `%r1`, `%r6` (block origins) | `sub.s32 %r1, %r359, %r360` and `sub.s32 %r6, %r367, %r366` | s6, s16 | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, W, %rd` | every load block | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd2, %rd` = `W + ((laneid*4) & 12)` | s7881–s7885 and copies | + +The last line matters: the four `ld.global.v2.u16` / `ld.global.u32` loads in an +epilogue read `W + ((laneid<<2)&12) + off`, i.e. **the same 64-byte record is +read by the four lanes with equal `laneid&3`, and the four loads pick four +16-byte words inside it.** So those tables are indexed by column, not by row. + +### 1.2 Constants that survive between epilogues + +| register | first definition | f32/f64 literal | value used (after the `cvt`) | +|---|---|---|---| +| `%f2085` | s3984 `mov.f32 %f2085, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 | +| `%fd767` | s3988 `mov.f64 %fd767, 0dBFE1CC0000000000` | −0.55615234375 | f16 `0xB873` = −0.55615234375 | +| `%fd769` | s3993 `mov.f64 %fd769, 0d3FE1CC0000000000` | +0.55615234375 | f16 `0x3873` = +0.55615234375 | +| `%f2087` | s3999 `mov.f32 %f2087, 0f3F6D6000` | 0.92724609375 | f16 `0x3B6B` = 0.92724609375 | +| `%f2089` | s4004 `mov.f32 %f2089, 0f3FB00000` | 1.375 | f16 `0x3D80` = 1.375 | +| `%fd770` | s2802 `mov.f64 %fd770, 0d3F20000000000000` | 2⁻¹³ | f16 `0x0800` = 0.0001220703125 | +| `%f2598` | s13192 `mov.f32 %f2598, 0f3ED306EB` | 0.4121621549129486 | f16 `0x3698` = 0.412109375 | +| `%f2599` | s13195 `mov.f32 %f2599, 0f3DA60DD6` | 0.0810810774564743 | f16 `0x2D30` = 0.0810546875 | +| `%f2600` | s13198 `mov.f32 %f2600, 0f3F000000` | 0.5 | f16 `0x3800` = 0.5 | +| `%f2601` | s13201 `mov.f32 %f2601, 0f40000000` | 2.0 | f16 `0x4000` = 2.0 | + +Also live across the region (defined in the prologue, read by every warp +reduction): `%r11301` = `mov.u32 %r11301, 1` (s2286), `%r11310` = +`mov.u32 %r11310, 2` (s2225), `%r11312` = `mov.u32 %r11312, -1` (s2621) — +the three operands of every `shfl.sync.bfly.b32`. + +`%f2598…%f2601` are defined **inside phase 13's epilogue** and reused by the +epilogues of phases 15, 17 and 19 (e.g. s14001 and s14693 read them). + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (round each step through f16). + +## 2. Summary + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E5 | s3983–s7825 | 3843 | softmax of the 64×96 score block, V-transpose, pack | +| E6 | s7874–s8033 | 160 | residual + per-column table add, pack, next B | +| E7 | s8050–s8056 | 7 | next-B weight loads | +| E8 | s8081–s8087 | 7 | next-B weight loads | +| E9 | s8112–s8282 | 171 | score-bias C-seed loads, pack | +| E10 | s8331–s12168 | 3838 | softmax (2nd window, same code as E5) | +| E11 | s12217–s12271 | 55 | next-B weight loads, pack | +| E12 | s12288–s13174 | 887 | RMS norm (², sum, rsqrt, gain) + packs + next C | +| E13 | s13191–s13899 | 709 | clamped cubic activation + column bias + pack | +| E14 | s13916–s13979 | 64 | next B/C loads, pack | +| E15 | s13996–s14595 | 600 | clamped cubic activation + pack | +| E16 | s14612–s14675 | 64 | next B/C loads, pack | +| E17 | s14692–s15291 | 600 | clamped cubic activation + pack | +| E18 | s15308–s15371 | 64 | next B/C loads, pack | +| E19 | s15388–s15987 | 600 | clamped cubic activation + pack | +| E20 | s16004–s16417 | 414 | pack → plane-arena scatter → 8-lane merge → next B/C | +| E21 | s16450–s16606 | 157 | pack → surface scatter → `%tid.x` → next B/C | +| E22 | s16615–s17222 | 608 | cross-lane row max, softmax, shared-patch gather, store | + +--- + +## 3. The epilogues + +### E5 — s3983–s7825: softmax of the 64×96 score block + +**Phase 5** = 48 `mma` (s3935–s3982), D registers `%r2566…%r3037` (96 +f16x2 = 64 rows × 96 columns held 8 rows × 8 cols per lane). The epilogue has +**no memory access at all** (0 `ld.*`, 0 `st.*`); it also reads phase 4's D +(`%r2149…%r2380`, 48 registers) and writes 77 registers that survive: +the 5 constants of §1.2, phase 6's 12 A fragments (`%r5884 %r5885 %r5886 %r5887`, +`%r5904…`, `… %r6284…%r6287`) and its 12 B fragments +(`%r6178 %r6179 %r6188 %r6189 … %r6288 %r6289`). + +Sub-sections: + +| range | stmts | what | +|---|---|---| +| s3983–s6100 | 2118 | 96 per-element groups: scale, clamp, cubic, exponent extract | +| s6101–s6180 | 80 | partial row-sum trees (in-lane) | +| s6181–s6312 | 132 | 16 `shfl.sync.bfly` → 8 row sums | +| s6313–s7081 | 769 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s7082–s7561 | 480 | 192 `mul.f16` → 96 probabilities | +| s7562–s7609 | 48 | `movmatrix` transpose of phase 4's D | +| s7610–s7825 | 216 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs | + +#### (a) per-element exponent, s3983–s6100 (96 groups of 22 statements) + +Evidence: + +``` +s3984 L8744: mov.f32 %f2085, 0f3C8CCB50 +s3987 L8752: mul.f16x2 %r3048,%r2566,%r3047 +s3992 L8766: max.f16x2 %r3051,%r3048,%r3053 +s3997 L8780: min.f16x2 %r3054,%r3051,%r3056 +s4003 L8798: fma.rn.f16x2 %r3059,%r3054,%r3057,%r3062 +s4008 L8812: fma.rn.f16x2 %r3063,%r3054,%r3059,%r3066 +s4009 L8815: shl.b32 %r16813, %r3063, 5 +s4010 L8816: and.b32 %r4968, %r16813, 2145419232 // 0x7FE07FE0 +``` + +For each of the 96 f16x2 D registers, per half (an f16 value `x`): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) // s3987,s3992,s3997 +t = f16(m*(-m) + 0.92724609375) // s4003 fma +u = f16(m*t + 1.375) // s4008 fma + = f16(1.375 + m*(0.92724609375 - m^2)) +E = bits(u)[9:5] // floor(32*frac(u)) -- the top five mantissa bits +F = bits(u)[4:0] // the low five mantissa bits +expval = f16 from bits (E << 10) | (F << 5) // = 2^(E-15) * (1 + F/32) +``` + +i.e. `((u_bits << 5) & 0x7FE07FE0)` keeps `u`'s mantissa and drops its sign and +exponent, so the mantissa lands in the exponent field. Numerically +`expval ≈ 2^(32*frac(u) - 15) = 2^(32u - 47)` and, because the clamp keeps +`u ∈ [1.03125, 1.71875]`, `expval ∈ [2⁻¹⁴, 2⁸]`. +**This is not `exp` and not `exp2(x*log2e)`**: the exponent is the *cubic* +`32*(0.375 + 0.92724609375*m − m³)`, quantised to a 6-bit significand (1.5 % +relative granularity). The 6-bit truncation is why the constant 1.375 is there: +`frac(u)` for `u∈[1,2)` *is* the mantissa. + +The clamp bounds are the guard: `d/dm [0.92724609375m − m³] = 0.92724609375 − 3m²` +vanishes at `m = √(0.92724609375/3) = 0.55615…`, exactly the clamp, so the +exponent saturates at `32·(0.92724609375·0.55615 − 0.55615³) + 12 = 23` +(`expval = 2⁸`) at the top and at `E = 1` (`2⁻¹⁴`) at the bottom. The two +`f64` literals are used only so the clamp is the *exact* f16 value. + +#### (b) in-lane partial sums, s6101–s6180 + +96 `expval` registers are summed in three groups of twelve: each group does +12 `add.f16x2` then `(a+b)+c` four times, giving 4 f16x2 (= 8 f16) per group, +so **each lane reduces its 96 values (8 rows × 12 registers) to 24 partial sums +in 12 f16x2 registers**. + +#### (c) cross-lane row sums, s6181–s6312 + +``` +s6182 L15601: add.f16x2 %r5208,%r5015,%r5021 +s6187 L15612: shfl.sync.bfly.b32 %r5212,%r5208,%r11301,%r5215,%r11312 +s6188 L15616: add.f16x2 %r5217,%r5208,%r5212 +s6193 L15627: shfl.sync.bfly.b32 %r5221,%r5217,%r11310,%r5224,%r11312 +s6194 L15631: add.f16x2 %r5226,%r5217,%r5221 +s6196 L15636: add.f16 %rs2318,%rs2319,%rs2320 +s6197 L15639: mov.b32 %r5423, {%rs2318, %rs2318} +``` + +Eight times (one per row `g, g+8` of the four m-tiles): add the two f16x2 +partials, butterfly over lane bits 0 and 1 (`%r11301 = 1`, `%r11310 = 2`), +add the two halves of the result with `add.f16`, then broadcast into both +halves. Result: **8 row sums** `%r5423 %r5427 %r5471 %r5475 %r5519 %r5523 +%r5567 %r5571` (rows `g`, `g+8` of m-tiles 0…3), covering all 96 columns of each +row because the four lanes with equal `laneid&7` hold different column pairs. + +**There is no row maximum anywhere in this epilogue**: `max.f16x2` (96×) and +`min.f16x2` (96×) are the clamp of (a); the only warp shuffles are the 16 +`shfl.sync.bfly` above. See §6. + +#### (d) reciprocal, s6313–s7081 + +192 `rcp.approx.ftz.f32` = 96 f16x2 reciprocals, each computed as +`cvt.f32.f16 → rcp.approx.ftz.f32 → cvt.rn.f16.f32` on a row-sum register +(duplicated, so each row sum is inverted four times — once per n-tile of that +row): + +``` +s6314 L15935: mov.b32 {hl, hu}, %r5423 +s6317 L15938: rcp.approx.ftz.f32 fl, fl +s6319 L15940: cvt.rn.f16.f32 hl, fl +s6321 L15942: mov.b32 %r5380, {hl, hu} +``` + +#### (e) probabilities, s7082–s7561 + +``` +s7082 L17180: mov.b32 {%rs2343, %rs2346}, %r4968 // expval (row g) +s7083 L17181: mov.b32 {%rs2344, %rs2347}, %r5380 // 1/rowsum (row g) +s7084 L17183: mul.f16 %rs2345,%rs2346,%rs2347 +s7085 L17187: mul.f16 %rs2342,%rs2343,%rs2344 +s7086 L17190: mov.b32 %r5716, {%rs2342, %rs2345} +``` + +192 `mul.f16` → 96 f16x2 results `p = expval * (1/rowsum)` — the row sums +computed in (b)/(c) cancel the constant `2⁻⁴⁷` of (a), so `p_ij ∝ +2^(32·u_ij)`, and `Σ_j p_ij = 1` up to the `rcp.approx` error. + +#### (f) V-transpose, s7562–s7609 + +``` +s7562 L18237: movmatrix.sync.trans.aligned.m8n8.b16 %r5572, %r2149 +s7563 L18240: movmatrix.sync.trans.aligned.m8n8.b16 %r5574, %r2150 +``` + +**48** `movmatrix` on 48 distinct phase-4 D registers (`%r2149…%r2380`, each +exactly once). Each instruction transposes one 8×8 b16 tile built from the 32 +threads' `%r`, i.e. 48 × 64 = 3072 values = the whole 96×32 D tile. (The +epilogue therefore contains 48, not 96, `movmatrix`.) + +#### (g) packs, s7610–s7825 + +``` +s7611 L18384: cvt.rn.satfinite.e4m3x2.f16x2 %rs2918, %r5572 +s7612 L18386: mov.b32 %r6178, {%rs2918, %rs2919} +s7683 L18552: cvt.rn.satfinite.e4m3x2.f16x2 %rs2966, %r5716 +s7684 L18554: mov.b32 %r5884, {%rs2966, %rs2967} +``` + +144 packs in three groups: + +1. s7610–s7681 — from the **movmatrix** results → phase 6's 12 B fragments + (`%r6178…%r6289`, 24 b32), i.e. the transposed V. +2. s7682–s7799 — from the **probabilities** → phase 6's 12 A fragments + (`%r5884…%r6287`, 48 b32). Each fragment consumes 8 consecutive products; + the four halves are re-ordered (`%r5884 ← (p0,p1)`, `%r5886 ← (p2,p3)`, + `%r5885 ← (p4,p5)`, `%r5887 ← (p6,p7)`) to match the e4m3 fragment byte order. +3. s7800–s7825 — more probability packs whose destinations are *not* read after + s7825 (compiler spill; harmless). + +**Inputs:** phase 5's 96 D f16x2, phase 4's 48 D f16x2, `%r11301/%r11310/%r11312`. +**Outputs:** the 5 constants + phase 6's 48 A-register / 24 B-register operands. +**Memory read/written:** none. + +--- + +### E6 — s7874–s8033: residual + per-column table, then pack + +160 statements. Evidence: + +``` +s7877 L19225: add.s64 %rd161, %rd229, 20672 +s7878 L19227: ld.weak.global.ca.v4.u32 { %r6293,%r6294,%r6295,%r6296},[%rd161] +s7880 L19231: ld.weak.global.ca.v4.u32 { %r6297,%r6298,%r6299,%r6300},[%rd162] // +21184 +s7886 L19240: ld.global.v2.u16 {%rs6191, %rs6192}, [%rd232+37072] +s7891 L19252: {add.f16 %rs3062,%rs6197,%rs3064;} +s7892 L19254: mov.b32 %r6342, {%rs3062, %rs3065} +s7987 L19536: cvt.rn.satfinite.e4m3x2.f16x2 %rs3254, %r5852 +``` + +Four things happen, in this order: + +1. **Next-B loads** (s7874–s7880): two `v4.u32` fragments from + `W + 16*laneid + {20672, 21184}` → `%r6293…%r6300`, phase 7's B operand. +2. **Table loads** (s7881–s7889): four `ld.global.v2.u16` from + `W + ((laneid<<2)&12) + {37056, 37072, 37088, 37104}` → 8 f16 + (`%rs6191…%rs6198`). 16 bytes/lane × 32 lanes × 4 words = 512 bytes: a + **per-column** vector covering 32 columns (4 words × 8 columns, each lane + holding the two columns `2t,2t+1` of two of the four 8-column groups). +3. **Residual + column table add** (s7890–s7985): 64 `add.f16`, i.e. 32 f16x2, + computed *in place* on the f16 halves of **phase 2's D** + (`%r1174…%r1325`, the halves unpacked at s2399–s2555 by + `mov.b32 {%rs3064, %rs3067}, %r1175` and its 38 siblings): + + ``` + new_low = table[2t] + D2_half_low s7891 + new_high = table[2t+1] + D2_half_high s7890 + → packed into %r6342, %r6343, %r6352, … %r6493 (32 registers) + ``` + + These 32 registers are **phase 7's C operand**, so phase 7 computes + `D7 = A7·B7 + (D2 + column_table)` — an out-projection plus the residual. +4. **Pack** (s7986–s8033): 32 packs of **phase 6's D** (`%r5852`, `%r5862`, + `%r5912`, `%r5922`, `%r5972`, … — 32 of the 48 D registers, i.e. the 64×32 + output) → 16 b32 = phase 7's A operand (`%r6366 %r6367 %r6368 %r6369`, + `%r6406…`, `%r6446…`, `%r6486…`). + +**Outputs (50 live):** `%r6293 %r6297` (B), the 32 C seeds `%r6342…%r6493`, the +16 packed A registers. **Memory:** 2 weight loads + 4 table reads. + +--- + +### E7 — s8050–s8056: next-B loads + +``` +s8053 L19761: add.s64 %rd163, %rd234, 21696 +s8054 L19763: ld.weak.global.ca.v4.u32 { %r6495,%r6496,%r6497,%r6498},[%rd163] +s8055 L19765: add.s64 %rd164, %rd234, 22208 +s8056 L19767: ld.weak.global.ca.v4.u32 { %r6499,%r6500,%r6501,%r6502},[%rd164] +``` + +Two 16-byte/lane fragments of `W + 16*laneid + {21696, 22208}` = phase 8's B +operand (weight block `[21696, 22720)` per the phase table). Nothing else. + +### E8 — s8081–s8087: next-B loads + +Same shape, offsets `+22720` and `+23232`: + +``` +s8084 L19942: add.s64 %rd165, %rd236, 22720 +s8085 L19944: ld.weak.global.ca.v4.u32 { %r6744,%r6745,%r6746,%r6747},[%rd165] +s8086 L19946: add.s64 %rd166, %rd236, 23232 +s8087 L19948: ld.weak.global.ca.v4.u32 { %r6748,%r6749,%r6750,%r6751},[%rd166] +``` + +→ phase 9's B operand, weight block `[22720, 23744)`. + +### E9 — s8112–s8282: score-bias C-seed loads + pack of phase 8's D + +171 statements, 24 loads + 80 packs: + +``` +s8116 L20125: ld.weak.global.ca.v4.u32 { %r6993,…%r6996},[%rd167] // +23744 + … +s8162 L20217: ld.weak.global.ca.v4.u32 { %r7085,…%r7088},[%rd190] // +23744+23*512 = +35520 +``` + +* **24 loads** at `W + 16*laneid + 23744 + 512*i`, `i = 0…23` — the phase-10 + score-bias seeds, byte block `[23744, 36032)` = 12288 bytes = 6144 f16. This + is the twin of phase 5's C-seed block (`[8384, 20672)`), loaded the same way + in phase 4's epilogue (s3764–s3814). +* **80 packs / 40 b32**, whose sources are *all* registers written by **phase 8's + mma** (`%r6503…%r6744`, the D pairs of s8057–s8080) — phase 9's D + (`%r6752…%r6983`) is **not** read here; it is consumed by E10's `movmatrix` + block instead (s11905: `movmatrix.sync.trans.aligned.m8n8.b16 %r10175, + %r6752`). The 40 packed b32 split into + * phase 10's four A-fragment sets: `%r7281 %r7282 %r7283 %r7284`, + `%r7401…`, `%r7521…`, `%r7641…` (16 b32, e.g. `s8237: mov.b32 %r7281, + {%rs3334, %rs3335}` from `cvt` of `%r6503`/`%r6523` at s8235–s8236), and + * phase 10's twelve B-fragment pairs `%r7535 %r7536 … %r7645 %r7646` + (24 b32, e.g. `s8163–s8165: cvt …%r6523; cvt …%r6503; mov.b32 %r7535, + {%rs3286, %rs3287}`). + + The first A set and the first B set are **bit-identical**: both are + `{pack(%r6503), pack(%r6523)}` (`%r7281` from s8235–s8237, `%r7535` from + s8163–s8165). Whatever the score GEMM's two operands are, phase 10 gets one + of them twice at fragment 0. + +**The C-seed layout** (identical for phase 5 and phase 10): the four C registers +of one mma are the four u32 of one 16-byte lane slot, and + +``` +C(m, n) = load_tile(4*(n>>1) + m) + 4*(n&1) [register index within the block] +byte = base + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1) +``` + +so the bias tile index runs `4*(n>>1) + m` (stride 512 bytes) over 4 m-tiles and +6 `(n>>1)` groups = 24 tiles = 12288 bytes. Verified from phase 5's own mma +operands: `s3935 C=%r2390, s3936 C=%r2392, s3937 C=%r2406, s3947 C=%r2394, +s3959 C=%r2398, s3971 C=%r2402, s3982 C=%r2484`. + +--- + +### E10 — s8331–s12168: softmax, second window + +**Identical code to E5** with shifted registers; the op histogram is byte-for-byte +the same (1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 `cvt.rn.f16.f64`, 192 each +`fma.rn.f16x2` / `cvt.f32.f16` / `rcp.approx.ftz.f32` / `mul.f16`, 144 packs, +48 `movmatrix`). It re-uses E5's constants (`%f2085 %fd767 %fd769 %f2087 +%f2089`, defined at s3984–s4004) and E5's shfl operands `%r11301 %r11310 +%r11312`, so it contains no `mov.f32`/`mov.f64` of its own. + +Sub-sections: + +| range | what | +|---|---| +| s8331–s10443 | 96 exponent groups (scale/clamp/cubic/`and.b32 0x7FE07FE0`) | +| s10444–s10523 | 80 in-lane partial-sum `add.f16x2` | +| s10524–s10655 | 16 `shfl.sync.bfly` → 8 row sums (`s10530 L27701`, `s10651 L27990`) | +| s10656–s11424 | 192 `rcp.approx.ftz.f32` (`s10660 L28027`) | +| s11425–s11904 | 192 `mul.f16` → 96 probabilities | +| s11905–s11952 | 48 `movmatrix` (`s11905 L30326: movmatrix… %r10175, %r6752`) | +| s11953–s12168 | 144 packs (`s11953 L30470`) | + +**Inputs:** phase 10's 96 D (`%r7169…`), phase 9's 48 D. **Outputs (72 live):** +phase 11's 12 A fragments (`%r10487…%r10892`) + 12 B fragments (`%r10781…`) ++ the 4 constants. **Memory:** none. + +--- + +### E11 — s12217–s12271: next-B loads + pack + +55 statements: + +``` +s12220 L31314: add.s64 %rd191, %rd240, 36032 +s12221 L31316: ld.weak.global.ca.v4.u32 { %r10896,…%r10899},[%rd191] +s12222 L31318: add.s64 %rd192, %rd240, 36544 +s12223 L31320: ld.weak.global.ca.v4.u32 { %r10900,…%r10903},[%rd192] +s12224 L31323: cvt.rn.satfinite.e4m3x2.f16x2 %rs4879, %r10515 +s12226 L31328: mov.b32 %r10968, {%rs4878, %rs4879} +``` + +* two weight fragments at `W + 16*laneid + {36032, 36544}` → phase 12's B; +* **32 packs** of phase 11's D (`%r10455…%r10645`) → 16 b32 = phase 12's A + (`%r10968 %r10969 %r10970 %r10971`, `%r11008…`, `%r11048…`, `%r11088…`). + +**Unlike E6, no table**: phase 11's output is requantised only, because +the residual for the second attention branch is folded into phase 12's C operand +(`%r6334 %r6335` = phase 7's D, see the phase table). + +#### Shape of the attention region (E5–E12) + +``` +P3 A = prologue tile, B = W+6336 C = 0 → D_K (96×32) +P4 A = prologue tile, B = W+7360 C = 0 → D_QV (96×32) epilogue E4 packs both + E4 packs D_K → P5 B (s3817: %r2932), E4 loads P5 C = bias@8384 (s3764–s3814) +P5 A = pack(D_QV) B = pack(D_K) C = bias@8384 → scores 64×96 + E5: softmax over the 96 columns (no row max), 48 movmatrix(D_QV), + pack → P6 A (48 b32) + P6 B (24 b32) +P6 A = pack(P) B = pack(transpose(D_QV)) C = 0 → D_PV (64×32) + E6: pack(PV) → P7 A (16 b32); P7 C = D_QV2 + column table@37056; loads P7 B +P7 C = residual → D7 epilogue E7 loads P8 B +P8 A = prologue tile, B = W+21696, C = 0 → D8 epilogue E9 packs D8 → P10 A and B +P9 A = prologue tile, B = W+22720, C = 0 → D9 (D9 only reaches E10's movmatrix) +P10 A = pack(D8) B = pack(D8) C = bias@23744 → scores 64×96 + E10: same softmax + transpose(D9) + packs → P11 A/B +P11 … → E11 packs → P12 A; P12 C = D7 (residual) +``` + +Window 2 therefore mirrors window 1 except that phase 10's *two* operands both +come out of phase 8 (see E9), while the transpose of phase 9's D supplies +phase 11. + +--- + +### E12 — s12288–s13174: RMS norm before the MLP + +887 statements, no stores, one `ld.global.v2.u16` group, two weight groups. +Structure: + +| range | stmts | op | +|---|---|---| +| s12288–s12415 | 128 | 32 × `x·x` squares of phase 12's D | +| s12416–s12431 | 16 | in-lane pairwise `add.f16x2` | +| s12432–s12555 | 124 | 8 rows × (`add` + 2 `shfl.sync.bfly` + `add` + `add.f16`) | +| s12556–s12652 | 97 | `+ eps`, broadcast into 16 b32 | +| s12653–s12909 | 257 | 32 × `rsqrt.approx.ftz.f32` | +| s12910–s12918 | 9 | gain loads `+37120/37136/37152/37168` | +| s12919–s13014 | 96 | `inv · gain` | +| s13015–s13110 | 96 | `x · (inv·gain)` | +| s13111–s13117 | 7 | next-B loads `+37184/+37696` | +| s13118–s13126 | 9 | next-C loads `+38208/38224/38240/38256` | +| s13127–s13174 | 48 | 32 packs → phase 13's A | + +Evidence: + +``` +s12289 L31548: mul.f16 %rs4913,%rs5740,%rs5740 // square of a D half +s12438 L31945: shfl.sync.bfly.b32 %r11149,%r11145,%r11301,%r11152,%r11312 +s12556 L32255: cvt.rn.f16.f64 %rs5126, %fd770 // eps = 2^-13 +s12657 L32555: rsqrt.approx.ftz.f32 fl, fl +s12915 L32972: ld.global.v2.u16 {%rs6199, %rs6200}, [%rd243+37136] +s13015 L33265: mul.f16 %rs5514,%rs5740,%rs5322 // D_half * (inv*gain) +s13114 L33557: add.s64 %rd193, %rd245, 37184 +s13123 L33572: ld.global.u32 %r11553, [%rd248+38208] +s13128 L33580: cvt.rn.satfinite.e4m3x2.f16x2 %rs5703, %r15389 +``` + +**What it computes.** For each of the 8 rows a lane holds (8 columns each): + +``` +sumsq[row] = Σ_{c=0..31} x[row,c]^2 (f16, 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2^-13))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` + +* **no mean subtraction and no `1/N`**: the quantity is the *raw* sum of the 32 + squares in a row plus the constant `2^-13`; the mean is not formed. +* `gain[c]` is read from `W + ((laneid<<2)&12) + {37120, 37136, 37152, 37168}` + (8 f16 per lane = 32 columns), so the gain is per column, constant across rows. +* the `inv` register is duplicated into both halves of a b32 before use + (`mov.b32 %r11318, {%rs5127, %rs5130}` at s12559), so one row-sum value serves + all four n-tiles of that row (32 `rsqrt` for 8 row sums). +* the norm's *bias* is not added here — it is folded into phase 13's C operand, + loaded at the end of this epilogue (`+38208…+38256`). + +**Outputs (22):** `%r11383 %r11387` (phase 13 B, from `+37184/+37696`), +`%r11553 %r11563 %r11573 %r11583` (phase 13 C), 16 packed A registers +(`%r11456 %r11457 %r11458 %r11459`, `%r11496…`, `%r11536…%r11539`), the 32 f16x2 +normalised values `%r15389…%r15420` (re-packed in E14), and the 32 +half-registers `%rs5737 %rs5743 … %rs5923` still read by E13's bias add. + +--- + +### E13 — s13191–s13899: clamped cubic activation, column bias, pack + +709 statements. This is the only epilogue that materialises `%f2598…%f2601` +(the four activation constants of §1.2). + +``` +s13192 L33803: mov.f32 %f2598, 0f3ED306EB +s13198 L33817: mov.f32 %f2600, 0f3F000000 // 0.5 +s13201 L33824: mov.f32 %f2601, 0f40000000 // 2.0 +s13204 L33832: neg.f16x2 %r11589,%r11588 +s13205 L33836: max.f16x2 %r11591,%r11424,%r11589 +s13206 L33840: min.f16x2 %r11594,%r11591,%r11588 +s13207 L33844: abs.f16x2 %r11597,%r11594 +s13208 L33848: mul.f16x2 %r11599,%r11586,%r11597 +s13209 L33852: sub.f16x2 %r11602,%r11585,%r11599 +s13210 L33856: mul.f16x2 %r11605,%r11594,%r11602 +s13211 L33860: add.f16x2 %r11608,%r11587,%r11605 +s13212 L33864: mul.f16x2 %r11611,%r11424,%r11608 +``` + +Per element, over each of the 32 f16x2 D registers of phase 13 +(`%r11424 %r11425 %r11504…`, 64 f16 per lane): + +``` +y = clamp(x, -2, +2) +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a *cubic ramp*, not a sigmoid: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`; `g(1) = 0.831055` where `x·sigmoid(x) = +0.730957`. **Reproduce the formula, not SiLU/GELU.** + +Then: + +| range | op | +|---|---| +| s13191–s13739 | 32 activation groups (each group 4 constants + 9 f16x2 ops) | +| s13740–s13746 | next-B loads: `+38272` → `%r12514…%r12517`, `+38784` → `%r12518…%r12521` | +| s13747–s13755 | lane-shift setup + `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {39296, 39312, 39328, 39344}` | +| s13756–s13851 | 64 `add.f16` — table add, written over the **activation inputs** | +| s13852–s13899 | 32 packs of the activation outputs → phase 14's A | + +Evidence for the table add: + +``` +s13752 L35747: ld.global.v2.u16 {%rs6207, %rs6208}, [%rd253+39312] +s13756 L35752: {add.f16 %rs5738,%rs6214,%rs5740;} +s13757 L35756: {add.f16 %rs5735,%rs6213,%rs5737;} +s13758 L35759: mov.b32 %r12563, {%rs5735, %rs5738} +s13853 L36043: cvt.rn.satfinite.e4m3x2.f16x2 %rs5927, %r11611 +``` + +`%rs5737/%rs5740` are the halves of `%r11424` (phase 13's D, split at s13191), +so `%r12563 = phase13_D + table[column]`. The 32 such registers +(`%r12563 %r12564 %r12573 %r12574 … %r12713 %r12714`) are **phase 14's C +operand**; `%r12514 %r12518` are phase 14's B fragments (weight image). + +**Outputs (54 live):** `%f2598…%f2601` (the constants — consumed again by E15, +E17, E19), the 32 C seeds, the 16 packed A registers, `%r12514 %r12518`. + +--- + +### E14 — s13916–s13979: next B/C loads + pack + +64 statements: + +``` +s13919 L36268: add.s64 %rd197, %rd255, 39360 +s13920 L36270: ld.weak.global.ca.v4.u32 { %r12716,…%r12719},[%rd197] +s13921 L36272: add.s64 %rd198, %rd255, 39872 +s13922 L36274: ld.weak.global.ca.v4.u32 { %r12720,…%r12723},[%rd198] +s13928 L36283: ld.global.u32 %r12886, [%rd258+40384] +s13929 L36284: ld.global.u32 %r12896, [%rd258+40400] +s13930 L36285: ld.global.u32 %r12906, [%rd258+40416] +s13931 L36286: ld.global.u32 %r12916, [%rd258+40432] +s13933 L36293: cvt.rn.satfinite.e4m3x2.f16x2 %rs5959, %r15389 +s13934 L36295: mov.b32 %r12789, {%rs5959, %rs5960} +``` + +* phase 15's B at `W + 16*laneid + {39360, 39872}`; +* **phase 15's C/bias**: 4 `ld.global.u32` at `W + ((laneid<<2)&12) + + {40384, 40400, 40416, 40432}` → `%r12886 %r12896 %r12906 %r12916`. Each of + those four u32 is used **in both halves** of an mma C operand + (`{%r12886, %r12886}` at s13980), i.e. a per-column bias replicated over the + 16 rows of a tile and reused by all four m-tiles; +* **32 packs of `%r15389…%r15420`** — the *normalised* values E12 produced, so + phase 15's A operand is bit-identical to phase 13's A operand (phases 13 and + 15 are two parallel GEMMs off the same normed tile). + +--- + +### E15 — s13996–s14595: clamped cubic activation, pack + +600 statements, histogram: 96 `mul.f16x2`, 32 each `neg/max/min/abs/sub/add` +f16x2, 128 `cvt.rn.f16.f32`, 144 `mov.b32`, 32 packs, 2 weight loads — and +**no constants of its own** and **no `ld.global`**. + +``` +s13997 L36516: cvt.rn.f16.f32 low, %f2598 // constants from E13 +s14005 L36539: neg.f16x2 %r12922,%r12921 +s14006 L36543: max.f16x2 %r12924,%r12757,%r12922 +s14009 L36555: mul.f16x2 %r12932,%r12919,%r12930 +s14013 L36571: mul.f16x2 %r12944,%r12757,%r12941 +s14545 L38441: ld.weak.global.ca.v4.u32 { %r13847,…%r13850},[%rd199] // +40448 +s14547 L38445: ld.weak.global.ca.v4.u32 { %r13851,…%r13854},[%rd200] // +40960 +``` + +Same function as E13: `out = x·(0.5 + y·(0.412109375 − 0.0810546875|y|))`, +`y = clamp(x,±2)`, over phase 15's 32 D registers (`%r12757 %r12758 …`), then +32 packs **of the activation outputs** (`%r12944` at s14549, `%r13060` at s14548, +…) → phase 16's A (`%r13919…%r14042`), plus phase 17's B fragments from +`W + 16*laneid + {40448, 40960}`. **No column-bias add.** + +### E16 — s14612–s14675: next B/C loads + pack + +Identical shape to E14 with offsets `+41472/+41984` (B) and +`+42496/42512/42528/42544` (C, 4 `ld.global.u32` → `%r14218 %r14228 %r14238 +%r14248`), followed by **32 packs of `%r15389…%r15420` — again the normed tile +E12 produced** — giving phase 17's A (`%r14121 %r14122 %r14123 %r14124`, +`%r14161…`, `%r14201…`). + +Evidence: `s14616 L38678: ld.weak.global…[%rd201]`, `s14624 L38691: ld.global.u32 +%r14218, [%rd265+42496]`, `s14629 L38699: cvt.rn.satfinite.e4m3x2.f16x2 %rs6023, +%r15389` (the pack source is E12's `%r15389`, defined at s13017). + +### E17 — s14692–s15291: clamped cubic activation, pack + +600 statements; identical histogram to E15. + +``` +s14693 L38924: cvt.rn.f16.f32 low, %f2598 +s14701 L38947: neg.f16x2 %r14254,%r14253 +s14702 L38951: max.f16x2 %r14256,%r14089,%r14254 // phase 17's D +s14709 L38979: mul.f16x2 %r14276,%r14089,%r14273 +s15241 L40849: ld.weak.global.ca.v4.u32 { %r15179,…},[%rd203] // +42560 +s15244: cvt.rn.satfinite.e4m3x2.f16x2 … +``` + +Activation on phase 17's D, 32 packs **of those activation outputs** (`%r14276` +at s15245, `%r14392` at s15244, …) → phase 18's A, 2 weight loads at +`W + 16*laneid + {42560, 43072}` → phase 18's B. No constants, no `ld.global`. + +### E18 — s15308–s15371: next B/C loads + pack + +Same shape as E14/E16: B at `+43584/+44096`, C at +`+44608/44624/44640/44656` → `%r15550 %r15560 %r15570 %r15580`, then **32 packs +of `%r15389…%r15420` — the normed tile for the fourth time** → phase 19's A +(`%r15453…%r15576`). Evidence: `s15312 L41086: ld.weak.global…`, +`s15320 L41100: ld.global.u32 %r15550, [%rd272+44608]`, and +`s15325 L41107: cvt.rn.satfinite.e4m3x2.f16x2 %rs6087, %r15389` (source defined +at s13017). + +### E19 — s15388–s15987: clamped cubic activation, pack + +600 statements; identical histogram to E15/E17. + +``` +s15389 L41332: cvt.rn.f16.f32 low, %f2598 +s15397 L41355: neg.f16x2 %r15586,%r15585 +s15398 L41359: max.f16x2 %r15588,%r15421,%r15586 // phase 19's D +s15399 L41363: min.f16x2 %r15591,%r15588,%r15585 +s15937 L43257: ld.weak.global.ca.v4.u32 { %r16511,…},[%rd207] // +44672 +s15940 L43270: cvt.rn.satfinite.e4m3x2.f16x2 … +``` + +Activation on phase 19's D, 32 packs **of those activation outputs** (`%r15608` +at s15941, `%r15724` at s15940, …) → phase 20's A (`%r16583…%r16706`), 2 +weight loads at `W + 16*laneid + {44672, 45184}` → phase 20's B. + +#### Shape of the whole MLP region (E12–E20) + +Putting the pack sources and the C operands together (all verified by tracing each +`mov.b32 %rX, {%rsA, %rsB}` back through its two `cvt` statements): + +``` +E12 normed tile N (32 f16x2, %r15389…%r15420) + ├─ pack → phase 13 A (s13127) phase 13: A=N, B=W13, C=bias@38208 → SiLU (E13) + │ pack of SiLU → phase 14 A (s13852) + │ phase 14: C = 0 → D14 + ├─ pack → phase 15 A (s13932) phase 15: A=N, B=W15, C=bias@40384 → SiLU (E15) + │ pack of SiLU → phase 16 A (s14548) + │ phase 16: C = D14 → D16 + ├─ pack → phase 17 A (s14628) phase 17: A=N, B=W17, C=bias@42496 → SiLU (E17) + │ pack of SiLU → phase 18 A (s15244) + │ phase 18: C = D16 → D18 + └─ pack → phase 19 A (s15324) phase 19: A=N, B=W19, C=bias@44608 → SiLU (E19) + pack of SiLU → phase 20 A (s15940) + phase 20: C = D18 → D20 (E20) +``` + +so the four branches share one input tile, each has its own weight+bias+SiLU, and +their outputs are folded into a running residual (`D16 = … + D14`, +`D18 = … + D16`, `D20 = … + D18`). The four `SiLU` sites are byte-identical +blocks of the same f16 expression with the same four constants. + +--- + +### E20 — s16004–s16417: pack → plane-arena scatter → 8-lane merge → next B/C + +414 statements. Four sub-sections: + +#### (a) requantise, s16004–s16051 + +32 `cvt.rn.satfinite.e4m3x2.f16x2` + 16 `mov.b32` → `%r262 … %r277` +(phase 20's 64×32 output as 16 b32 = 32 e4m3 values per lane). + +#### (b) plane-arena scatter, s16052–s16326 + +``` +s16052 L43599: ld.param.u64 %rd276, [%rd368+48] +s16053 L43600: cvta.to.global.u64 %rd37, %rd276 +s16055 L43604: shr.u32 %r278, %r16743, 2 // g = laneid>>2 +s16056 L43605: and.b32 %r279, %r16743, 3 // t = laneid&3 +s16059 L43608: add.s32 %r17110, %r6, %r17108 // y = %r6 + (laneid>>5) +s16065 L43614: add.s32 %r17111, %r1, %r17109 // x = %r1 + (g&7) +s16070 L43619: shl.b32 %r17112, %r17111, 3 +s16071 L43620: mad.lo.s32 %r280, %r18179, %r17110, %r17112 +s16072 L43621: add.s32 %r17113, %r279, %r280 +s16073 L43622: selp.b32 %r281, -1, %r17113, %p35 +s16074 L43623: setp.lt.s32 %p317, %r281, 0 +s16075 L43624: @%p317 bra $L__BB1_258 +s16078 L43628: st.global.u32 [%rd278], %r262 +s16080 L43631: or.b32 %r282, %r279, 4 +s16087 L43639: st.global.u32 [%rd280], %r263 +``` + +The stride register is `%r18179 = shl.b32 %r18179, %r364, 3` (s2219): **8·ex**, +and `%r364/%r365 = ld.param.v2.u32 [param_0+0]`. + +**All sixteen stores** (`s` = `st.global.u32 [%rd37 + 4*index], value`), where +`idx = stride*y + (x<<3) + d`: + +| # | statement | value | stride | y | x | d | +|---|---|---|---|---|---|---| +| 1 | s16078 | `%r262` | `%r18179` | `%r6 + (laneid>>5)` | `%r1 + ((laneid>>2)&7)` | `t` | +| 2 | s16087 | `%r263` | `%r18179` | as above | as above | `t\|4` | +| 3 | s16113 | `%r264` | `%r18180 = %r364<<3` | `%r6 + ((g+8)>>3)` | `%r1 + ((g+8)&7)` | `t` | +| 4 | s16121 | `%r265` | `%r18180` | as above | as above | `t\|4` | +| 5 | s16147 | `%r266` | `%r18181` | `%r6 + ((g+16)>>3)` | `%r1 + ((g+16)&7)` | `t` | +| 6 | s16155 | `%r267` | `%r18181` | as above | as above | `t\|4` | +| 7 | s16181 | `%r268` | `%r18182` | `%r6 + ((g+24)>>3)` | `%r1 + ((g+24)&7)` | `t` | +| 8 | s16189 | `%r269` | `%r18182` | as above | as above | `t\|4` | +| 9 | s16215 | `%r270` | `%r18183` | `%r6 + ((g+32)>>3)` | `%r1 + ((g+32)&7)` | `t` | +| 10 | s16223 | `%r271` | `%r18183` | as above | as above | `t\|4` | +| 11 | s16249 | `%r272` | `%r18184` | `%r6 + ((g+40)>>3)` | `%r1 + ((g+40)&7)` | `t` | +| 12 | s16257 | `%r273` | `%r18184` | as above | as above | `t\|4` | +| 13 | s16283 | `%r274` | `%r18185` | `%r6 + ((g+48)>>3)` | `%r1 + ((g+48)&7)` | `t` | +| 14 | s16291 | `%r275` | `%r18185` | as above | as above | `t\|4` | +| 15 | s16317 | `%r276` | `%r18186` | `%r6 + ((g+56)>>3)` | `%r1 + ((g+56)&7)` | `t` | +| 16 | s16325 | `%r277` | `%r18186` | as above | as above | `t\|4` | + +with `g = laneid>>2`, `t = laneid&3`, every `%r1818N` equal to `%r364<<3` +(s16090, s16124, s16158, s16192, s16226, s16260, s16294), and each block guarded +by `p35…p43 = (y<0) | (y ≥ %r365) | (laneid>255) | (x<0) | (x ≥ %r364)`; a +guard failure stores `-1` as the index, which the following `setp.lt.s32 +%p, %idx, 0` + `bra` turns into "skip the store". Note `(g+8j)&7 = g&7` and +`(g+8j)>>3 = (g>>3)+j`, so blocks 1…7 only differ from block 0 in the row they +land on (`%r6 + g>>3 + j`) and in the value written. + +The 16 stored b32 are the requantised 64×32 output of phase 20, so this writes +`8*32 = 256` bytes per row-stride unit of a `%r364`-wide arena. + +#### (c) 8-lane merge, s16327–s16369 + +``` +s16332 L43915: and.b32 %r17575, %r17171, 4 // laneid & 4 +s16334 L43917: setp.eq.s32 %p389, %r17575, 0 +s16338 L43921: shfl.sync.down.b32 %r17580|%p390, %r262, %r17576, %r17578, %r17579 +s16339 L43922: shfl.sync.up.b32 %r17581|%p391, %r266, %r17577, %r17578, %r17579 +s16340 L43923: selp.b32 %r17490, %r262, %r17581, %p389 +s16341 L43924: selp.b32 %r17510, %r17580, %r266, %p389 +``` + +**Eight** `shfl.sync.down/up` pairs, all with **delta = 4** — the *third* +operand (`%r17576 = mov.u32 4`, s16333) is the PTX `b` (delta/mask) operand and +the fourth is the group/width operand `c`: `31` for the `.down` (`%r17578`, +s16336) and `0` for the `.up` (`%r17577`, s16335) — with `c = 0` the "same +group" test `~(c-1) = 0` always succeeds, so the up-shuffle is unrestricted. +Membermask is `%r17579 = mov.u32 -1` (s16337). The selection predicate is +`%p389 = (laneid & 4) == 0`: + +``` +down = a[lane+4] (shfl.sync.down, delta 4) +up = a[lane-4] (shfl.sync.up, delta 4) +dst1 = p389 ? own_low : up // lanes 0-3: own low ; lanes 4-7: lane-4's high +dst2 = p389 ? down : own_high // lanes 0-3: lane+4's low ; lanes 4-7: own high +``` + +so each of the eight destinations ends up holding, in its two halves, the values +of both members of the pair `{lane, lane±4}`. + +The eight pairs take `(src_low, src_high)` = +`(%r262,%r266) (%r264,%r268) (%r263,%r267) (%r265,%r269) (%r270,%r274) +(%r272,%r276) (%r271,%r275) (%r273,%r277)` and write, in order, +`%r17490 %r17510 %r17530 %r17550 %r17492 %r17512 %r17532 %r17552 %r17491 %r17511 +%r17531 %r17551 %r17493 %r17513 %r17533 %r17553` (s16340–s16369). Those sixteen +are **phase 21's A operand**: `{%r17490 %r17491 %r17492 %r17493}`, `{%r17510 …}`, +`{%r17530 …}`, `{%r17550 …}` (four fragments of four, confirmed from the 32 mma +at s16418–s16449); the same sixteen are re-read as +`%r17490 %r17491 %r17492 %r17493 %r17497 %r17510 %r17511 %r17512 %r17513 %r17530 +%r17531 %r17532 %r17533 %r17550 %r17551 %r17552 %r17553` by the loads that +follow. Net effect: the sixteen 32-bit payloads that eight lanes scattered are +re-paired into four A fragments of four before the next GEMM. + +#### (d) next B/C loads, s16370–s16417 + +``` +s16373 L43958: add.s64 %rd309, %rd326, 45696 +s16374 L43960: ld.weak.global.ca.v4.u32 { %r17173,…},[%rd309] // … +45696+512*i, i=0..15 +s16410 L44029: ld.global.u32 %r17247, [%rd329+53888] +s16411 L44030: ld.global.u32 %r17257, [%rd329+53904] + … +53920, +53936, +53952, +53968, +53984, +54000 +``` + +* **16 weight fragments** at `W + 16*laneid + 45696 + 512*i` → phase 21's B + (`%r17173 … %r17236`); +* **8 bias words** at `W + ((laneid<<2)&12) + {53888…54000}` → `%r17247 %r17257 + %r17327 %r17337 %r17407 %r17417 %r17487 %r17497` = **phase 21's C seed** + (128 bytes per lane = 64 f16 per lane). + +**Inputs:** phase 20's D, `%r1/%r6/%r364/%r365/%r18179`, `W`, `S`. +**Outputs (58 live):** `%r262…%r277` (they are *read again* inside this same +epilogue by the merge), the 16 merged A registers, phase 21's B and C, +`%rd369 %rd370` (cached weight pointer). + +--- + +### E21 — s16450–s16606: pack → surface scatter → `%tid.x` → next B/C + +157 statements. + +#### (a) requantise, s16450–s16472 + +``` +s16450 L44261: add.s64 %rd38, %rd369, 54016 +s16451 L44263: cvt.rn.satfinite.e4m3x2.f16x2 %rs6215, %r17298 +s16453 L44269: cvt.rn.satfinite.e4m3x2.f16x2 %rs6218, %r17388 +s16455 L44274: mov.b32 %r305, {%rs6217, %rs6218} +``` + +16 packs of phase 21's D → six b32 `%r305…%r310` plus the two `v2.u16` payloads +`{%rs6215,%rs6216}` and `{%rs6229,%rs6230}`. + +#### (b) coordinate / surface scatter, s16473–s16592 + +``` +s16473 L44316: ld.param.v2.u32 {%r17597, %r17598}, [%rd370] // param block +0 +s16474 L44317: shr.u32 %r313, %r17598, 1 // ey>>1 +s16475 L44318: shr.u32 %r314, %r17597, 1 // ex>>1 +s16476 L44319: shl.b32 %r315, %r314, 3 // 8*(ex>>1) +s16477 L44320: mul.lo.s32 %r316, %r313, %r315 // row stride +s16481 L44326: ld.param.u64 %rd331, [%rd370+56] +s16482 L44327: cvta.to.global.u64 %rd39, %rd331 // destination buffer +s16487 L44332: bfi.b32 %r17603, %r17602, %r17599, 1, 31 +s16490 L44335: shr.s32 %r319, %r17605, 1 // y0 = %r6 >> 1 (arith) +s16506 L44351: mad.lo.s32 %r321, %r315, %r17606, %r17610 +s16507 L44352: or.b32 %r17611, %r318, %r321 +s16513 L44359: st.global.v2.u16 [%rd333], {%rs6215, %rs6216} +``` + +The destination pointer is **param block +56**, not the plane arena; extents come +from `param+0` and are *halved*. Four index bases are formed, each guarded by +`p43 = (y<0)|(y≥(ey>>1))|(tile bits>3)|(x<0)|(x≥(ex>>1))`: + +| base | statement | y | x | stores | +|---|---|---|---|---| +| `%r321` | s16506 | `(%r6>>1) + (((laneid>>5)&~2)\|((g&1)<<1))` | `(%r1>>1) + ((laneid>>3)&3)` | s16513 `v2.u16 {%rs6215,%rs6216}` at `+t`; s16522 `u32 %r305` at `+(t\|4)` | +| `%r325` | s16542 | recomputed from `g+8` | recomputed | s16549 `u32 %r306` at `+t`; s16557 `u32 %r307` at `+(t\|4)` | +| `%r328 = %r321 + %r316` | s16559 | (as `%r321`) | (as `%r321`) | s16566 `u32 %r308` at `+t`; s16574 `u32 %r309` at `+(t\|4)` | +| `%r331 = %r325 + %r316` | s16576 | (as `%r325`) | (as `%r325`) | s16583 `u32 %r310` at `+t`; s16591 `v2.u16 {%rs6229,%rs6230}` at `+(t\|4)` | + +So: **8 guarded stores**, 6 × `st.global.u32` and 2 × `st.global.v2.u16`, index +`base + (t or t|4)` in units of 4 bytes. (`%r325` and `%r328` are equal — see §6.) + +#### (c) next B/C and `%tid.x`, s16593–s16606 + +``` +s16595 L44456: mov.u32 %r18203, %tid.x +s16599 L44463: ld.weak.global.ca.v4.u32 { %r17629,…%r17632},[%rd348] // +54016 +s16605 L44472: ld.global.u32 %r17703, [%rd352+54528] +s16606 L44473: ld.global.u32 %r17713, [%rd352+54544] +``` + +phase 22's B fragment (`W + 16*laneid + 54016`) and two C seeds +(`W + ((laneid<<2)&12) + {54528, 54544}`). + +**Outputs (5 live):** `%r17597` (the `param+0` v2.u32), `%r17629`, +`%r17703 %r17713`, `%r18203` (`%tid.x`) — two of the eighteen values the cut +returns. + +--- + +### E22 — s16615–s17222: the final epilogue + +608 statements; it consumes the eighteen values returned by the cut +(`%r17597`, `%r18203` and the sixteen D registers `%r17634 %r17635 %r17644 +%r17645 %r17654 %r17655 %r17664 %r17665 %r17674 %r17675 %r17684 %r17685 +%r17694 %r17695 %r17704 %r17705`) and writes the surfaces. + +#### (a) cross-lane row max, s16615–s16765 + +``` +s16616 L44534: and.b32 %r17717, %r17714, 7 // row key = laneid & 7 +s16617 L44535: shr.u32 %r17718, %r17714, 3 // column group = laneid >> 3 +s16618 L44536: and.b32 %r17719, %r17714, 3 +s16620 L44537: selp.b32 %r17720, %r17635, %r17634, %p430 // pick by (laneid&3) +s16636 L44554: bfi.b32 %r17733, %r17717, %r17732, 2, 3 +s16639 L44556: shfl.sync.idx.b32 %r17736|%p434, %r17722, %r17733, %r17734, %r17735 +s16657 L44574: selp.b32 %r334, %r17748, %r17750, %p440 +``` + +Two identical blocks (rows `g` from the D pairs `{r17634,r17635}`, `{r17654,r17655}` +and rows `g+8` from `{r17674,r17675}`, `{r17694,r17695}`), each doing: + +1. a `selp` chain over `(laneid&3)` selects one of the four D pairs into + `%r17722/%r17725/%r17728/%r17731` (the four n-tiles of the row segment); +2. four `shfl.sync.idx.b32` with `srcLane = (laneid&7) | ((((laneid>>3)+d)&3)<<2)` + for `d = 0, 1, 2, -1` (`%r17734 = mov.u32 31`, `%r17735 = mov.u32 -1`); +3. a `selp` chain over `laneid>>3` picks between the four shuffled values. + +Result: `%r334…%r337` (row `g`) and `%r339…%r342` (row `g+8`) hold the +**per-lane row maximum over the 8 columns**; the following `max.f16` / `max.f16x2` +chain (`s16792–s16799`, `s16800…`) reduces those four registers, then `sub.f16x2 +%r17849, %r334, %r17863` (`s16800`) subtracts the row max: **this is a real row +max**, done with `shfl.sync.idx`, unlike E5's. + +#### (b) bounds check, s16766–s16784 + +``` +s16774 L44693: setp.ge.u32 %p462, %r346, %r17597 // x >= ex (%r17597 = param+0 low) +s16775 L44694: setp.ge.u32 %p463, %r348, %r17598 // y >= ey +s16780 L44699: @%p466 bra $L__BB1_307 +s16784 L44704: ld.param.u64 %rd353, [%rd372+112] // surface A (param+112) +s16766 L44685: shr.s32 %r17836, %r18203, 31 // %r18203 = %tid.x (E21) +``` + +`%r18203` is used to derive `%r345 = tid.x - ((tid.x+round)>>3<<3)` (row/tile +offset), `%r346 = %r345 + %r1` (x), `%r348 = (…>>3) + %r6` (y); out-of-range +lanes jump to `$L__BB1_307` and skip (b)…(e). + +#### (c) softmax, s16785–s16867 + +``` +s16786 L44710: mul.ftz.f32 %f2630, %f2602, 0fBFB8AA3B // -log2(e) +s16787 L44711: ex2.approx.ftz.f32 %f2631, %f2630 +s16788 L44712: add.ftz.f32 %f2632, %f2631, 0f3F800000 +s16790 L44713: div.approx.ftz.f32 %f2603, %f2633, %f2632 // 1/(1+2^(-max*log2e)) +s16792 L44719: max.f16x2 %r17840,%r334,%r335 +s16800 L44742: sub.f16x2 %r17849,%r334,%r17863 // x - rowmax +s16803 L44750: mul.ftz.f32 %f2634, %f2604, 0f3FB8AA3B // *log2(e) +s16804 L44751: ex2.approx.ftz.f32 %f2606, %f2634 // 2^(…) +s16859 L44869: add.ftz.f32 %f2651, %f2649, %f2621 // row sum +s16860 L44870: div.approx.ftz.f32 %f2622, %f2633, %f2651 // 1/rowsum +s16863 L44875: mul.f16x2 %r17864,%r17865,%r17878 +``` + +A textbook f32 softmax over each row's 8 values: `max` over the four lane +registers, `y = 2^((x-max)*log2e)` in f32 (`cvt.f32.f16 → mul by 0f3FB8AA3B → +ex2.approx`), accumulate the row sum in f32, invert with `div.approx.ftz.f32 1.0/…`, +round to f16, and multiply the five f16x2 registers +(`%r17864 %r17867 %r17870 %r17873 %r17876`). The `%f2633` dividend is the +`mov.f32 %f2633, 0f3F800000` at s16789 (1.0). Note `s16786` uses `-log2(e)` on +the *max* to build `1/(1+2^(-max·log2e))` (a per-row scale kept in `%rs6232`), +which is applied later to the second row group. + +#### (d) shared-patch gather, s16868–s17143 + +``` +s16871 L44899: mov.u32 %r17960, 8 +s16868 L44896: mad.lo.s32 %r17969, %r347, 80, %r18206 // input_noise + 80*y +s16869 L44897: shl.b32 %r17970, %r345, 3 +s16870 L44898: add.s32 %r17971, %r17969, %r17970 +s16872 L44900: ld.shared.v4.u16 {%rs6327,…%rs6330}, [%r17971+8] +s16873 L44901: ld.shared.v4.u16 {%rs6331,…%rs6334}, [%r17971] +s16874 L44902: mov.b32 %r17880, {%rs6331, %rs6327} // 2x2 transpose pair +s16875 L44904: fma.rn.f16x2 %r17879,%r17880,%r17864,%r17890 // acc += w * p +s16880 L44917: ld.shared.v4.u16 {%rs6341,…}, [%r17971+80] +s16881 L44918: ld.shared.v4.u16 {%rs6348,…}, [%r17971+16] +s16888 L44934: ld.shared.v4.u16 {%rs6355,…}, [%r17971+96] +s16889 L44935: ld.shared.v4.u16 {%rs6362,…}, [%r17971+88] +s16896 L44951: ld.shared.v4.u16 {…}, [%r17971+168] +s16897 L44952: ld.shared.v4.u16 {…}, [%r17971+160] +s16910 L44983: ld.shared.v4.u16 {…}, [%r17971+176] +``` + +18 `ld.shared.v4.u16` at `+0 +8 +16 | +80 +88 +96 | +160 +168 | +176`, i.e. a +2×2 (plus one extra column) stencil of the shared array `input_noise` +(`_ZZ33cuda_dldn_engine_swin_enc0_kernel35DldnEngineFusedSwinEnc0ParamsStructE11input_noise`), +which is filled in the prologue (s1457–s1547) as +`st.shared.v4.u16 [input_noise + y*80 + x*8], {f16c0, f16c1, f16c2, 0}` — a +10×10 grid of `f16x2` triples (three channels + a zero pad), 800 bytes. + +The 2×2 blocks are multiplied by the five softmax registers with +`fma.rn.f16x2`, accumulated into `%r17879 %r17883 %r17887 %r17891…` (a 2×2 +accumulator per row group), then the accumulator halves are summed with +`add.f16` (`s17135–s17137`) and one more shared value is folded in with +`fma.rn.f16` (`s17140–s17142`). + +#### (e) sigmoid, difference, scale, cross-lane sum, s17143–s17200 + +``` +s17145 L45494: mul.ftz.f32 %f2708, %f2679, 0fBFB8AA3B +s17146 L45495: ex2.approx.ftz.f32 %f2709, %f2708 +s17148 L45497: div.approx.ftz.f32 %f2680, %f2689, %f2710 // sigmoid(acc) +s17156 L45515: mul.f16 %rs6445,%rs6394,%rs6429 +s17160 L45530: mov.f32 %f2685, 0f3E800000 // 0.25 +s17162 L45536: sub.f16 %rs6454,%rs6429,%rs6445 // acc - sigmoid term +s17167 L45550: mul.f16x2 %r18080,%r18081,%r18082 // * 0.25 +s17175 L45568: shfl.sync.down.b32 %r18084,%r18080,%r18105,%r18087,%r18115 +s17176 L45574: add.f16x2 %r18089,%r18080,%r18084 +s17191 L45613: add.f16 %rs6472,%rs6466,%rs6471 +s17200 L45637: add.f16 %rs6478,%rs6472,%rs6477 +``` + +`sigmoid(v) = 1/(1 + 2^(-log2e·v))`, then three `acc − sigmoid(acc)` differences +scaled by `0.25`, then a two-step cross-lane sum: `shfl.sync.down` with the +delta operand `%r18105 = 1` (s17175) then `%r18113 = 8` (s17181), each followed +by an `add.f16x2`; the same two steps repeat on the scalar path (s17188 delta 1, +s17197 delta 8, `add.f16` at s17191 and s17200). The group/width operand is 31 +in all four, so this is a partial (not five-step) warp reduction. + +#### (f) surface stores, s17201–s17222 + +``` +s17201 L45640: ld.param.u64 %rd362, [%rd371+120] // surface B +s17202 L45641: ld.param.u64 %rd365, [%rd371+128] // surface half +s17204 L45644: sust.b.2d.v4.b16.zero [%rd360, {%r18119,%r354}], {%rs6454,%rs6457,%rs6460,%rs6549} +s17205 L45647: sust.b.2d.v4.b16.zero [%rd362, {%r18119,%r354}], {%rs6445,%rs6448,%rs6451,%rs6550} +s17210 L45653: @%p477 bra $L__BB1_310 // gated on (%r355&1)==0 +s17220 L45665: sust.b.2d.v4.b16.zero [%rd365, {%r18134,%r18135}], {%rs6551,%rs6552,%rs6478,%rs6554} +s17222 L45669: ret +``` + +Three 4-channel b16 surface writes (params +112, +120, +128); the third is taken +only by even `%r355 = %r315|%r354` lanes and stores `0` in its fourth channel. + +**Inputs:** the eighteen returned values, `W` (+54016/54528), `param+0/+112/+120/+128`, +the shared `input_noise` array, constants `0fBFB8AA3B`, `0f3FB8AA3B`, +`0f3F800000`, `0f3E800000`. +**Outputs:** none (the kernel returns). + +--- + +## 4. The plane-arena writes (param block +48) + +`S = cvta.to.global.u64(%rd276)` with `%rd276 = ld.param.u64 [%rd368+48]` +(s16052–s16053) is the **only** occurrence of `param_0+48` in the entry: I +grep'ed every `ld.param` and this offset is read once. + +There are exactly **two** store groups in the whole entry (24 `st.global.*` in +the file, all after line 43628): + +**(i) E20, 16 × `st.global.u32 [%rd37 + 4*idx], v` — s16078…s16325** (see §3/E20 +for the full table). In one line per store: + +``` +idx = (8*ex)*y + 8*x + d, guard 0 <= y < ey and 0 <= x < ex and laneid <= 255 +store1 (s16078): v = %r262, y = %r6 + (laneid>>5), x = %r1 + ((laneid>>2)&7), d = t +store2 (s16087): v = %r263, same d = t|4 +store3 (s16113): v = %r264, y = %r6 + ((g+8)>>3), x = %r1 + ((g+8)&7), d = t +store4 (s16121): v = %r265, same d = t|4 +store5 (s16147): v = %r266, y = %r6 + ((g+16)>>3), x = %r1 + ((g+16)&7), d = t +store6 (s16155): v = %r267, same d = t|4 +store7 (s16181): v = %r268, y = %r6 + ((g+24)>>3), x = %r1 + ((g+24)&7), d = t +store8 (s16189): v = %r269, same d = t|4 +store9 (s16215): v = %r270, y = %r6 + ((g+32)>>3), x = %r1 + ((g+32)&7), d = t +store10 (s16223): v = %r271, same d = t|4 +store11 (s16249): v = %r272, y = %r6 + ((g+40)>>3), x = %r1 + ((g+40)&7), d = t +store12 (s16257): v = %r273, same d = t|4 +store13 (s16283): v = %r274, y = %r6 + ((g+48)>>3), x = %r1 + ((g+48)&7), d = t +store14 (s16291): v = %r275, same d = t|4 +store15 (s16317): v = %r276, y = %r6 + ((g+56)>>3), x = %r1 + ((g+56)&7), d = t +store16 (s16325): v = %r277, same d = t|4 +where g = laneid>>2, t = laneid&3, ex = %r364, ey = %r365, + %r1 = x origin (s6), %r6 = y origin (s16) +``` + +**(ii) E21, 8 stores to `param+56`, not to the arena** — s16513 (`v2.u16` of +`%rs6215/%rs6216`), s16522, s16549, s16557, s16566, s16574, s16583 (`u32` of +`%r305…%r310`), s16591 (`v2.u16` of `%rs6229/%rs6230`). See §3/E21 for the +indices. + +**What is written:** phase 20's requantised 64×32 output — 16 b32 per lane, one +per store — i.e. 4 bytes × 32 lanes × 16 stores = 2048 bytes per block (4096 +e4m3 elements' worth is not what lands in memory; only 16 of phase 20's 32 D +registers per lane are scattered). + +**What reads it back:** nothing inside this kernel. `param_0+48` is never the +base of an `ld.*`; P5 and P10 take their score bias from the *weight image* +(E9's 24 loads at `W+23744+512*i`, and phase 4's epilogue's 24 loads at +`W+8384+512*i`), and P5/P10 take their `B` operand from registers (phases 3/9 +D → e4m3 packs). See §6. + +## 5. The eight shfl reductions of the merge + +The brief's "eight shfl reductions" are the **eight `shfl.sync.down/up` +pairs of E20(c), s16338–s16368** (statement range s16327–s16369 including the +setup). Each pair uses the same delta operand `%r17576 = 4` (the PTX `b` +operand), with the group/width operand `c` = 31 (`.down`) or 0 (`.up`), and +`laneid & 4` as the selection predicate, so each of the eight 32-bit payloads +(`%r262…%r277`) is re-paired between lanes 0-3 and 4-7 of every `laneid&7` +group before it becomes phase 21's A operand. + +(There is a *second*, unrelated cross-lane reduction in E22: the four +`shfl.sync.idx` per row group at s16639–s16651 / s16680–s16683 / s16714–s16726 / +s16755–s16758 that implement the row maximum, plus the `shfl.sync.down` pair +after the sigmoid at s17175/s17181 and its scalar copy at s17188/s17197.) + +## 6. Uncharacterised + +**U1. "The plane-arena writes at stmts 15053–15198".** In this file, with the +`rr_layer_spec.py` numbering: + +* `s15053`–`s15198` lie **inside phase 17's epilogue** (s14692–s15291). They + are the per-output-channel activation coefficient materialisation + (`cvt.rn.f16.f32 %rs, %f2601` / `neg` / `max` / `min` / `abs` / `mul` / `sub` + / `mul` / `add` / `mul`) and contain **no store of any kind** — the entry has + zero `st.*` between line 1450 and line 43628. +* The only writes to the plane arena are (i) and (ii) of §4, at s16078–s16325 + and s16513–s16591. +* No statement reads `param_0+48`, so nothing written there can be read back by + P5 or P10 *within this launch*. + +I could not reconcile 15053–15198 with this corpus file. The two other +landmarks supplied with that range also disagree with it: `%r17597` (the +`ld.param.v2.u32` of `param+0`) is **s16473 / L44316**, and `%r18203` (`%tid.x`) +is **s16595 / L44456**, not 15448 and 15570. *Missing:* the statement numbering +that produced 15053/15198/15448/15570 — most likely a different linearisation +(every `;`-terminated physical line of the whole file gives 14946 for +L44316 and 15375 for L43628; entry-only gives 14567 and 19913 for the +non-`;` variant, neither matches). Give me that numbering (or the tool) and the +range will map directly. + +**U2. The identity of the 12288-byte score bias.** Both score phases add a +12288-byte f16 table as their GEMM C operand (P5: `W+8384…W+20672`, P10: +`W+23744…W+36032`), indexed as §3/E9 describes. Whether it is a relative +position bias, a learned score bias, or a per-lane constant cannot be decided +from the PTX: it is an opaque blob in a permuted weight image. *Missing:* the +weight image's layout description (the `_prep` permutation) or the parameter +names from the model file. + +**U3. The identity of the per-column tables.** `W+37056/37072/37088/37104` +(E6), `W+37120/37136/37152/37168` (E12, used as the norm gain), and +`W+39296/39312/39328/39344` (E13) are all read with the same +`W + ((laneid<<2)&12) + off` pattern and are 8 f16 per lane (32 columns). Their +role is *computable* (E6: added to the residual before phase 7; E12: multiplies +the inverse std; E13: added after the activation) but their *names* are not. +The GEMM biases at `+38208/40384/42496/44608/53888/54528` are the same case. + +**U4. E21's index bases.** `%r325` (s16542) and `%r328` (s16559) are both +`%r321 + %r316`, so the stores at s16549/s16557 and s16566/s16574 target the +same two indices in program order — the later store wins. I could not tell from +the PTX whether `%r316`'s value or the `g+8` recomputation in the second block +is meant to separate them (it looks like the source of a dropped output, but it +may equally be a degenerate case that the guard prevents). *Missing:* either a +run of the kernel with a plane-arena/surface dump, or the corresponding +high-level code. + +**U5. The geometry of P6 (M/N/K).** E5 produces 12 A fragments and 12 B +fragments for phase 6; the A side is the 96 probabilities and the B side the 48 +transposed-V registers, so phase 6 is `64×32 = (64×96)·(96×32)` with three +k-steps of 32 (verified from the mma chain at s7826–s7873: `D ← A·B + D_prev` +for exactly three steps). `rr_layer_spec.py`'s phase table still prints +M=192 N=96 K=96 for that phase; the *epilogue* contract above does not depend on +resolving it. + +**U6. The logical meaning of E22's final expression.** The tail computes +`out = (acc − sigmoid(acc)) * 0.25` on three channels gathered from the shared +input patch. The PTX gives the arithmetic exactly (§3/E22(e)) but not what +model term it corresponds to. *Missing:* the high-level source (a `shrink` / +`gate` / `residual` term) or a reference implementation to compare against. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| P5 epilogue: row max / exp / row sum / reciprocal / position bias | §3-E5(a)–(e); **no row max and no bias add are present — see §6 U1/U2** | +| P5: the position bias | added as the GEMM **C operand** (s3764–s3814, `W+8384+512*i`), *not* in the epilogue | +| P6: `P*V`, the transposes | §3-E5(f) (48 `movmatrix`, s7562–s7609) + E6 | +| second window P8–P11 | §3-E8, E9, E10, E11 | +| MLP P12–P20, the norm | §3-E12 | +| fc1/gelu/fc2 triples | §3-E13…E19 (activation is the clamped cubic of E13, not GELU) | +| gains/biases at 38208/40384/42496/44608/53888 | §1.1, §3-E12/E13/E14/E16/E18/E20 | +| P21/P22 merge + eight shfl | §5, §3-E20(c), E21 | +| plane-arena writes, exact value and index | §4 | +| final epilogue after L44528 and the 18 values | §3-E22 | \ No newline at end of file diff --git a/kernels/rr/rrswin_enc1.hip b/kernels/rr/rrswin_enc1.hip new file mode 100644 index 0000000..169781a --- /dev/null +++ b/kernels/rr/rrswin_enc1.hip @@ -0,0 +1,737 @@ +// Native replacement for the Ray Reconstruction denoiser's second Swin encoder, +// cuda_dldn_engine_swin_enc1_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the recipe (kernels/rr/swin_enc1_recipe.py) cuts statements s8270-s26139 +// out of the entry and calls this body instead, handing over the prologue's two +// staged A operand sets, the zero register phase 1 uses as its C seed and the +// dequantised input tile E6 needs for phase 7's residual. The window implemented +// here is phases 1-7: the four 96x32 projections, the 64x96 score, P*V and the +// 64x64 output projection. Phase 32's accumulators are still placeholders, so the +// epilogue's surface output differs from the translated kernel; every implemented +// stage is bit-exact against the debug oracle (see "Ground truth" below). +// +// The kernel is one warp per 8x8 token patch: grid (81, 47, 1), block (32, 1, 1) +// with one wave per block (the prologue also handles tid.y > 0, for waves > 1, but +// the shipped manifest launches one), parameter block 144 bytes. The PTX this +// file replaces is kernels/extracted/rr/0014-PREPASS_ENTRYPOINT_NAME.ptx. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinEnc1Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinEnc1Params) == 144, "parameter block"); + +enum : int +{ + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // plane arena pointer, as make_ptx.py's debug splice reads it + kExtents = 0, // ex, ey (v2.u32) +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// The implemented phases, as byte offsets into arg040 (from the PTX's own loads; +// K=32, 512 bytes per group of 16 columns): +// P1 weights 128 P2 weights 2176 P3 weights 1152 P4 weights 3200 +// P5 score bias 4224..16512 (24 tiles of 512) +// P6 none (P*V; B is the movmatrix transpose of phase 4's D) +// P7 weights 16512..18560, per-column table 36992..37120 (8 words of 16 bytes) + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (VERIFIED on all 1024 (n, k) pairs of a tile for enc0; the B operand layout is +// the hardware's, so the same inversion applies here.) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +DEVF float bfly1(float v) +{ + return __builtin_bit_cast(float, bfly1_bits(__builtin_bit_cast(uint32_t, v))); +} + +DEVF float bfly2(float v) +{ + return __builtin_bit_cast(float, bfly2_bits(__builtin_bit_cast(uint32_t, v))); +} + +// the low/high f16 of a packed pair (columns 2t / 2t+1) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +// add.f16x2 on a packed pair (the PTX's reduction and requantisation steps) +DEVF uint32_t pair_add(uint32_t a, uint32_t b) +{ + return __builtin_bit_cast(uint32_t, __builtin_bit_cast(hv2, a) + __builtin_bit_cast(hv2, b)); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// ZLUDA's relu_keep_nan_halves: a negative (or -0) half becomes +0, NaN is kept. +DEVF uint32_t relu_pair(uint32_t p) +{ + if ((p & 0x8000u) != 0 && (p & 0x7fffu) <= 0x7c00u) { + p &= 0xffff0000u; + } + if ((p & 0x80000000u) != 0 && ((p >> 16) & 0x7fffu) <= 0x7c00u) { + p &= 0x0000ffffu; + } + return p; +} + +// --------------------------------------------------------------------------- +// One GEMM: `nmi` m-tiles of 16 rows x `nti` n-tiles of 8 columns, K=32, f16 out. +// +// A lane's A registers hold, for each m-tile and each of its two rows, the eight +// e4m3 values of k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3) and of k + 8; the +// four lanes that differ in t hold the four disjoint eighths of the 32 k's, so two +// butterfly steps broadcast the other three eighths in. The B operand is read from +// the weight image (waddr) for the lane's own two columns of each n-tile. The dot +// product runs in f32 and is rounded to f16 once, which is what the translated mma +// does: e4m3 x e4m3 products are exact and 32 of them sum exactly in f32. +// +// The C operand is the 32-bit seed the PTX's mma adds (one packed f16 pair per D +// register, indexed [m-tile][row half][n-tile] as `cmat`) or a constant (`fixed`). +// d is [m-tile][row half][n-tile], each entry the packed f16 pair 2t, 2t+1. +DEVF void gemm(const uint32_t* as, const uint8_t* w, int base, uint32_t fixed, + const uint32_t* cmat, int nmi, int nti, int t, uint32_t d[6][2][8]) +{ + for (int nt = 0; nt < nti; ++nt) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + for (int mi = 0; mi < nmi; ++mi) { + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + uint32_t p[4]; + p[0] = as[4 * mi + 2 * reg + row]; + p[1] = bfly1_bits(p[0]); + p[2] = bfly2_bits(p[0]); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + const uint32_t seed = (cmat != nullptr) ? cmat[(4 * mi + row) * nti + nt] : fixed; + d[mi][row][nt] = pair_of((half_t)(acc[row][0] + h2f(seed)), + (half_t)(acc[row][1] + h2f(seed >> 16))); + } + } + } +} + +// --------------------------------------------------------------------------- +// the f16 the PTX's literals carry: 0x2466, 0xb873, 0x3873, 0x3b6b, 0x3d80 +DEVF half_t hf16(uint16_t bits) +{ + return __builtin_bit_cast(half_t, bits); +} + +DEVF hv2 hv2_of(uint32_t p) +{ + return __builtin_bit_cast(hv2, p); +} + +DEVF uint32_t u32_of(hv2 v) +{ + return __builtin_bit_cast(uint32_t, v); +} + +// ZLUDA's own rcp.approx.ftz.f32 helper: calling it is what makes the reciprocal +// bit-exact. +extern "C" __attribute__((device)) float __zluda_ptx_impl_rcp_approx_f32(float); + +// the e4m3 code of one f16 (cvt.rn.satfinite.e4m3x2.f16x2 of a pair of equal halves) +DEVF uint32_t q8(half_t v) +{ + return e4m3x2(pair_of(v, v)); +} + +// the f16 at (row, col) of a 96x32 (or 64x32) block of packed pairs, +// col = 8*n-tile + 2t + c +DEVF half_t dcell(const uint32_t d[6][2][8], int row, int col) +{ + const uint32_t p = d[row >> 4][(row >> 3) & 1][col >> 3]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +// the lane's two e4m3-packed words for row r: word 0 packs n-tiles 0 and 2, word 1 +// packs tiles 1 and 3 (the mma's own k order) +DEVF void row_words(const uint32_t d[6][2][8], int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// out[i][m]: word i as lane t^m holds it, which is what the mma pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + +// word i at butterfly index m (0..3), without the dynamic index into the pair +DEVF uint32_t word_at(const uint32_t out[2][4], int i, int m) +{ + return m == 0 ? out[i][0] : (m == 1 ? out[i][1] : (m == 2 ? out[i][2] : out[i][3])); +} + +// the 32-term dot product of two packed operand word pairs, in the mma's own k order +DEVF float dot32(const uint32_t a[2][4], const uint32_t b[2][4]) +{ + float acc = 0.0f; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + acc += e4m3_to_f32((a[i][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((b[i][m] >> (8 * j)) & 0xffu); + } + } + } + return acc; +} + +// E5(a), one element: the scale, the clamp, the two clamped-cubic fma pairs and the +// trick that moves the mantissa into the exponent field ((u << 5) & 0x7FE07FE0). +DEVF uint32_t expval_pair(uint32_t score) +{ + hv2 m = hv2_of(score) * __builtin_bit_cast(hv2, pair_of(hf16(0x2466), hf16(0x2466))); + m = __builtin_elementwise_max(m, __builtin_bit_cast(hv2, pair_of(hf16(0xb873), hf16(0xb873)))); + m = __builtin_elementwise_min(m, __builtin_bit_cast(hv2, pair_of(hf16(0x3873), hf16(0x3873)))); + const hv2 t = __builtin_elementwise_fma(m, -m, + __builtin_bit_cast(hv2, pair_of(hf16(0x3b6b), hf16(0x3b6b)))); + const uint32_t u = u32_of(__builtin_elementwise_fma(m, t, + __builtin_bit_cast(hv2, pair_of(hf16(0x3d80), hf16(0x3d80))))); + return (u << 5) & 0x7fe07fe0u; +} + +// E5(a)-(e), one row: the twelve exponent pairs, the in-lane sum tree, the two +// butterfly steps that finish the row's 96 columns, the two halves' add, the +// reciprocal and the twelve products. +DEVF void row_probs(const uint32_t d5[4][2][12], int mi, int rh, uint32_t prob[12]) +{ + hv2 ev[6], eo[6]; +#pragma unroll + for (int i = 0; i < 6; ++i) { + ev[i] = hv2_of(expval_pair(d5[mi][rh][2 * i])); + eo[i] = hv2_of(expval_pair(d5[mi][rh][2 * i + 1])); + } + const hv2 even = ((ev[0] + ev[1]) + (ev[2] + ev[3])) + (ev[4] + ev[5]); + const hv2 odd = ((eo[0] + eo[1]) + (eo[2] + eo[3])) + (eo[4] + eo[5]); + hv2 s = even + odd; + s = s + hv2_of(bfly1_bits(u32_of(s))); + s = s + hv2_of(bfly2_bits(u32_of(s))); + const uint32_t p = u32_of(s); + // the PTX broadcasts the f16 sum of the two halves (add.f16) and takes cvt.f32.f16 + // of it: the value, not its bits + const half_t r = (half_t)__zluda_ptx_impl_rcp_approx_f32((float)(half_lo(p) + half_hi(p))); + const uint32_t rcp = pair_of(r, r); +#pragma unroll + for (int i = 0; i < 6; ++i) { + prob[2 * i] = u32_of(ev[i] * hv2_of(rcp)); + prob[2 * i + 1] = u32_of(eo[i] * hv2_of(rcp)); + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/tex/make_ptx.py's debug recipe: +// with D4R_RRSWIN_DEBUG= the NVIDIA body keeps every mma and stores that +// stage's registers into the plane arena (per block 0..63, slot by register count, +// 4 bytes per lane), and the launch dump then holds the translated values. Built +// with -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this +// body stores the same registers of its own phase n in the same order, so the two +// dumps compare byte for byte. +// +// The offset into the arena is D4R_RRSWIN_DEBUG_BASE on the oracle side (read by +// make_ptx.py's swin_debug_block) and D4R_RRSWIN_DEBUG_BASE_NUM here. Two measured +// facts fix its value for enc1: +// +// * enc1's param_0+48 is not dumped as arg048. The launch manifest puts it at byte +// 45,219,840 of the 65,945,600-byte block the bridge dumps as arg008 +// (`pointer 8 0 30146560`, `pointer 48 0 45219840`, `pointer 56 0 60293120`), so +// the bridge skips arg048 as a duplicate allocation base. The payload therefore +// lives in the arg008 dump at 45,219,840 + base, and enc0's default of 46,000,000 +// would fall 25 MB past the end of the block. +// * enc1's own 44 `st.global` fill that block's whole 20,725,760-byte tail (measured +// on an isolated launch: the translated kernel changes every byte of it), so a base +// inside the tail is overwritten by the kernel's own later stores and the comparison +// silently compares ambient memory. The last byte E31 reaches is arena + 16,957,436, +// and the block ends at arena + 20,725,760. +// +// 17,006,592 is a multiple of the largest slot (16,384), clears E31, and leaves room +// for all 64 slots (1,048,576 bytes) inside the block. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif +#ifndef D4R_RRSWIN_DEBUG_BASE_NUM +#define D4R_RRSWIN_DEBUG_BASE_NUM 17006592 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + // make_ptx.py's swin_debug_block forms the block index as ctaid.x + 161*ctaid.y + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 161u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot: 32 lanes x n x 4 bytes, at least 8192, rounded up to a power of two + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + (uint64_t)D4R_RRSWIN_DEBUG_BASE_NUM + + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// stage registers in the oracle's order: m-tile major, n-tile minor, each as the +// (row g, row g+8) pair the mma writes. +DEVF void stage_regs(const uint32_t d[6][2][8], int nmi, int nti, uint32_t regs[96]) +{ + int i = 0; + for (int mi = 0; mi < nmi; ++mi) { + for (int nt = 0; nt < nti; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// The native body. +// +// Live-ins (recipes's order): AS1[24] (phases 1/2/8/9), AS2[24] (phases 3/4/10/11), +// the phase-1 C seed (the constant zero register), RES[64] (the dequantised input +// tile in (m-tile, n-tile, row half) order), the weight image, the parameter block +// and the address of the LDS scratch the accumulators go back through. +#define AS(i) a##i +extern "C" __attribute__((device)) void d4r_swin_enc1( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t a24, uint32_t a25, uint32_t a26, uint32_t a27, + uint32_t a28, uint32_t a29, uint32_t a30, uint32_t a31, uint32_t a32, uint32_t a33, uint32_t a34, + uint32_t a35, uint32_t a36, uint32_t a37, uint32_t a38, uint32_t a39, uint32_t a40, uint32_t a41, + uint32_t a42, uint32_t a43, uint32_t a44, uint32_t a45, uint32_t a46, uint32_t a47, + uint32_t cseed, + uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3, uint32_t r4, uint32_t r5, uint32_t r6, + uint32_t r7, uint32_t r8, uint32_t r9, uint32_t r10, uint32_t r11, uint32_t r12, uint32_t r13, + uint32_t r14, uint32_t r15, uint32_t r16, uint32_t r17, uint32_t r18, uint32_t r19, uint32_t r20, + uint32_t r21, uint32_t r22, uint32_t r23, uint32_t r24, uint32_t r25, uint32_t r26, uint32_t r27, + uint32_t r28, uint32_t r29, uint32_t r30, uint32_t r31, uint32_t r32, uint32_t r33, uint32_t r34, + uint32_t r35, uint32_t r36, uint32_t r37, uint32_t r38, uint32_t r39, uint32_t r40, uint32_t r41, + uint32_t r42, uint32_t r43, uint32_t r44, uint32_t r45, uint32_t r46, uint32_t r47, uint32_t r48, + uint32_t r49, uint32_t r50, uint32_t r51, uint32_t r52, uint32_t r53, uint32_t r54, uint32_t r55, + uint32_t r56, uint32_t r57, uint32_t r58, uint32_t r59, uint32_t r60, uint32_t r61, uint32_t r62, + uint32_t r63, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[24] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23}; + const uint32_t as2[24] = {a24, a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, + a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, a47}; + const uint32_t res[64] = {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, + r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, + r30, r31, r32, r33, r34, r35, r36, r37, r38, r39, r40, r41, r42, r43, + r44, r45, r46, r47, r48, r49, r50, r51, r52, r53, r54, r55, r56, r57, + r58, r59, r60, r61, r62, r63}; +#if D4R_RRSWIN_DEBUG_STAGE + // The oracle's payload store is spliced in after E31's last arena write (see + // swin_enc1_debug_stages.LINE), because enc1 fills its whole plane-arena tail, so a + // store placed beside its own phase is overwritten before the dump reads it back. + // This side therefore fills `cap` where each stage's registers are live and hands + // the whole thing to debug_store() once, at the end of the body -- after this + // body's own E30/E31 stores, which is the same program point. + uint32_t cap[128]; + int capn = 0; +#if D4R_RRSWIN_DEBUG_STAGE == 10 + // the oracle's stage a: the two staged A operand sets, the phase-1 C seed and + // the three shfl constants the PTX carries (1, 2, -1) + for (int i = 0; i < 24; ++i) { + cap[i] = as1[i]; + cap[24 + i] = as2[i]; + } + cap[48] = cseed; + cap[49] = 1u; + cap[50] = 2u; + cap[51] = 0xffffffffu; + capn = 52; +#endif +#endif + (void)cseed; // phase 1's C operand is this register's value, the constant zero + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + const int g = (int)(lane_id() >> 2); // ... and of its sixteen rows + + lds_u32* const slot = (lds_u32*)(uintptr_t)scratch; // the phase 5/6 exchange + + // ---- the four 96x32 projections ---------------------------------------- + // Phases 1 and 2 have C = 0 (the PTX hands in the zero register); phases 3 and + // 4 add phase 1's / phase 2's D back in as their C seed. + uint32_t d1[6][2][8]; + uint32_t d2[6][2][8]; + gemm(as1, w, 128, 0u, nullptr, 6, 4, t, d1); + gemm(as1, w, 2176, 0u, nullptr, 6, 4, t, d2); +#if D4R_RRSWIN_DEBUG_STAGE == 1 + stage_regs(d1, 6, 4, cap); + capn = 48; +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 2 + stage_regs(d2, 6, 4, cap); + capn = 48; +#endif + uint32_t d3[6][2][8]; + uint32_t d4[6][2][8]; + { + uint32_t c1[96], c2[96]; + for (int mi = 0; mi < 6; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + for (int rh = 0; rh < 2; ++rh) { + c1[(4 * mi + rh) * 4 + nt] = d1[mi][rh][nt]; + c2[(4 * mi + rh) * 4 + nt] = d2[mi][rh][nt]; + } + } + } + gemm(as2, w, 1152, 0u, c1, 6, 4, t, d3); + gemm(as2, w, 3200, 0u, c2, 6, 4, t, d4); + } +#if D4R_RRSWIN_DEBUG_STAGE == 3 + stage_regs(d3, 6, 4, cap); + capn = 48; +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 4 + stage_regs(d4, 6, 4, cap); + capn = 48; +#endif + + // ---- phase 5, the score: Q.K^T over the patch and its halo --------------- + // A and B are both phase 3's accumulators. The lane's rows 16*mi + g + 8*rh are the + // queries (the 8x8 token patch) and its rows 16*(nb>>1) + 8*(nb&1) + g the keys (the + // patch plus a 32-row halo): the PTX builds n-tile nb's B fragment from phase 3's + // m-tile nb>>1 and row half nb&1, whose two words are the k-groups {0, 2} and {1, 3} + // of the 32 columns. row_words() packs a row that way. + // + // A lane holds one row group of the queries and one of the keys, so it can only dot + // them with each other; every lane therefore publishes its two key words per n-tile + // (12 x 2 x 32 lanes = 768 words = 3072 bytes, the whole scratch) and then forms the + // dots its own D registers hold. + // + // The C operand is the 64x96 f16 score bias at weight bytes 4224..16512: 24 tiles of + // 512 bytes, the seed of (m-tile, n-tile, row half) at byte + // 4224 + 512*(mi + 4*(nb>>1)) + 16*lane + 4*(2*(nb&1) + row). + uint32_t d5[4][2][12]; + { +#pragma unroll + for (int nb = 0; nb < 12; ++nb) { + uint32_t wd[2]; + row_words(d3, 16 * (nb >> 1) + 8 * (nb & 1) + g, wd); + slot[64 * nb + lane_id()] = wd[0]; + slot[64 * nb + 32 + lane_id()] = wd[1]; + } + __builtin_amdgcn_wave_barrier(); +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int row = 0; row < 2; ++row) { + uint32_t aw[2], a[2][4]; + row_words(d3, 16 * mi + g + 8 * row, aw); + bfly2x4(aw, a); +#pragma unroll + for (int nb = 0; nb < 12; ++nb) { + float s[2]; +#pragma unroll + for (int c = 0; c < 2; ++c) { + uint32_t kb[2][4]; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { + kb[i][m] = slot[64 * nb + 32 * i + 4 * (2 * t + c) + (t ^ m)]; + } + } + s[c] = dot32(a, kb); + } + const uint32_t bias = *(const uint32_t*)(w + 4224 + 512 * (mi + 4 * (nb >> 1)) + + 16 * lane_id() + 4 * (2 * (nb & 1) + row)); + d5[mi][row][nb] = pair_of((half_t)(s[0] + h2f(bias)), + (half_t)(s[1] + h2f(bias >> 16))); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 8 + // the oracle's stage p5o: the 96 C words (the score bias, tile-major: 24 tiles + // of four words per lane) and the 24 B words (the two e4m3 key words of each of + // the twelve n-tiles) exactly as the mma reads them. +#pragma unroll + for (int ti = 0; ti < 24; ++ti) { + for (int wd = 0; wd < 4; ++wd) { + cap[4 * ti + wd] = *(const uint32_t*)(w + 4224 + 512 * ti + 16 * lane_id() + 4 * wd); + } + } +#pragma unroll + for (int nb = 0; nb < 12; ++nb) { + cap[96 + 2 * nb] = slot[64 * nb + lane_id()]; + cap[96 + 2 * nb + 1] = slot[64 * nb + 32 + lane_id()]; + } + capn = 120; +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 5 + { + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nb = 0; nb < 12; ++nb) { + cap[i++] = d5[mi][0][nb]; + cap[i++] = d5[mi][1][nb]; + } + } + capn = 96; + } +#endif + + // ---- E5 and phase 6: the softmax and P.V -------------------------------- + // row_probs() gives the twelve probability pairs of one row; k-step ks packs key + // columns {4ks, 4ks+2} into the fragment's first word and {4ks+1, 4ks+3} into its + // second. The lane's A fragment is its own two rows (16*mi + g and 16*mi + g + 8), + // so the D row it accumulates is its own g; what it lacks is V. The key rows + // 32*ks + kk live in the lanes whose g is kk % 8, and every lane needs all 96 of + // them, so V goes through the scratch as one e4m3 byte per element (96 x 32 = 3072 + // bytes) and each lane then walks the full k range. Each k-step rounds to f16 + // before the next one adds to it, which is why the chain has three separate mma. + uint32_t d6[4][2][8]; + { +#pragma unroll + for (int mi4 = 0; mi4 < 6; ++mi4) { + for (int rh4 = 0; rh4 < 2; ++rh4) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + for (int c = 0; c < 2; ++c) { + const int r = 16 * mi4 + 8 * rh4 + g; + ((lds_u8*)(uintptr_t)scratch)[r * 32 + 8 * nt + 2 * t + c] = + (uint8_t)q8(dcell(d4, r, 8 * nt + 2 * t + c)); + } + } + } + } + } + __builtin_amdgcn_wave_barrier(); + { + const lds_u8* const vs = (const lds_u8*)(uintptr_t)scratch; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int rh = 0; rh < 2; ++rh) { + uint32_t prob[12], aw[3][2]; + row_probs(d5, mi, rh, prob); +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + aw[ks][0] = e4m3x2(prob[4 * ks]) | (e4m3x2(prob[4 * ks + 2]) << 16); + aw[ks][1] = e4m3x2(prob[4 * ks + 1]) | (e4m3x2(prob[4 * ks + 3]) << 16); + } +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + half_t prev0 = hf16(0x0000), prev1 = hf16(0x0000); +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + uint32_t a[2][4]; + bfly2x4(aw[ks], a); + float acc0 = 0.0f, acc1 = 0.0f; +#pragma unroll + for (int kk = 0; kk < 32; ++kk) { + const float pv = e4m3_to_f32( + (word_at(a, (kk >> 3) & 1, t ^ ((kk >> 1) & 3)) + >> (8 * (2 * (kk >> 4) + (kk & 1)))) & 0xffu); + const int r = (32 * ks + kk) * 32 + 8 * nt + 2 * t; + acc0 += pv * e4m3_to_f32(vs[r]); + acc1 += pv * e4m3_to_f32(vs[r + 1]); + } + prev0 = (half_t)(acc0 + (float)prev0); + prev1 = (half_t)(acc1 + (float)prev1); + } + d6[mi][rh][nt] = pair_of(prev0, prev1); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 6 + // the oracle's stage p6: the third (last) k-step of each chain, m-tile major, + // n-tile minor, the (row g, row g+8) pair + { + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + cap[i++] = d6[mi][0][nt]; + cap[i++] = d6[mi][1][nt]; + } + } + capn = 32; + } +#endif + + // ---- E6 and phase 7, the output projection ------------------------------ + // A is phase 6's D packed as before; C is the pipeline's residual + the + // per-column table at weight bytes 36992..37120 (8 words of two f16 per n-tile, + // the lane's own column pair 2t, 2t+1). + uint32_t as7[16]; + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + as7[4 * mi + row] = e4m3x2(d6[mi][row][0]) | (e4m3x2(d6[mi][row][2]) << 16); + as7[4 * mi + 2 + row] = e4m3x2(d6[mi][row][1]) | (e4m3x2(d6[mi][row][3]) << 16); + } + } + uint32_t c7[64]; // [(4*m-tile + row half)][n-tile] + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 8; ++nt) { + const uint32_t tab = *(const uint32_t*)(w + 36992 + 16 * nt + ((lane_id() << 2) & 12)); + for (int row = 0; row < 2; ++row) { + const uint32_t rr = res[(mi * 8 + nt) * 2 + row]; + c7[(4 * mi + row) * 8 + nt] = pair_of( + (half_t)(half_lo(tab) + half_lo(rr)), (half_t)(half_hi(tab) + half_hi(rr))); + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 9 + // the oracle's stage e6: phase 7's 16 A registers and its 64 C seeds + { + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int o = 0; o < 4; ++o) { + cap[i++] = as7[4 * mi + o]; + } + } + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 8; ++nt) { + cap[i++] = c7[(4 * mi + 0) * 8 + nt]; + cap[i++] = c7[(4 * mi + 1) * 8 + nt]; + } + } + capn = 80; + } +#endif + uint32_t d7[6][2][8]; + gemm(as7, w, 16512, 0u, c7, 4, 8, t, d7); +#if D4R_RRSWIN_DEBUG_STAGE == 7 + stage_regs(d7, 4, 8, cap); + capn = 64; +#endif + + // ---- handing the accumulators back -------------------------------------- + // Phase 32's eight mma D pairs are not implemented yet. Until they are, fill the + // sixteen slots with lane-distinct values so the read-back path is observable + // without producing wild magnitudes (the epilogue's surface output changes from + // the known-bad baseline). 64 bytes apart per lane, inside the 8 KiB scratch. + lds_u32* const out = (lds_u32*)(uintptr_t)scratch + 16 * (uint32_t)lane_id(); + for (int i = 0; i < 16; ++i) { + out[i] = (uint32_t)lane_id() + 32u * (uint32_t)i; + } +#if D4R_RRSWIN_DEBUG_STAGE + // the payload goes out here, after every store this body makes: the oracle's store + // is spliced in at the same program point (after E31's last arena write) + debug_store(prm, cap, capn); +#endif +} + +// --------------------------------------------------------------------------- +// Weight image layout of the implemented phases (byte ranges of arg040, from the +// PTX's own ld.weak.global loads; 512 bytes per group of 16 columns, K=32): +// P1 [128,1152) P2 [2176,3200) P3 [1152,2176) P4 [3200,4224) +// P5 bias [4224,16512) (24 tiles of 512, a 64x96 f16 block) +// P6 none (P.V: B is the movmatrix transpose of phase 4's D) +// P7 [16512,18560) column table [36992,37120) +// +// Fragment maps (the hardware's, identical to enc0's, VERIFIED against the debug +// oracle there; g = lane>>2, t = lane&3): +// A reg 0 -> row g, k = 2t + (j&1) + 16*((j>>1)&1) +// A reg 1 -> row g+8, same k +// A reg 2 -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// A reg 3 -> row g+8, same k +// B byte j (j<4) -> n = 16*tt + 8*(b>>3) + g, k = 2t + (j&1) + 16*((j>>1)&1) +// B byte j (j>=4) -> same n, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// C/D reg 0 -> row g, cols t*2, t*2+1 +// C/D reg 1 -> row g+8, cols t*2, t*2+1 diff --git a/kernels/rr/rrswin_enc1_epilogues.md b/kernels/rr/rrswin_enc1_epilogues.md new file mode 100644 index 0000000..cc179c9 --- /dev/null +++ b/kernels/rr/rrswin_enc1_epilogues.md @@ -0,0 +1,1234 @@ +# `cuda_dldn_engine_swin_enc1_kernel` — the epilogues of phases 1…32 + +Companion to `kernels/rr/rr_layer_spec.py enc1`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0014-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc1_kernel`. + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. The phase table (`rr_layer_spec.py enc1`) gives the + ranges; this file names what each one *computes*. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_enc1_kernel_param_0+40]` (s11) and + `cvta.to.global.u64 %rd3, %rd2` (s12). Every `ld.weak.global.ca.v4.u32` in an + epilogue reads `W + 16*laneid + imm`. +* `S` denotes the destination buffer at `param_0+48`: `ld.param.u64 %rd337, + [%rd1+-32]` (s25221) with `%rd1 = param_0+80` (s4). The buffer at + `param_0+56` is `ld.param.u64 [%rd535+-24]` (s25963), same base. +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, + `g = laneid>>2`, `t = laneid&3`. A reg = `reg0 = (row g, k=2t+(j&1)+16*((j>>1)&1))`, + `reg1 = (row g+8, same k)`, `reg2 = (row g, k+8)`, `reg3 = (row g+8, k+8)`. +* Block origins, defined once in the prologue and read by every epilogue: + `%r1 = (ctaid.x<<3) - ext.x` (s3, s7), `%r7 = ((ctaid.y+tid.y)<<3) - ext.y` + (s10, s16, s19), `%r5 = ext.x<<3` (s17), `%r6 = ext.y * %r5` (s18), + `%r465 = ext.x`, `%r466 = ext.y` (s13). Every `add.s32 %rX, %r7, …` is a y + origin and every `add.s32 %rX, %r1, …` an x origin. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, ≥96480 bytes) | `ld.param.u64 %rd2, [param_0+40]` / `cvta.to.global.u64 %rd3, %rd2` | s11 / s12 | +| `S` (destination buffer) | `ld.param.u64 %rd337, [%rd1+-32]` with `%rd1 = param_0+80` | s4, s25221–s25222 | +| `D` (2nd destination buffer) | `ld.param.u64 %rd455, [%rd535+-24]`, `%rd535 = param_0+80` | s25635, s25963–s25964 | +| input tile buffer | `ld.param.u64 %rd12, [param_0+8]` / `cvta.to.global.u64 %rd4, %rd12` | s21 / s22 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r465, %r466}, [param_0+0]` | s13 | +| `%r1`, `%r5`, `%r6`, `%r7` | `sub.s32 %r1, %r460, %r461`; `shl %r5, %r465, 3`; `mul %r6, %r466, %r5`; `sub.s32 %r7, %r468, %r467` | s7, s17, s18, s19 | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, W, %rd` | every load block | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd3, %rd` = `W + ((laneid*4) & 12)` | s12509–s12512 and copies | + +The last line matters: the eight `ld.global.v2.u16` / four `ld.global.u32` loads +in an epilogue read `W + ((laneid<<2)&12) + off`, i.e. **the same 64-byte record +is read by the four lanes with equal `laneid&3`, and the eight loads pick eight +16-byte words inside it.** So those tables are indexed by column, not by row. + +`param_0+80` is used *as a base as well as* a value: `ld.param.v2.u16 {%rs103, +%rs104}, [param_0+80]` (s5) reads two u16 at the offset that `%rd1 = param_0+80` +(s4) points at, and every later param read is relative to `param_0+80`: +`[%rd1+-32]` = +48, `[%rd535+-24]` = +56, `[%rd535+-80]` = +0, +`[%rd539+8]` = +88, `[%rd539+32]` = +112, `[%rd539+40]` = +120, +`[%rd539+48]` = +128. + +### 1.2 Constants that survive between epilogues + +| register | first definition | f32/f64 literal | value used (after the `cvt`) | +|---|---|---|---| +| `%f956` | s8607 `mov.f32 %f956, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 | +| `%fd767` | s8611 `mov.f64 %fd767, 0dBFE1CC0000000000` | −0.55615234375 | f16 `0xB873` = −0.55615234375 | +| `%fd769` | s8616 `mov.f64 %fd769, 0d3FE1CC0000000000` | +0.55615234375 | f16 `0x3873` = +0.55615234375 | +| `%f958` | s8622 `mov.f32 %f958, 0f3F6D6000` | 0.92724609375 | f16 `0x3B6B` = 0.92724609375 | +| `%f960` | s8627 `mov.f32 %f960, 0f3FB00000` | 1.375 | f16 `0x3D80` = 1.375 | +| `%f1981` | s18793 `mov.f32 %f1981, 0f3ED306EB` | 0.4121621549129486 | f16 `0x3698` = 0.412109375 | +| `%f1982` | s18796 `mov.f32 %f1982, 0f3DA60DD6` | 0.0810810774564743 | f16 `0x2D30` = 0.0810546875 | +| `%f1983` | s18799 `mov.f32 %f1983, 0f3F000000` | 0.5 | f16 `0x3800` = 0.5 | +| `%f1984` | s18802 `mov.f32 %f1984, 0f40000000` | 2.0 | f16 `0x4000` = 2.0 | +| `%fd770` | s6471 `mov.f64 %fd770, 0d3F20000000000000` | 2⁻¹³ | f16 `0x0800` = 0.0001220703125 | + +Also live across the region (defined in the prologue, read by every warp +reduction): `%r16376` = `mov.u32 %r16376, 1` (s5731), `%r16385` = +`mov.u32 %r16385, 2` (s6296), `%r16387` = `mov.u32 %r16387, -1` (s6289) — +the three operands of every `shfl.sync.bfly.b32`. + +`%f1981…%f1984` are defined **inside E15** (phase 15's epilogue) and reused by +the epilogues of phases 17, 19, 21, 23, 25, 27 and 29 — those epilogues contain +no `mov.f32` at all (E17 at s19785 has none; E19's histogram at s20569 likewise). +`%f956/%fd767/%fd769/%f958/%f960` are defined inside E5 and reused by E10/E12. + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (round each step through f16), except in + E32 where the f32 softmax is kept in f32 until its final `cvt.rn.f16.f32`. + +## 2. Summary + +### 2.1 Phase table with the M/N/K arithmetic checked + +The `rr_layer_spec.py` phase table's `M`,`N`,`K` columns come from counting +distinct A and B fragments, which is unambiguous only for a one-k32-step phase. +For every phase I followed the `D → C` chains of the phase's own `mma` run and +counted `k_steps`, `m_tiles = distinctA/k_steps`, `n_tiles = distinctB/k_steps`: + +| # | stmts | mma | k_steps | M | N | K | `M/16·N/8·K/32 == mma` | spec row | +|---|---|---|---|---|---|---|---|---| +| 1 | s8270–s8293 | 24 | 1 | 96 | 32 | 32 | 24 == 24 OK | 96/32/32 OK | +| 2 | s8301–s8324 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 3 | s8332–s8355 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 4 | s8363–s8386 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 5 | s8558–s8605 | 48 | 1 | 64 | 96 | 32 | 48 OK | OK | +| 6 | s12449–s12496 | 48 | **3** | **64** | **32** | **96** | 4·4·3 = 48 OK | spec says 192/96/96 → **wrong** | +| 7 | s12761–s12792 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 8 | s12800–s12823 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 9 | s12831–s12854 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 10 | s12862–s12885 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 11 | s12893–s12916 | 24 | 1 | 96 | 32 | 32 | 24 OK | OK | +| 12 | s13088–s13135 | 48 | 1 | 64 | 96 | 32 | 48 OK | OK | +| 13 | s16974–s17021 | 48 | **3** | **64** | **32** | **96** | 48 OK | spec says 192/96/96 → **wrong** | +| 14 | s17081–s17112 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 15 | s18760–s18791 | 32 | **2** | **64** | **32** | **64** | 4·4·2 = 32 OK | spec says 128/64/64 → **wrong** | +| 16 | s19605–s19636 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 17 | s19753–s19784 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 18 | s20389–s20420 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 19 | s20537–s20568 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 20 | s21173–s21204 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 21 | s21321–s21352 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 22 | s21957–s21988 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 23 | s22105–s22136 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 24 | s22741–s22772 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 25 | s22889–s22920 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 26 | s23525–s23556 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 27 | s23673–s23704 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 28 | s24309–s24340 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 29 | s24457–s24488 | 32 | **2** | **64** | **32** | **64** | 32 OK | spec says 128/64/64 → **wrong** | +| 30 | s25093–s25124 | 32 | 1 | 64 | 64 | 32 | 32 OK | OK | +| 31 | s25824–s25919 | 96 | **8** | **16** | **96** | **256** | 1·12·8 = 96 OK | spec says 128/768/256 → **wrong** | +| 32 | s26124–s26139 | 16 | **2** | **64** | **16** | **64** | 4·2·2 = 16 OK | spec says 128/32/64 → **wrong** | + +Method, on phase 6 as the example: the 48 `mma` (s12449–s12496) split into 16 +chains of 3, e.g. `s12449 → s12451 → s12453` (C of each is the D of the +previous), each chain consuming three A fragments and three B fragments. So +`k_steps = 3`, `distinctA = 12 = 4 m_tiles × 3`, `distinctB = 12 = 4 n_tiles × 3`. +The spec's `M=192 N=96` double-counts the k-steps on both sides; the true shape +is `64×32 = (64×96)·(96×32)`, i.e. the same P·V GEMM enc0's phase 6 is. + +Every row above satisfies `M/16 · N/8 · K/32 == mma` once `k_steps` is taken out +of the fragment counts. **No row is left unexplained.** + +### 2.2 Weight image extent + +`rr_layer_spec.py --geometry` reports `enc1 … image=96468`, which is +`(highest immediate) + (width of that access)`. That number is exact for the +`W + 16*laneid + imm` B-fragment loads but **undercounts the per-lane *table* +loads**, whose base is `W + ((laneid*4)&12)`: the highest such immediate is +`+96464` (`ld.global.u32 %r32027, [%rd485+96464]` at s26123, the second of phase +32's C seeds), and `%rd485 = %rd3 + ((laneid<<2)&12)` (s26118–s26121), so for +lanes with `laneid&3 == 3` the address reaches `96464 + 12 + 4`. + +``` +s26117 L66827: mov.u32 %r31887, %laneid +s26118 L66829: shl.b32 %r32050, %r31887, 2 +s26120 L66831: and.b64 %rd484, %rd483, 12 +s26121 L66832: add.s64 %rd485, %rd543, %rd484 +s26123 L66834: ld.global.u32 %r32027, [%rd485+96464] +``` + +Taking the per-lane bases into account over every load in the entry, the highest +byte touched is **96480**; the largest `W + 16*laneid + imm` load ends at 96448 +(phase 32's B, `+95936` tile). So the image spans at least **96480 bytes**. + +### 2.3 Phases that read no weight operand + +* **Phase 6** (`s12449–s12496`) and **phase 13** (`s16974–s17021`) read **no + weight bytes at all**: both A and B come from registers. Phase 6's A is the + packed softmax of phase 5's D and its B is the `movmatrix` transpose of phase + 4's D, both packed in E5 (s12233–s12448, see §3/E5(g)); phase 13's A and B are + packed in E12 (s16758–s16973) from phase 12's softmax and phase 11's D. Their + C operands are the zero register `%r15665` (§3/E5). +* **Phase 5** (`s8558–s8605`) and **phase 12** (`s13088–s13135`) read only a + **C bias operand**, never a B operand: their B comes from registers packed by + E4 (s8438–s8521) resp. E11 (s12968–s12990), while C is the 12288-byte score + table at `W+4224…W+16512` (24 tiles, E4 s8390–s8437) resp. `W+22656…W+34848` + (24 tiles, E11 s12920–s12967). + +So phases 1–4, 7–11, 14–32 read weight operands; 5 and 12 read only a bias +table; 6 and 13 read neither. + +### 2.4 Summary of the epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s8294–s8300 | 7 | next-B weight loads | +| E2 | s8325–s8331 | 7 | next-B weight loads | +| E3 | s8356–s8362 | 7 | next-B weight loads | +| E4 | s8387–s8557 | 171 | score-bias C-seed loads (24 tiles) + pack of D3 and D4 | +| E5 | s8606–s12448 | 3843 | softmax of the 64×96 score block, V-transpose, pack | +| E6 | s12497–s12760 | 264 | input-residual + per-column table add, pack, next B | +| E7 | s12793–s12799 | 7 | next-B weight loads | +| E8 | s12824–s12830 | 7 | next-B weight loads | +| E9 | s12855–s12861 | 7 | next-B weight loads | +| E10 | s12886–s12892 | 7 | next-B weight loads | +| E11 | s12917–s13087 | 171 | score-bias C-seed loads (24 tiles) + pack of D10 | +| E12 | s13136–s16973 | 3838 | softmax (2nd window, same code as E5) | +| E13 | s17022–s17080 | 59 | pack of D13 → next A; next B loads | +| E14 | s17113–s18759 | 1647 | RMS norm + gain, 8 next-B / next-C loads, pack of the normed tile | +| E15 | s18792–s19604 | 813 | clamped cubic activation + column table add + pack | +| E16 | s19637–s19752 | 116 | next B/C loads + pack of the normed tile | +| E17 | s19785–s20388 | 604 | clamped cubic activation + pack | +| E18 | s20421–s20536 | 116 | next B/C loads + pack of the normed tile | +| E19 | s20569–s21172 | 604 | clamped cubic activation + pack | +| E20 | s21205–s21320 | 116 | next B/C loads + pack of the normed tile | +| E21 | s21353–s21956 | 604 | clamped cubic activation + pack | +| E22 | s21989–s22104 | 116 | next B/C loads + pack of the normed tile | +| E23 | s22137–s22740 | 604 | clamped cubic activation + pack | +| E24 | s22773–s22888 | 116 | next B/C loads + pack of the normed tile | +| E25 | s22921–s23524 | 604 | clamped cubic activation + pack | +| E26 | s23557–s23672 | 116 | next B/C loads + pack of the normed tile | +| E27 | s23705–s24308 | 604 | clamped cubic activation + pack | +| E28 | s24341–s24456 | 116 | next B/C loads + pack of the normed tile | +| E29 | s24489–s25092 | 604 | clamped cubic activation + pack | +| E30 | s25125–s25823 | 699 | pack → destination-buffer scatter → 8-lane merge → next B/C | +| E31 | s25920–s26123 | 204 | pack → 2nd-buffer scatter → `%tid.x` → next B/C | +| E32 | s26140–s26819 | 680 | cross-lane row max, softmax, texture gather, surface stores | + +--- + +## 3. The epilogues + +### E1–E3, E7–E10 — s8294–s8300, s8325–s8331, s8356–s8362, s12793–s12799, s12824–s12830, s12855–s12861, s12886–s12892: next-B loads + +Seven statements each, all the same shape: + +``` +s8294 L13511: mov.u32 %r5787, %laneid +s8298 L13517: ld.weak.global.ca.v4.u32 { %r5788,%r5789,%r5790,%r5791},[%rd105] +s8300 L13521: ld.weak.global.ca.v4.u32 { %r5792,%r5793,%r5794,%r5795},[%rd106] +``` + +`mul.wide.u32` + two `add.s64` + two `ld.weak.global.ca.v4.u32` = +`W + 16*laneid + {P, P+512}` for the next phase's 4 B fragments. Offsets: + +| epilogue | phase it feeds | offsets | +|---|---|---| +| E1 | 2 | +2176, +2688 (s8296, s8299) | +| E2 | 3 | +1152, +1664 | +| E3 | 4 | +3200, +3712 | +| E7 | 8 | +18560, +19072 | +| E8 | 9 | +20608, +21120 | +| E9 | 10 | +19584, +20096 | +| E10 | 11 | +21632, +22144 | + +### E4 — s8387–s8557: score-bias C-seed loads + pack of D3 + +171 statements: **24 `ld.weak.global.ca.v4.u32`** (s8391–s8437, one per `add.s64` +at s8390–s8436) and **80 packs / 40 b32** (s8438–s8557). + +1. **Score bias** (s8388–s8437): `ld.weak.global.ca.v4.u32 …, + [W + 16*laneid + 4224 + 512*i]`, `i = 0…23` — the phase-5 score-bias C seeds, + byte block `[4224, 16512)` = 12288 bytes = 6144 f16 = 24 tiles of 512 bytes. + The last offset is `+16000` (s8436, `%rd134`), whose 16 bytes end at 16512. +2. **Packs** (s8438–s8557): 80 `cvt.rn.satfinite.e4m3x2.f16x2` + 40 `mov.b32`, + whose sources are **all 48 registers of phase 3's D** (`%r6045…%r6276`, + verified: the set of cvt source registers is exactly that range). They form + *both* operands of phase 5: + * `%r7077 %r7078`, `%r7087 %r7088`, … `%r7187 %r7188` (24 b32) = phase 5's + **B** fragments, built by shuffling phase 3's D (`s8438: cvt …%r6065`, + `s8439: cvt …%r6045`, `s8440: mov.b32 %r7077, {%rs2730,%rs2731}`); and + * `%r6823 %r6824 %r6825 %r6826`, `%r6943…`, `%r7063…`, `%r7183…` (16 b32) = + phase 5's **A** fragments, also from phase 3's D (`s8512: mov.b32 %r6823, + {%rs2778, %rs2779}` from `%r6045`/`%r6065`). + + So phase 5 computes `scores = pack(D3)·pack(D3)` — **Q and K are the same + projection**, and the V operand is phase 4's D, which E5's `movmatrix` block + transposes into phase 6's B (§3/E5(f)). + +**The C-seed layout** (identical for phase 5 and phase 12): the four C registers +of one mma are the four `u32` of one 16-byte lane slot, and + +``` +C(m, n) = tile(4*(n>>1) + m) + 4*(n&1) [tile index within the block] +byte = base + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1) +``` + +so the tile index runs `4*(n>>1) + m` (stride 512 bytes) over 4 m-tiles and +24 `(n>>1)` groups = 24 tiles = 12288 bytes. Verified from phase 5's own +operands: `s8558 C={%r6535,%r6536}` … `s8570 C={%r6539,%r6540}` (the second +m-tile row), i.e. consecutive `v4` registers from one 16-byte slot. + +### E5 — s8606–s12448: softmax of the 64×96 score block + +**Phase 5** = 48 `mma` (s8558–s8605), D registers `%r6711…%r7182` (96 f16x2 = +64 rows × 96 columns held 8 rows × 24 cols per lane). The epilogue has **no memory access at all** (0 `ld.*`, +0 `st.*`); it reads **phase 5's D** (the 96 score registers, for the softmax) and +**phase 4's D** (through the `movmatrix` block), plus the constants, and writes +phase 6's operands. + +Sub-sections (boundaries found from the op sequence; the per-element group is +22 statements and there are exactly 96 `and.b32 …, 2145419232`): + +| range | stmts | what | +|---|---|---| +| s8606–s10723 | 2118 | 96 per-element groups: scale, clamp, cubic, exponent extract | +| s10724–s10803 | 80 | partial row-sum trees (in-lane `add.f16x2`) | +| s10804–s10939 | 136 | 16 `shfl.sync.bfly` → 8 row sums | +| s10940–s11701 | 762 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s11702–s12184 | 483 | 192 `mul.f16` → 96 probabilities | +| s12185–s12232 | 48 | `movmatrix` transpose of phase 4's D | +| s12233–s12448 | 216 | 72 packs (144 `cvt.rn.satfinite.e4m3x2.f16x2`) | + +#### (a) per-element exponent, s8606–s10723 + +``` +s8607 L14773: mov.f32 %f956, 0f3C8CCB50 +s8610 L14781: mul.f16x2 %r7193,%r6711,%r7192 +s8615 L14795: max.f16x2 %r7196,%r7193,%r7198 +s8620 L14809: min.f16x2 %r7199,%r7196,%r7201 +s8626 L14827: fma.rn.f16x2 %r7204,%r7199,%r7202,%r7207 +s8631 L14841: fma.rn.f16x2 %r7208,%r7199,%r7204,%r7211 +s8632 L14844: shl.b32 %r30241, %r7208, 5 +s8633 L14845: and.b32 %r9113, %r30241, 2145419232 // 0x7FE07FE0 +``` + +For each of the 96 f16x2 D registers, per half (an f16 value `x`): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) // s8610,s8615,s8620 +t = f16(m*(-m) + 0.92724609375) // s8626 fma +u = f16(m*t + 1.375) // s8631 fma + = f16(1.375 + m*(0.92724609375 - m^2)) +E = bits(u)[9:5] // floor(32*frac(u)) +F = bits(u)[4:0] // the low five mantissa bits +expval = f16 from bits (E << 10) | (F << 5) // = 2^(E-15) * (1 + F/32) +``` + +`((u_bits << 5) & 0x7FE07FE0)` keeps `u`'s mantissa and drops sign and exponent, +so the mantissa lands in the exponent field. Numerically +`expval ≈ 2^(32*frac(u) - 15) = 2^(32u - 47)` and, because the clamp keeps +`u ∈ [1.03125, 1.71875]`, `expval ∈ [2⁻¹⁴, 2⁸]`. **This is not `exp` and not +`exp2(x*log2e)`**: the exponent is the *cubic* `32*(0.375 + 0.92724609375*m − m³)` +quantised to a 6-bit significand (1.5 % relative granularity). The two `f64` +literals exist only so the clamp is the *exact* f16 value. + +#### (b) in-lane partial sums, s10724–s10803 + +80 `add.f16x2` reduce the 96 `expval` registers in tree fashion: + +``` +s10724 L21307: add.f16x2 %r9112,%r9113,%r9114 +s10750 L21411: add.f16x2 %r9190,%r9191,%r9192 +s10782 L21539: add.f16x2 %r9286,%r9274,%r9262 +``` + +Each lane reduces its 96 values (8 rows × 12 registers) to 16 f16x2 partials. + +#### (c) cross-lane row sums, s10804–s10939 + +``` +s10810 L21641: shfl.sync.bfly.b32 %r9357,%r9353,%r16376,%r9360,%r16387 +s10811 L21645: add.f16x2 %r9362,%r9353,%r9357 +s10816 L21656: shfl.sync.bfly.b32 %r9366,%r9362,%r16385,%r9369,%r16387 +s10817 L21660: add.f16x2 %r9371,%r9362,%r9366 +s10818 L21663: mov.b32 {%rs3579, %rs3580}, %r9371 +s10819 L21665: add.f16 %rs3578,%rs3579,%rs3580 +s10820 L21668: mov.b32 %r9568, {%rs3578, %rs3578} +``` + +Eight times (one per row `g, g+8` of the four m-tiles): add the two f16x2 +partials, butterfly over lane bits 0 and 1 (`%r16376 = 1`, `%r16385 = 2`), add +the two halves with `add.f16`, then broadcast into both halves. Result: +**8 row sums** `%r9568`, `%r9572`, … (rows `g`, `g+8` of m-tiles 0…3), covering +all 96 columns because the four lanes with equal `laneid&7` hold different +column pairs. + +The shuffle's `c` operand is built as `(WARP_SZ<<8) - 8192 | 31` (s10807–s10809) +rather than a plain constant; since `WARP_SZ = 32`, that is `8192 - 8192 | 31 = 31`. + +**There is no row maximum anywhere in this epilogue**: the only `max.f16x2` +(96×) and `min.f16x2` (96×) are the clamp of (a); the only warp shuffles are the +16 `shfl.sync.bfly` above. See §6. + +#### (d) reciprocal, s10940–s11701 + +192 `rcp.approx.ftz.f32` = 96 f16x2 reciprocals, each computed as +`cvt.f32.f16 → rcp.approx.ftz.f32 → cvt.rn.f16.f32` on a row-sum register +(duplicated, so each row sum is inverted once per n-tile of that row): + +``` +s11025 L22107: mov.b32 {hl, hu}, %r9572 +s11028 L22110: rcp.approx.ftz.f32 fl, fl +s11029 L22111: rcp.approx.ftz.f32 fu, fu +s11032 L22114: mov.b32 %r9547, {hl, hu} +``` + +#### (e) probabilities, s11702–s12184 + +``` +s11705 L23209: mov.b32 {%rs3603, %rs3606}, %r9113 // expval (row g) +s11706 L23210: mov.b32 {%rs3604, %rs3607}, %r9525 // 1/rowsum +s11707 L23212: mul.f16 %rs3605,%rs3606,%rs3607 +s11708 L23216: mul.f16 %rs3602,%rs3603,%rs3604 +s11709 L23219: mov.b32 %r9861, {%rs3602, %rs3605} +``` + +192 `mul.f16` → 96 f16x2 results `p = expval * (1/rowsum)` — the row sums +cancel the constant `2⁻⁴⁷` of (a), so `p_ij ∝ 2^(32·u_ij)` and +`Σ_j p_ij = 1` up to the `rcp.approx` error. + +#### (f) V-transpose, s12185–s12232 + +``` +s12185 L24266: movmatrix.sync.trans.aligned.m8n8.b16 %r9717, %r6294 +s12186 L24269: movmatrix.sync.trans.aligned.m8n8.b16 %r9719, %r6295 +s12189 L24278: movmatrix.sync.trans.aligned.m8n8.b16 %r9725, %r6334 +``` + +**48** `movmatrix` on 48 distinct **phase 4 D** registers (`%r6294…%r6525`, each +exactly once — the source list runs `%r6294 %r6295 %r6304 %r6305 %r6334 … +%r6524 %r6525`). Each instruction transposes one 8×8 b16 tile built from the +32 threads, i.e. 48 × 64 = 3072 values = the whole 96×32 D tile. + +#### (g) packs, s12233–s12448 + +72 packs, in two groups (classified by which phase-6 operand register they +write): + +1. **s12235–s12304** — 24 packs from the `movmatrix` results → phase 6's + **12 B fragments** (`%r10323 %r10333 %r10343 … %r10423 %r10433`, 24 b32): + `s12235: mov.b32 %r10323, {%rs4178, %rs4179}` where `%rs4178/%rs4179` come + from `%r9717`/`%r9725` (s12233–s12234). +2. **s12307–s12448** — 48 packs from the **probabilities** → phase 6's + **12 A fragments** (`%r10029 %r10031 %r10049 … %r10427 %r10428`, 48 b32): + `s12307: mov.b32 %r10029, {%rs4226, %rs4227}` where `%rs4226/%rs4227` come + from `%r9861`/`%r9862` — probability products (s11709 s11789). + +**Inputs:** phase 5's 96 D f16x2, phase 4's 48 D f16x2, `%r16376/%r16385/%r16387`. +**Outputs:** the 5 constants + phase 6's 48 A-register / 24 B-register operands. +**Memory read/written:** none. + +### E6 — s12497–s12760: input residual + per-column table, then pack + +264 statements; op mix: `add.f16:128, mov.b32:80, cvt…e4m3:32, ld.global.v2.u16:8, +ld.weak.global.ca.v4.u32:4`, 6 × `add.s64`. + +``` +s12501 L25256: ld.weak.global.ca.v4.u32 { %r10438,%r10439,%r10440,%r10441},[%rd135] +s12509 L25273: shl.b32 %r30369, %r10454, 2 +s12512 L25276: add.s64 %rd262, %rd3, %rd261 // W + ((laneid<<2)&12) +s12513 L25277: ld.global.v2.u16 {%rs9161, %rs9162}, [%rd262+37008] +s12520 L25284: ld.global.v2.u16 {%rs9175, %rs9176}, [%rd262+36992] +s12521 L25286: add.f16 %rs4325,%rs9176,%rs4327 +s12522 L25290: add.f16 %rs4322,%rs9175,%rs4324 +s12523 L25293: mov.b32 %r10495, {%rs4322, %rs4325} +s12713 L25862: cvt.rn.satfinite.e4m3x2.f16x2 %rs4707, %r10057 +s12715 L25867: mov.b32 %r10559, {%rs4706, %rs4707} +``` + +Four things happen, in this order: + +1. **Next-B loads** (s12497–s12507): four `v4.u32` fragments from + `W + 16*laneid + {16512, 17024, 17536, 18048}` → `%r10438…%r10453`, phase 7's + B operand (weight block `[16512, 18060)`). +2. **Table loads** (s12508–s12520): **eight** `ld.global.v2.u16` from + `W + ((laneid<<2)&12) + {36992, 37008, 37024, 37040, 37056, 37072, 37088, + 37104}` → 16 f16 (`%rs9161…%rs9176`). 16 bytes/lane × 32 lanes × 8 words = + 4096 bytes = **a per-column vector covering 32 columns** (8 words × 4 lanes + with distinct `laneid&3`). +3. **Residual + column table add** (s12521–s12712): 128 `add.f16`, i.e. 64 f16x2, + computed on the halves of the **dequantised input tile** — each + `%rs4324/%rs4327` is unpacked at s5827 `mov.b32 {%rs4324, %rs4327}, %r4678` + from `cvt.rn.f16x2.e4m3x2 %r4678, %rs107` (s5730), and `%rs107` is + `ld.global.v2.u16 …` at s173 from the `param_0+8` buffer. So: + + ``` + new_low = table[2t] + input_low s12522 + new_high = table[2t+1] + input_high s12521 + → packed into %r10495, %r10496, %r10505, %r10506, … (64 registers) + ``` + + These 64 registers are **phase 7's C operand** (`s12761` first mma + `C={%r10495,%r10496}`), so phase 7 computes + `D7 = A7·B7 + (input_tile + column_table)` — the attention out-projection + plus the *un-normalised input* residual, exactly enc0's E6 shape but with the + input patch instead of a second GEMM output. +4. **Pack** (s12713–s12760): 32 packs of **phase 6's D** (`%r9957…%r10428`, + 16 b32 = phase 7's A operand `%r10559` … `%r10802`) — the P·V output + requantised for the out-projection. + +**Outputs (80 live):** `%r10438…%r10453` (B), the 64 C seeds `%r10495…%r10806`, +the 16 packed A registers. **Memory:** 4 weight loads + 8 table reads. + +### E11 — s12917–s13087: score-bias C-seed loads + pack of D10 + +171 statements, identical in shape to E4 with different offsets: + +* **24 loads** at `W + 16*laneid + 22656 + 512*i`, `i = 0…23` (s12920–s12967) — + the phase-12 score-bias seeds, byte block `[22656, 34848)` = 12288 bytes. +* **80 packs / 40 b32** (s12968–s13087), whose sources are all registers written + by **phase 10's mma** (`%r11314…%r11465`, the D pairs of s12862–s12885). + Phase 11's D (`%r11555…`) is **not** read here; it is consumed by E12's + `movmatrix` block instead (s16710: `movmatrix… %r14986, %r11563`). + The 40 packed b32 split into phase 12's A fragments + (`s12968: cvt …%r11334`, `s12969: cvt …%r11314`, `s12970: mov.b32 %r12346, + {%rs4738, %rs4739}`) and phase 12's B fragments. + +### E12 — s13136–s16973: softmax, second window + +**Identical code to E5** with shifted registers; the op histogram is +byte-for-byte the same (1048 `mov.b32`, 672 `cvt.rn.f16.f32`, 384 +`cvt.rn.f16.f64`, 192 each `fma.rn.f16x2` / `cvt.f32.f16` / +`rcp.approx.ftz.f32` / `mul.f16`, 144 packs, 48 `movmatrix`). It re-uses E5's +constants (`%f956 %fd767 %fd769 %f958 %f960`, defined at s8607–s8627) and E5's +shfl operands `%r16376 %r16385 %r16387`, so it contains **no `mov.f32`/`mov.f64` +of its own**. + +Sub-sections (by the same markers): + +| range | what | +|---|---| +| s13136–s15248 | 96 exponent groups (`and.b32 …, 2145419232`, s13158…s15248) | +| s15249–s15457 | 80 in-lane partial-sum `add.f16x2` | +| s15335–s15456 | 16 `shfl.sync.bfly` → 8 row sums | +| s15465–s16226 | 192 `rcp.approx.ftz.f32` | +| s16232–s16708 | 192 `mul.f16` → 96 probabilities | +| s16710–s16757 | 48 `movmatrix` on phase 11's D (`s16710 L37129`) | +| s16758–s16973 | 144 packs (72 `mov.b32`) | + +(The `movmatrix` block is *before* the reciprocal block in program order here, +unlike enc0 where it also sits late; the statement index is what identifies it.) + +**Inputs:** phase 12's 96 D (`%r11980…`), phase 11's 48 D. **Outputs:** phase +13's 12 A fragments + 12 B fragments + the 5 constants. **Memory:** none. + +### E13 — s17022–s17080: pack of D13, next B + +59 statements: **4 `ld.weak.global.ca.v4.u32`** at +`W + 16*laneid + {34944, 35456, 35968, 36480}` (s17026–s17032) and **16 packs** +(s17035–s17080, 32 `cvt…e4m3` + 16 `mov.b32`) from **phase 13's D** +(`%r15226…%r15697`) → phase 14's A fragments +(`s17035: mov.b32 %r15827, {%rs6330, %rs6331}`). + +Phase 14's C is phase 7's D (see §3/E14 for the trace), so phase 14 is the +second window's out-projection whose residual is the *first window's whole +attention output*. + +### E14 — s17113–s18759: RMS norm before the MLP + +1647 statements, no stores. Structure (by op sequence): + +| range | stmts | op | +|---|---|---| +| s17113–s17368 | 256 | 32 × unpack of phase 14's D + 128 × `x·x` squares (last at s17367) | +| s17369–s17416 | 48 | in-lane `add.f16x2` | +| s17417–s17539 | 123 | 8 rows × (`add.f16x2` + 2 `shfl.sync.bfly` + `add.f16x2` + `add.f16` + broadcast) | +| s17540–s17543 | 4 | `+ eps` (2⁻¹³) | +| s17544–s18246 | 703 | 128 × `rsqrt.approx.ftz.f32` | +| s18247–s18260 | 14 | gain loads `+37120/37136/…/37232` | +| s18261–s18642 | 382 | 256 `mul.f16`: 128 × `inv · gain`, then 128 × `x · (inv·gain)` | +| s18643–s18654 | 12 | next-B loads `+37248/+37760/+38272/+38784` | +| s18655–s18663 | 9 | next-C loads `+39296/39312/39328/39344` | +| s18664–s18759 | 96 | 32 packs → phase 15's A | + +Evidence: + +``` +s17114 L38471: mul.f16 %rs6365,%rs7992,%rs7992 // square of a D half +s17423 L39316: shfl.sync.bfly.b32 %r16224,%r16220,%r16376,%r16227,%r16387 +s17541 L39626: cvt.rn.f16.f64 %rs6770, %fd770 // eps = 2^-13 +s17738 L40214: rsqrt.approx.ftz.f32 fl, fl +s18252 L41047: ld.global.v2.u16 {%rs9177, %rs9178}, [%rd277+37136] +s18261 L41057: mul.f16 %rs7155,%rs7156,%rs9191 // inv * gain +s18641 L42199: mul.f16 %rs7920,%rs8370,%rs7536 // x * (inv*gain) +s18664 L42240: cvt.rn.satfinite.e4m3x2.f16x2 %rs7924, %r28441 +``` + +**What it computes.** For each of the 8 rows a lane holds (8 columns each, +covering the 64×64 phase-14 D): + +``` +sumsq[row] = Σ_{c=0..31} x[row,c]^2 (f16, 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2^-13))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` + +* **no mean subtraction and no `1/N`**: the quantity is the *raw* sum of the 32 + squares in a row plus the constant `2^-13`; the mean is not formed. This is an + RMS norm, not a LayerNorm. +* `gain[c]` is read from `W + ((laneid<<2)&12) + {37120, 37136, 37152, 37168, + 37184, 37200, 37216, 37232}` (16 f16 per lane = 32 columns), so the gain is + per column, constant across rows. +* the `inv` register is duplicated into both halves of a b32 before use + (`mov.b32 %r16392, {hl, hu}`), so one row-sum value serves all n-tiles. +* the norm's *bias* is not added here — it is folded into phase 15's C operand, + loaded at the end of this epilogue (`+39296…+39344`, four `ld.global.u32`). + +**The normed tile** (32 f16x2 = `%r28440…%r28503`) is packed **eight times**, +once in E14 (s18664–s18759 → phase 15's A) and again in E16, E18, E20, E22, E24, +E26, E28 (each s19…/s20… pack of `%r28441`/`%r28440`, e.g. `s19657 L45595: +cvt.rn.satfinite.e4m3x2.f16x2 %rs8404, %r28441`). So all eight odd phases +15, 17, 19, 21, 23, 25, 27, 29 share one input tile. + +### E15 — s18792–s19604: clamped cubic activation, column table, pack + +813 statements. This is the only epilogue that materialises `%f1981…%f1984` +(the four activation constants of §1.2): + +``` +s18793 L42690: mov.f32 %f1981, 0f3ED306EB +s18796 L42697: mov.f32 %f1982, 0f3DA60DD6 +s18799 L42704: mov.f32 %f1983, 0f3F000000 // 0.5 +s18802 L42711: mov.f32 %f1984, 0f40000000 // 2.0 +s18805 L42719: neg.f16x2 %r16928,%r16927 +s18806 L42723: max.f16x2 %r16930,%r16623,%r16928 +s18807 L42727: min.f16x2 %r16933,%r16930,%r16927 +s18808 L42731: abs.f16x2 %r16936,%r16933 +s18809 L42735: mul.f16x2 %r16938,%r16925,%r16936 +s18810 L42739: sub.f16x2 %r16941,%r16924,%r16938 +s18811 L42743: mul.f16x2 %r16944,%r16933,%r16941 +s18812 L42747: add.f16x2 %r16947,%r16926,%r16944 +s18813 L42751: mul.f16x2 %r16950,%r16623,%r16947 +``` + +Per element, over each of the 32 f16x2 D registers of phase 15 +(`%r16603 %r16613 %r16623 …`, 64 f16 per lane): + +``` +y = clamp(x, -2, +2) +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a *cubic ramp*, not a sigmoid: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`; `g(1) = 0.831055` where `x·sigmoid(x) = +0.730957`. **Reproduce the formula, not SiLU/GELU.** + +Then: + +| range | op | +|---|---| +| s18803–s19340 | 32 activation groups (each 4 constants + 11 f16x2 ops) | +| s19341–s19351 | next-B loads: `+40448 +512*i`, `i=0..3` → phase 16's B | +| s19352–s19364 | lane-shift setup + 8 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {41408,41424,41440,41456,41472,41488,41504,41520}` | +| s19365–s19555 | 128 `add.f16` (64 f16x2) — table add, written over **phase 14's D** | +| s19559–s19604 | 16 packs of the activation outputs → phase 16's A | + +Evidence for the table add: + +``` +s19365 L44651: add.f16 %rs7990,%rs9208,%rs7992 +s19366 L44655: add.f16 %rs7987,%rs9207,%rs7989 +s19367 L44658: mov.b32 %r17910, {%rs7987, %rs7990} +s19559 L45232: mov.b32 %r17974, {%rs8371, %rs8372} +``` + +`%rs7989/%rs7992` are the halves of `%r15755` (phase 14's D, unpacked at +`s17113: mov.b32 {%rs7989, %rs7992}, %r15755`), so +`%r17910 = phase14_D + table[column]`. The 64 such registers +(`%r17910 %r17920 %r17930 …`) are **phase 16's C operand** +(`s19605 C={%r17910,%r17911}`); `%r17853 %r17857 %r17861 %r17865` are phase 16's +B fragments (weight image, `+40448…`). + +**Outputs:** `%f1981…%f1984` (consumed again by E17, E19, E21, E23, E25, E27, +E29), the 64 C seeds (`%r17910…%r18221`), the 16 packed A registers +(`%r17974…%r18217`), and the 4 next-B fragments (`%r17853 %r17857 %r17861 +%r17865`, from the s19345–s19351 loads). + +### E16, E18, E20, E22, E24, E26, E28 — s19637–s19752 etc.: next B/C loads + pack of the normed tile + +116 statements each, identical shape. Taking E16 as the example: + +``` +s19638 L45565: mul.wide.u32 %rd288, %r18222, 16 +s19641 L45569: ld.weak.global.ca.v4.u32 { %r18223,…, %r18226},[%rd183] // +41536 +s19643 L45573: ld.weak.global.ca.v4.u32 { %r18227,…, %r18230},[%rd184] // +42048 +s19645 L45577: ld.weak.global.ca.v4.u32 { %r18231,…, %r18234},[%rd185] // +42560 +s19647 L45581: ld.weak.global.ca.v4.u32 { %r18235,…, %r18238},[%rd186] // +43072 +s19653 L45590: ld.global.u32 %r18553, [%rd292+43584] +s19654 L45591: ld.global.u32 %r18563, [%rd292+43600] +s19655 L45592: ld.global.u32 %r18593, [%rd292+43616] +s19656 L45593: ld.global.u32 %r18603, [%rd292+43632] +s19657 L45595: cvt.rn.satfinite.e4m3x2.f16x2 %rs8404, %r28441 +``` + +* phase 17's B at `W + 16*laneid + {41536, 42048, 42560, 43072}`; +* **phase 17's C/bias**: 4 `ld.global.u32` at `W + ((laneid<<2)&12) + + {43584, 43600, 43616, 43632}` → `%r18553 %r18563 %r18593 %r18603`. Each of + those four u32 is used in **both halves** of an mma C operand + (`{%r18553, %r18553}` at s19753), i.e. a per-column bias replicated over the + 16 rows of a tile and reused by all four m-tiles; +* **32 packs** of `%r28440…%r28441` — **the normed tile E14 produced** — giving + phase 17's A (`%r18356…%r18619`). + +The offsets of the other six epilogues (each 4 × B + 4 × C + 32 packs): + +| epilogue | phase it feeds | B offsets | C/bias offsets | +|---|---|---|---| +| E16 | 17 | 41536, 42048, 42560, 43072 | 43584, 43600, 43616, 43632 | +| E18 | 19 | 45696, 46208, 46720, 47232 | 47744, 47760, 47776, 47792 | +| E20 | 21 | 49856, 50368, 50880, 51392 | 51904, 51920, 51936, 51952 | +| E22 | 23 | 54016, 54528, 55040, 55552 | 56064, 56080, 56096, 56112 | +| E24 | 25 | 58176, 58688, 59200, 59712 | 60224, 60240, 60256, 60272 | +| E26 | 27 | 62336, 62848, 63360, 63872 | 64384, 64400, 64416, 64432 | +| E28 | 29 | 66496, 67008, 67520, 68032 | 68544, 68560, 68576, 68592 | + +(from the phase table's `bias bytes` column; the B offsets are the four `add.s64` +immediates preceding the four `ld.weak.global.ca.v4.u32`.) + +### E17, E19, E21, E23, E25, E27, E29 — s19785–s20388 etc.: clamped cubic activation, pack + +604 statements each; identical histograms (`mov.b32:144, cvt.rn.f16.f32:128, +mul.f16x2:96, neg/max/min/abs/sub/add f16x2: 32 each, cvt…e4m3:32, 4 weight +loads`, **no `ld.global`, no constants of its own**). + +``` +s19795 L46074: max.f16x2 %r18631,%r18324,%r18629 // phase 17's D +s19796 L46078: min.f16x2 %r18634,%r18631,%r18628 +s19812 L46134: max.f16x2 %r18660,%r18334,%r18658 +s20334 L47972: ld.weak.global.ca.v4.u32 { %r19554,…, %r19557},[%rd187] // +43648 +s20343 L47992: mov.b32 %r19674, {%rs8467, %rs8468} +``` + +Same function as E15: `out = x·(0.5 + y·(0.412109375 − 0.0810546875|y|))`, +`y = clamp(x,±2)`, over the 32 D registers of the phase, then 32 packs **of the +activation outputs** (`%r19674…%r19917`) → the next phase's A, plus 4 weight +loads → the next phase's B. **No column-bias add and no column table.** + +The four activation constants are re-read by `cvt.rn.f16.f32` from +`%f1981…%f1984` (e.g. E17 has `128 cvt.rn.f16.f32` and zero `mov.f32`). + +#### Shape of the whole MLP region (E14–E30) + +Putting the pack destinations and the C operands together (all verified by +tracing each `mov.b32 %rX, {%rsA, %rsB}` back through its two `cvt` statements, +and each C register back to its `mma` in the *previous even* phase): + +``` +E14 normed tile N (32 f16x2, %r28440…%r28503) + ├─ pack → P15 A (s18664) P15: A=N, B=W15, C=bias@39296 → D15 → E15 activation + │ E15 packs act(D15) → P16 A (s19559) + │ P16: C = D14 + table@41408 → D16 (s19605) + ├─ pack → P17 A (s19657) P17: A=N, B=W17, C=bias@43584 → D17 → E17 activation + │ E17 packs act(D17) → P18 A (s20343) + │ P18: C = D16 → D18 (s20389) + ├─ pack → P19 A (s20443) P19: A=N, B=W19, C=bias@47744 → D19 → E19 activation + │ E19 packs act(D19) → P20 A (s21127) + │ P20: C = D18 → D20 (s21173) + ├─ pack → P21 A (s21227) P21: A=N, B=W21, C=bias@51904 → D21 → E21 activation + │ E21 packs act(D21) → P22 A (s21911) + │ P22: C = D20 → D22 (s21957) + ├─ pack → P23 A (s22011) P23: A=N, B=W23, C=bias@56064 → D23 → E23 activation + │ E23 packs act(D23) → P24 A (s22695) + │ P24: C = D22 → D24 (s22741) + ├─ pack → P25 A (s22795) P25: A=N, B=W25, C=bias@60224 → D25 → E25 activation + │ E25 packs act(D25) → P26 A (s23479) + │ P26: C = D24 → D26 (s23525) + ├─ pack → P27 A (s23579) P27: A=N, B=W27, C=bias@64384 → D27 → E27 activation + │ E27 packs act(D27) → P28 A (s24263) + │ P28: C = D26 → D28 (s24309) + └─ pack → P29 A (s24363) P29: A=N, B=W29, C=bias@68544 → D29 → E29 activation + E29 packs act(D29) → P30 A (s25045) + P30: C = D28 → D30 (s25093) +``` + +So the region is **eight bottleneck residual blocks** `64 → 32 → 64`: every odd +phase expands the shared normed tile into 32 channels with its own weight and +per-column bias, its epilogue applies the clamped cubic activation, and the +following even phase projects back to 64 channels and adds the running residual +(`D16 = D14 + table + act(D15)·W16`, then `D18 = D16 + act(D17)·W18`, …, +`D30 = D28 + act(D29)·W30`). The only difference from enc0 is the count +(eight blocks instead of four) and the first residual's `+ table` term. + +### E30 — s25125–s25823: pack → destination-buffer scatter → 8-lane merge → next B/C + +699 statements. Four sub-sections: + +#### (a) requantise, s25125–s25220 + +64 `cvt.rn.satfinite.e4m3x2.f16x2` + 32 `mov.b32` → `%r317 … %r348` +(phase 30's 64×64 output as 32 b32 = 64 e4m3 per lane). + +#### (b) destination-buffer scatter, s25221–s25630 + +``` +s25221 L65106: ld.param.u64 %rd337, [%rd1+-32] // %rd1 = param_0+80 → param+48 +s25222 L65107: cvta.to.global.u64 %rd5, %rd337 +s25223 L65109: mov.u32 %r30186, %laneid +s25224 L65111: shr.u32 %r349, %r30186, 2 // g = laneid>>2 +s25225 L65112: and.b32 %r350, %r30186, 3 // t = laneid&3 +s25226 L65113: shr.u32 %r30540, %r30186, 5 // laneid>>5 +s25227 L65114: and.b32 %r30541, %r349, 7 // g&7 +s25228 L65115: add.s32 %r30542, %r7, %r30540 // y = %r7 + (laneid>>5) +s25234 L65121: add.s32 %r30543, %r1, %r30541 // x = %r1 + (g&7) +s25239 L65126: shl.b32 %r30544, %r30543, 3 +s25240 L65127: mad.lo.s32 %r351, %r5, %r30542, %r30544 +s25241 L65128: add.s32 %r30545, %r350, %r351 +s25247 L65135: st.global.u32 [%rd339], %r317 +``` + +Thirty-two stores `st.global.u32 [%rd5 + 4*idx], v` (s25247…s25630, one per +`selp.b32`+`bra` guard), writing `%r317…%r348` **in that order**. The index is + +``` +idx = %r5 * y + 8*x + d, %r5 = ex<<3 +d = t (even-numbered store) or t|4 (odd-numbered store) +``` + +and the y/x bases are the eight values `(g + 8j)`, `j = 0…7`: + +``` +y = %r7 + ((g + 8j) >> 3) // j=0 uses the raw laneid>>5 (s25226) +x = %r1 + ((g + 8j) & 7) // j=0 uses the raw g&7 (s25227) +``` + +`g = laneid>>2`, `t = laneid&3`. The bases are recomputed at s25260 (`+8`), +s25328 (`+16`), s25362 (`+24`), s25430 (`+32`), s25464 (`+40`), s25532 (`+48`), +s25566 (`+56`); group 0's base is the prologue's raw `%r30540`/`%r30541`. Each +store is guarded by the compiler's standard triplet, +`selp.b32 %r, -1, idx, %p` (s25242 and 31 siblings) + `setp.lt.s32 %p, %r, 0` + +`@%p bra`, where `%p` is the disjunction +`(y<0) | (y ≥ ey) | (laneid > 255 or (g+8j) > 63) | (x<0) | (x ≥ ex)` +(`s25229–s25238` for group 0), so a guard failure becomes "skip the store". + +The stride is `%r5 = ex<<3`, so the buffer is `8*ex` 4-byte words = 32*ex bytes +wide per row. Which of the eight bases each individual store uses is not +determined by the PTX alone — see §6 U6. + +#### (c) 8-lane merge, s25632–s25707 + +``` +s25638 L65591: and.b32 %r31799, %r30619, 4 +s25640 L65593: setp.eq.s32 %p422, %r31799, 0 +s25644 L65597: shfl.sync.down.b32 %r31804|%p423, %r317, %r31800, %r31802, %r31803 +s25645 L65598: shfl.sync.up.b32 %r31805|%p424, %r325, %r31800, %r31801, %r31803 +s25646 L65599: selp.b32 %r31626, %r317, %r31805, %p422 +s25647 L65600: selp.b32 %r31666, %r31804, %r325, %p422 +``` + +**Sixteen** `shfl.sync.down/up` pairs, all with **delta = 4** (`%r31800 = +mov.u32 4`, s25639), width operand `31` for the `.down` (`%r31802`, s25642) and +`0` for the `.up` (`%r31801`, s25641), membermask `-1` (`%r31803`, s25643), and +the selection predicate `%p422 = (laneid & 4) == 0`: + +``` +down = a[lane+4] (shfl.sync.down, delta 4) +up = a[lane-4] (shfl.sync.up, delta 4) +dst1 = p422 ? own_low : up +dst2 = p422 ? down : own_high +``` + +so each pair re-pairs the two members of `{lane, lane±4}`. The sixteen +destinations are **phase 31's A operand** — `s25824` first mma uses +`{%r31626, %r31627, %r31628, %r31629}`. + +#### (d) next B/C loads, s25708–s25823 + +``` +s25712 L65668: ld.weak.global.ca.v4.u32 { %r30621,…, %r30624},[%rd402] // +70656 +s25714 L65672: ld.weak.global.ca.v4.u32 { %r30625,…, %r30628},[%rd403] // +71168 + … one every 512 bytes, 48 of them, up to +94720 (s25805) +s25812 L65865: ld.global.u32 %r30823, [%rd454+95232] + … twelve in all, +95232 … +95408 (s25823) +``` + +* **48 weight fragments** at `W + 16*laneid + 70656 + 512*i` → phase 31's B; +* **12 bias words** at `W + ((laneid<<2)&12) + {95232…95408}` → phase 31's C + seeds, each used in both halves (`s25824 C={%r30823,%r30823}`). + +**Inputs:** phase 30's D, `%r1/%r5/%r7/%r465/%r466`. **Outputs (live):** +`%r317…%r348` (read again by the merge *and* by phase 32), the 16 merged A +registers, phase 31's B and C. + +### E31 — s25920–s26123: pack → 2nd-buffer scatter → `%tid.x` → next B/C + +204 statements. + +#### (a) requantise, s25921–s25954 + +24 `cvt.rn.satfinite.e4m3x2.f16x2` (each on a phase-31 D register +`%r30954…%r31765`) grouped 2-by-2 into **12 e4m3 pairs**: 10 of them are +immediately combined with `mov.b32` into `%r400 … %r409`, and the first two pairs +are kept as the raw `{%rs9209,%rs9210}` and `{%rs9231,%rs9232}` for the +`v2.u16` stores. + +``` +s25921 L66551: cvt.rn.satfinite.e4m3x2.f16x2 %rs9209, %r30954 +s25922 L66554: cvt.rn.satfinite.e4m3x2.f16x2 %rs9210, %r31114 +s25925 L66562: mov.b32 %r400, {%rs9211, %rs9212} +s25953 L66627: cvt.rn.satfinite.e4m3x2.f16x2 %rs9231, %r31605 +s25954 L66630: cvt.rn.satfinite.e4m3x2.f16x2 %rs9232, %r31765 +``` + +#### (b) coordinate / 2nd-buffer scatter, s25955–s26107 + +``` +s25955 L66632: ld.param.v2.u32 {%r31837, %r31838}, [%rd535+-80] // param+0, extents +s25956 L66633: shr.u32 %r412, %r31838, 1 // ey>>1 +s25957 L66634: shr.u32 %r413, %r31837, 1 // ex>>1 +s25958 L66635: shl.b32 %r414, %r413, 3 // 8*(ex>>1) +s25959 L66636: mul.lo.s32 %r415, %r412, %r414 // row stride +s25963 L66642: ld.param.u64 %rd455, [%rd535+-24] // param+56 +s25964 L66643: cvta.to.global.u64 %rd7, %rd455 +s25965 L66644: and.b32 %r31839, %r416, 1 // g&1 +s25969 L66648: bfi.b32 %r31843, %r31842, %r31839, 1, 31 // ((laneid>>5)&~2)|((g&1)<<1) +s25973 L66652: add.s32 %r31846, %r418, %r31843 // y +s25982 L66661: add.s32 %r31849, %r419, %r31841 // x +s25988 L66667: mad.lo.s32 %r420, %r414, %r31846, %r31850 +s25995 L66675: st.global.v2.u16 [%rd457], {%rs9209, %rs9210} +``` + +The destination is **`param_0+56`**, not the plane arena; extents come from +`param+0` and are *halved*. Two index bases are formed, `%r421` (s25990, the +`(g&1)`-bfi'd `y` with `x = (%r1>>1) + ((laneid>>3)&3)`) and `%r424` (s26026, +the same shape recomputed from a shifted index), each guarded by a +`(y<0)|(y≥(ey>>1))|(tile bits>3)|(x<0)|(x≥(ex>>1))` predicate (`%p9`, `%p10`). + +**Twelve guarded stores**, all at `base + (t or t|4)` in 4-byte units: + +| # | statement | value | base | d | +|---|---|---|---|---| +| 1 | s25995 `st.global.v2.u16` | `{%rs9209, %rs9210}` | `%r421` | `t` | +| 2 | s26004 `u32` | `%r400` | `%r421` | `t\|4` | +| 3 | s26031 `u32` | `%r401` | `%r424` | `t` | +| 4 | s26039 `u32` | `%r402` | `%r424` | `t\|4` | +| 5 | s26048 `u32` | `%r403` | `%r421` | `t` | +| 6 | s26056 `u32` | `%r404` | `%r421` | `t\|4` | +| 7 | s26065 `u32` | `%r405` | `%r424` | `t` | +| 8 | s26073 `u32` | `%r406` | `%r424` | `t\|4` | +| 9 | s26082 `u32` | `%r407` | `%r421` | `t` | +| 10 | s26090 `u32` | `%r408` | `%r421` | `t\|4` | +| 11 | s26099 `u32` | `%r409` | `%r424` | `t` | +| 12 | s26107 `st.global.v2.u16` | `{%rs9231, %rs9232}` | `%r424` | `t\|4` | + +(the guard predicates alternate `%p9`/`%p10` exactly as listed by the `selp.b32` +at s25999, s26034, s26043, s26051, s26060, s26068, s26077, s26085, s26094, +s26102.) + +#### (c) next B/C and `%tid.x`, s26109–s26123 + +``` +s26114 L66820: ld.weak.global.ca.v4.u32 { %r31879,…, %r31882},[%rd480] // +95424 +s26116 L66824: ld.weak.global.ca.v4.u32 { %r31883,…, %r31886},[%rd481] // +95936 +s26122 L66833: ld.global.u32 %r32017, [%rd485+96448] +s26123 L66834: ld.global.u32 %r32027, [%rd485+96464] +``` + +phase 32's B fragments (`W + 16*laneid + 95424 + 512*i`) and two C seeds +(`W + ((laneid<<2)&12) + {96448, 96464}`). + +### E32 — s26140–s26819: the final epilogue + +679 statements in **two identical passes** (the second at s26554 onward). Each +pass selects the four f16 values of a row from phase 32's D registers, does a +cross-lane row maximum, an f32 softmax, nine `tex.base.2d.v4.f16.s32` gathers, +an f16 fma accumulation, a sigmoid difference, a two-step cross-lane sum, and +three `sust.b.2d.v4.b16.zero` surface writes. + +#### (a) cross-lane row maximum / row selection, s26141–s26290 + +``` +s26141 L66950: and.b32 %r32051, %r32048, 7 // laneid&7 +s26142 L66951: shr.u32 %r32052, %r32048, 3 // laneid>>3 +s26143 L66952: and.b32 %r32053, %r32048, 3 +s26145 L66954: selp.b32 %r32054, %r31909, %r31908, %p483 // pick by (laneid&3) +s26161 L66970: bfi.b32 %r32067, %r32051, %r32066, 2, 3 +s26164 L66973: shfl.sync.idx.b32 %r32070|%p487, %r32056, %r32067, %r32068, %r32069 +s26182 L66991: selp.b32 %r438, %r32082, %r32084, %p493 +``` + +Two blocks (s26141–s26216 for the first two 4-value rows, s26217–s26290 for the +other two), each doing: + +1. a `selp` chain over `(laneid&3)` selecting one of four **phase-32 D** + registers (`%r31908/%r31909`, `%r31948/%r31949`, `%r32028/%r32029`, + `%r32038/%r32039`) into four registers; +2. four `shfl.sync.idx.b32` with `srcLane = (laneid&7) | ((((laneid>>3)+d)&3)<<2)` + for `d = 0, 1, 2, -1` (`%r32068 = mov.u32 31`, `%r32069 = mov.u32 -1`); +3. a `selp` chain over `laneid>>3` picking between the four shuffled values. + +Result: `%r438 %r439 %r440 %r441` (and `%r443…%r446`) hold four values per lane; +`%r442`, `%r447`, `%r448` are the corresponding single values of the other two +register sets. + +#### (b) bounds check, s26291–s26306 + +``` +s26291 L67102: mov.u32 %r449, %tid.x +s26296 L67107: sub.s32 %r32174, %r449, %r32173 // tid.x - ((tid.x+round)>>3<<3) +s26298 L67109: add.s32 %r450, %r32174, %r1 // x +s26299 L67110: add.s32 %r451, %r32175, %r7 // y +s26300 L67111: setp.ge.u32 %p515, %r450, %r31837 // x >= ex +s26301 L67112: setp.ge.u32 %p516, %r451, %r31838 // y >= ey +s26306 L67117: @%p519 bra $L__BB1_438 +``` + +Out-of-range lanes jump past (b)…(f). The second pass recomputes with +`tid.x + 32` (s26554: `add.s32 %r32350, %r449, 32`). + +#### (c) softmax, s26307–s26394 + +``` +s26311 L67124: cvt.f32.f16 %f1985, %rs96 +s26312 L67127: mul.ftz.f32 %f2013, %f1985, 0fBFB8AA3B // -log2(e) +s26313 L67128: ex2.approx.ftz.f32 %f2014, %f2013 +s26314 L67129: add.ftz.f32 %f2015, %f2014, 0f3F800000 +s26316 L67131: div.approx.ftz.f32 %f1986, 0f3F800000, %f2015 // sigmoid(%rs96) +s26318 L67137: max.f16x2 %r32176,%r438,%r439 +s26320 L67145: max.f16x2 %r32182,%r32179,%r441 +s26323 L67151: max.f16 %rs9235,%rs9236,%rs9237 +s26324 L67155: max.f16 %rs9238,%rs9235,%rs95 // the real row max +s26326 L67160: sub.f16x2 %r32185,%r438,%r32199 // x - rowmax +s26329 L67168: mul.ftz.f32 %f2017, %f1987, 0f3FB8AA3B // *log2(e) +s26330 L67169: ex2.approx.ftz.f32 %f1989, %f2017 +s26386 L67288: div.approx.ftz.f32 %f2005, 0f3F800000, %f2034 // 1/rowsum +s26389 L67295: mul.f16x2 %r32200,%r32201,%r32214 +``` + +A textbook f32 softmax over the row's four values plus the fifth: `max` via +`max.f16x2`/`max.f16`, `y = 2^((x-max)*log2e)` in f32 +(`cvt.f32.f16 → mul by 0f3FB8AA3B → ex2.approx`), accumulate the row sum in f32, +invert with `div.approx.ftz.f32 1.0/…`, round to f16, multiply the five f16x2 +registers `%r32200 %r32203 %r32206 %r32209 %r32212`. Separately, +`1/(1+2^(-log2e·c))` is built at s26311–s26317 from `%r442` — a sigmoid of the +fifth value, kept in `%rs9234` for the second pass. **This epilogue does have a +real row maximum** (unlike E5), done with four `shfl.sync.idx` per row group. + +#### (d) texture gather and accumulate, s26395–s26471 + +``` +s26397 L67317: selp.b32 %r32324, %r32322, %r32323, %p520 // clamp x +s26412 L67333: tex.base.2d.v4.f16.s32 {%rs9260,…, %rs9263}, [%rd486, {%r32263,%r32232}] +s26414 L67337: tex.base.2d.v4.f16.s32 {%rs9264,…, %rs9267}, [%rd488, {%r32265,%r32232}] +s26444 L67394: mov.b32 %r32252, {%rs9276, %rs9280} +s26445 L67396: fma.rn.f16x2 %r32251,%r32252,%r32206,%r32235 +s26468 L67441: add.f16 %rs9292,%rs9293,%rs9294 +s26473 L67457: fma.rn.f16 %rs9305,%rs9301,%rs9307,%rs9292 +``` + +**Nine** `tex.base.2d.v4.f16.s32` (s26412, s26414, s26431, s26433, s26441, +s26443, s26456, s26458, s26471) at a 2×2-plus-one stencil of the texture at +`param_0+88` (`%rd486 %rd488 %rd490 %rd492 %rd494 %rd496 %rd498 %rd500 %rd502`, +handles built from `[%rd539+8]`), indexed by clamped `(x,y)` neighbourhoods. +The 2×2 blocks are multiplied by the five softmax registers with `fma.rn.f16x2` +and accumulated; the accumulator halves are summed with `add.f16`, then one more +texture value is folded in with `fma.rn.f16` (`* %rs9307`, the 5th weight). + +#### (e) sigmoid, difference, scale, cross-lane sum, s26472–s26552 + +``` +s26476 L67469: cvt.f32.f16 %f2006, %rs97 +s26477 L67472: mul.ftz.f32 %f2035, %f2006, 0fBFB8AA3B +s26478 L67473: ex2.approx.ftz.f32 %f2036, %f2035 +s26479 L67474: add.ftz.f32 %f2037, %f2036, 0f3F800000 +s26480 L67475: div.approx.ftz.f32 %f2007, 0f3F800000, %f2037 // sigmoid +s26488 L67493: mul.f16 %rs9321,%rs9234,%rs9305 +s26492 L67508: mov.f32 %f2012, 0f3E800000 // 0.25 +s26493 L67510: sub.f16 %rs9333,%rs9309,%rs9324 +s26507 L67548: shfl.sync.down.b32 %r32285,%r32281,%r32306,%r32288,%r32069 +s26508 L67552: add.f16x2 %r32290,%r32281,%r32285 +s26513 L67563: shfl.sync.down.b32 %r32294,%r32290,%r32314,%r32297,%r32069 +s26514 L67567: add.f16x2 %r32299,%r32290,%r32294 +s26529 L67606: shfl.sync.down.b32 %r32312,%r32310,%r32314,%r32315,%r32069 +``` + +`sigmoid(v) = 1/(1 + 2^(-log2e·v))`, then three `acc − sigmoid(acc)` differences +scaled by `0.25` (`%f2012`), then a two-step cross-lane sum: `shfl.sync.down` +with the delta operand `%r32306 = 1` (s26504) then `%r32314 = 8` (s26504), each +followed by an `add.f16x2`; the same two steps repeat on the scalar path +(`add.f16` at s26523 and s26532). The width operand is 31, so this is a partial +(not five-step) warp reduction. + +#### (f) surface stores, s26533–s26552 + +``` +s26533 L67618: ld.param.u64 %rd506, [%rd539+40] // param_0+120 +s26534 L67619: ld.param.u64 %rd508, [%rd539+48] // param_0+128 +s26536 L67622: sust.b.2d.v4.b16.zero [%rd504, {%r32320,%r451}], {%rs9330,%rs9333,%rs9336,%rs9365} +s26537 L67625: sust.b.2d.v4.b16.zero [%rd506, {%r32320,%r451}], {%rs9321,%rs9324,%rs9327,%rs9366} +s26538 L67627: and.b32 %r32342, %r452, 1 +s26552 L67643: sust.b.2d.v4.b16.zero [%rd508, {%r32343,%r32344}], {%rs9367,%rs9368,%rs9354,%rs9370} +``` + +Three 4-channel b16 surface writes (`param_0+112`, `+120`, `+128`; `%rd504 = +[%rd539+32]` at s26310); the third is taken only when `(%r452 & 1) != 1` (s26538– +s26542) and stores `0` in its fourth channel (`%rs9370 = mov.u16 0`). + +**Inputs:** phase 32's D, the surface handles and the texture handle from +`param_0+88/+112/+120/+128`, `param_0+0` extents, constants `0fBFB8AA3B`, +`0f3FB8AA3B`, `0f3F800000`, `0f3E800000`. +**Outputs:** none (the kernel returns at s26819). + +--- + +## 4. The destination-buffer writes (`param_0+48` and `param_0+56`) + +There are exactly **three** store groups in the whole entry: + +**(i) E30, 32 × `st.global.u32 [%rd5 + 4*idx], v` — s25247…s25630**, into +`%rd5 = cvta(param_0+48)`. In one line per store, with +`%r5 = ex<<3`, `g = laneid>>2`, `t = laneid&3`: + +``` +idx = %r5*y + 8*x + d, d = t (even store) or t|4 (odd store) +guard: 0 <= y < ey and 0 <= x < ex and (laneid <= 255 or (g+8j) <= 63) +bases: y = %r7 + ((g+8j)>>3), x = %r1 + ((g+8j)&7), j = 0…7 + recomputed at s25260 (+8), s25328 (+16), s25362 (+24), s25430 (+32), + s25464 (+40), s25532 (+48), s25566 (+56); j=0 uses the raw laneid>>5 / g&7 +``` + +| # | statement | value | # | statement | value | +|---|---|---|---|---|---| +| 1 | s25247 | `%r317` | 17 | s25452 | `%r333` | +| 2 | s25256 | `%r318` | 18 | s25460 | `%r334` | +| 3 | s25282 | `%r319` | 19 | s25486 | `%r335` | +| 4 | s25290 | `%r320` | 20 | s25494 | `%r336` | +| 5 | s25299 | `%r321` | 21 | s25503 | `%r337` | +| 6 | s25307 | `%r322` | 22 | s25511 | `%r338` | +| 7 | s25316 | `%r323` | 23 | s25520 | `%r339` | +| 8 | s25324 | `%r324` | 24 | s25528 | `%r340` | +| 9 | s25350 | `%r325` | 25 | s25554 | `%r341` | +| 10 | s25358 | `%r326` | 26 | s25562 | `%r342` | +| 11 | s25384 | `%r327` | 27 | s25588 | `%r343` | +| 12 | s25392 | `%r328` | 28 | s25596 | `%r344` | +| 13 | s25401 | `%r329` | 29 | s25605 | `%r345` | +| 14 | s25409 | `%r330` | 30 | s25613 | `%r346` | +| 15 | s25418 | `%r331` | 31 | s25622 | `%r347` | +| 16 | s25426 | `%r332` | 32 | s25630 | `%r348` | + +Which of the eight bases each individual store uses is not determined by the PTX +alone — see §6 U6. + +**(ii) E31, 12 stores to `param_0+56`** — s25995 (`v2.u16` of `%rs9209/%rs9210`), +s26004, s26031, s26039, s26048, s26056, s26065, s26073, s26082, s26090, s26099 +(`u32` of `%r400…%r409`), s26107 (`v2.u16` of `%rs9231/%rs9232`). See §3/E31 for +the indices. + +**(iii) E32, 6 × `sust.b.2d.v4.b16.zero`** to `param_0+112/+120/+128` +(s26536, s26537, s26552 and their second-pass copies s26801, s26802, s26817). + +**What is written to `param_0+48`:** phase 30's requantised 64×64 output — 32 b32 +per lane, one per store — i.e. 4 bytes × 32 lanes × 32 stores = 4096 bytes per +block. **Nothing inside this kernel reads `param_0+48` back**: the only read of +that offset are the `ld.param.u64 [%rd1+-32]` at s25221 that *creates* the base +pointer. + +## 5. Cross-lane reductions of the merge + +The merge's "shfl reductions" are the **sixteen `shfl.sync.down/up` pairs of +E30(c), s25644–s25705**. Each pair uses delta operand 4 (PTX `b`), group/width +operand 31 (`.down`) or 0 (`.up`), and `laneid & 4` as the selection predicate, +so each of the 32 payloads is re-paired between lanes 0-3 and 4-7 of every +`laneid&7` group before it becomes phase 31's A operand. + +There is a *second*, unrelated cross-lane reduction family: +* E5/E12's 16 `shfl.sync.bfly` (lane bits 0 and 1) for the softmax row sums; +* E14's 16 `shfl.sync.bfly` for the RMS sums; +* E32's four `shfl.sync.idx` per row group (row maximum) and its + `shfl.sync.down` pairs at delta 1 and 8 after the sigmoid. + +## 6. Uncharacterised + +**U1. The identity of the 12288-byte score bias.** Both score phases add a +12288-byte f16 table as their GEMM C operand (P5: `W+4224…W+16512`, P12: +`W+22656…W+34848`), indexed as §3/E4 describes. Whether it is a relative +position bias, a learned score bias, or a per-lane constant cannot be decided +from the PTX: it is an opaque blob in a permuted weight image. *Missing:* the +weight image's layout description (the `_prep` permutation) or the parameter +names from the model file. + +**U2. Why phase 5's two operands are the same projection.** E4 packs phase 3's +D into *both* phase 5's A and its B (fragment-permuted), and phase 4's D becomes +the transposed V of phase 6. So `scores = pack(D3)·pack(D3)ᵀ`. The PTX proves +the arithmetic; it does not say which of D3/D4 is "Q", "K" or "V" in the model. +*Missing:* the high-level source or the model's projection names. + +**U3. The identity of the per-column tables and biases.** `W+36992…37104` (E6), +`W+37120…37232` (E14, used as the norm gain), `W+41408…41520` (E15), and the +per-column biases at `+39296/+43584/+47744/+51904/+56064/+60224/+64384/+68544` +are all read with the same `W + ((laneid<<2)&12) + off` pattern and are 16 f16 +per lane (32 columns). Their role is *computable* (E6: added to the input +residual before phase 7; E14: multiplies the inverse std; E15: added after the +input tile) but their *names* are not. The biases at `+95232…95408` and +`+96448/+96464` are the same case. + +**U4. The exact purpose of phase 32's texture reads.** Nine +`tex.base.2d.v4.f16.s32` per pass fetch a 2×2-plus-one stencil through handles +built from `param_0+88`; the arithmetic is §3/E32(d)–(e), but which input surface +that handle is and what model term `(acc − sigmoid(acc))·0.25` corresponds to is +not decidable from the PTX. Note that enc0's equivalent epilogue reads a +*shared* array (`input_noise`) instead, so enc1 and enc0 differ here. *Missing:* +the high-level source (a `shrink`/`gate`/`residual` term) or a reference +implementation. + +**U5. The geometry the spec reports for the band phases.** `rr_layer_spec.py` +prints `M=192 N=96 K=96` for phases 6 and 13 and `M=128 N=64 K=64` for phases +15…29; §2.1 shows the true shapes are `64×32×96` and `64×32×64`. The tool's +`band` grid marker comes from the address pattern, not from the chain; I could +not find a rule that recovers `k_steps` from the tool's own data, so the table in +§2.1 was derived by walking each phase's `D → C` chain by hand. The epilogue +contracts above do not depend on the tool's numbers. + +**U6. E30's base-to-store assignment.** The 32 stores write `%r317…%r348` in +order and there are eight `(g+8j)` bases (recomputed at s25260, s25328, s25362, +s25430, s25464, s25532, s25566 plus the prologue's raw `g`), but the PTX does +not pair them one-to-one: between two consecutive recomputations there are +sometimes two and sometimes six stores, and the guard predicates used inside one +such run alternate between the run's own predicate and an earlier one (e.g. +`s25282/s25290` use `%p2` while `s25299/s25307` use `%p1`). I could not +determine whether the six-store runs cover a second base or merely re-store the +same addresses. *Missing:* a run of the kernel with a `param_0+48` buffer dump, +or the corresponding high-level code. + +**U7. Why `%r442`/`%r447` differ from `%r438…%r441`.** In E32 the first +`selp`+`shfl` block produces `%r438…%r441` from `%r31908/%r31909/%r31948/%r31949` +and `%r442…` from `%r31918/%r31919/%r31958/%r31959`, i.e. two disjoint sets of +phase-32 D registers. The softmax uses the first set and a sigmoid a member of +the second; the PTX does not say why. *Missing:* the high-level source. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| phase table with M/N/K checked | §2.1 (twelve rows differ from the tool's numbers, all explained) | +| weight image extent | §2.2 — ≥ 96480 bytes (tool says 96468; the per-lane table base adds 12) | +| phases with no weight operand | §2.3 — 6 and 13 read none; 5 and 12 read only a C bias | +| E5 row max / exp / row sum / reciprocal | §3/E5(a)–(e); **no row max**; the exponent is a cubic-with-6-bit-mantissa, not `exp2` | +| P5 score bias | §3/E4 — 24 × `ld.weak.global.ca.v4.u32` at `W+4224+512*i`, used as the GEMM C operand, *not* in the epilogue | +| P6 `P·V`, the transposes | §3/E5(f) (48 `movmatrix`, s12185–s12232) + E6 | +| second window P8–P14 | §3/E8–E13 | +| the RMS norm | §3/E14 — sum of squares + 2⁻¹³, `rsqrt`, ·gain, **no mean, no 1/N, no bias** | +| the activation | §3/E15/E17/… — clamped cubic `x·(0.5 + y·(0.412109375 − 0.0810546875|y|))`, `y = clamp(x,±2)` | +| the eight bottleneck residual blocks | §3/E15…E30 ("Shape of the whole MLP region") | +| patch merge / destination-buffer writes | §4(i) — 32 stores at `param_0+48`; §4(ii) — 12 at `param_0+56` | +| final epilogue | §3/E32 — row max, f32 softmax, 9 texture reads, surface stores | +| plane-arena table generated per launch | §4 — the buffer at `param_0+48` is write-only inside this kernel (see §3/E30(b)) | diff --git a/kernels/rr/rrswin_enc2.hip b/kernels/rr/rrswin_enc2.hip new file mode 100644 index 0000000..b63d85f --- /dev/null +++ b/kernels/rr/rrswin_enc2.hip @@ -0,0 +1,540 @@ +// Native replacement for the Ray Reconstruction denoiser's third Swin encoder, +// cuda_dldn_engine_swin_enc2_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the mirror cut is in place and phases 1-7 are implemented and bit-exact +// against the debug oracle (see "Ground truth" below): each stage's payload region +// compares byte for byte, 0 differing f16 halves out of the whole payload. Phases +// 8-38 (the attention output projection, the MLP band and the patch merge) are not +// ported yet, so the five accumulators the epilogue reads are still filled with +// lane-distinct placeholders; the read-back path is exercised, the layer's output is +// not yet correct. +// +// The cut hands over phase 1's staged A fragments, its B fragments, its zero C seed, +// the weight image, the parameter block and the base of the entry's own `.shared` +// tile, which the body reuses: the A fragments of phases 3 and 5 are read back out +// of it, phase 7's keys are published through it (32 lanes x 24 words), and the five +// live-out accumulators cross the cut through it. +// +// --------------------------------------------------------------------------- +// The kernel is one warp per 8x8 token patch, four waves deep in z: grid (161, 93, 1), +// block (32, 1, 4), parameter block 144 bytes. The PTX this file replaces is +// ~/.cache/d4r-rr-corpus/0015-PREPASS_ENTRYPOINT_NAME.ptx, statements s4621-s13876 +// (file lines 7669-33949): the 630 mma of 38 phases. +// +// kernels/rr/swin_enc2_recipe.py owns the splice (kernels/tex/make_ptx.py loads it for +// cuda_dldn_engine_swin_enc2_kernel), so NVIDIA's texture prologue (s1-s4620) and its +// surface epilogue (s13877-end, the staged softmax window, the 3x3 texture gather and +// the three surface writes) stay PTX and the region above becomes one call.uni. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the raw +// image is kept and read through a typed accessor. +struct DldnSwinEnc2Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinEnc2Params) == 144, "parameter block"); + +enum : int +{ + kExtents = 0, // (ex, ey) v2.u32 + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // plane arena pointer (arg048), read by the debug store only + kOutArg = 56, // phase 37's output buffer (arg056) + kOrigins = 80, // patch origins v2.u16 (rs126, rs127) +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// The implemented phases, as byte offsets into arg040. Every offset is relative to +// the slab pointer Wz = W + 21504*tid.z + 16*laneid that the entry builds at s4613, +// which is what phases 1..7 index through (rrswin_enc2_epilogues.md, section 1.1): +// P1 weights 192 P4 weights 4288 +// P2 weights 3264 P5 weights 2240 +// P3 weights 1216 P6 weights 5312 +// P7 no weights (A and B are packs of phase 5's D), C = the score bias at 6336 +// +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through ZLUDA's +// exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (inverted from the hardware fragment layout: a lane's 16-byte chunk holds the eight +// k = 8*h + 2t + (j&1) + 16*((j>>1)&1) of its own t, for the columns 16*tt + 8*f + g; +// the mma hands column n out of lane n, so the native side reads n = 8*nt + 2t + c +// straight from the image instead.) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// One GEMM: six m-tiles of 16 rows x four n-tiles of eight columns, K=32, f16 out. +// +// A lane's A registers hold, for each m-tile and each of its two rows, the eight e4m3 +// values of k = 8*reg + 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3 of register +// 2*reg + row); the four lanes that differ in t hold the four disjoint eighths of the +// 32 k's, so two butterfly steps broadcast the other three eighths in. The B operand +// is read from the weight image (waddr) for the lane's own two columns of each n-tile. +// The dot product runs in f32 and is rounded to f16 once, which is what the translated +// mma does: e4m3 x e4m3 products are exact and 32 of them sum exactly in f32. +// +// `cprev` is the C operand as a [m-tile][row half][n-tile] array of packed pairs -- +// phase 1 and phase 2 start from zero (%r8606), phases 3..6 accumulate onto phase 1's, +// 2's, 3's and 4's accumulators. d is [m-tile][row half][n-tile]. +DEVF void gemm_k32(const uint32_t* as, const uint8_t* w, int base, const uint32_t* cprev, + int nmi, int t, uint32_t d[6][2][4]) +{ + for (int nt = 0; nt < 4; ++nt) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + for (int mi = 0; mi < nmi; ++mi) { + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + uint32_t p[4]; + p[0] = as[4 * mi + 2 * reg + row]; + p[1] = bfly1_bits(p[0]); + p[2] = bfly2_bits(p[0]); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + const uint32_t seed = cprev != nullptr ? cprev[(2 * mi + row) * 4 + nt] : 0u; + d[mi][row][nt] = pair_of((half_t)(acc[row][0] + h2f(seed)), + (half_t)(acc[row][1] + h2f(seed >> 16))); + } + } + } +} + +// out[i][m]: word i as lane t^m holds it, which is what the mma pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + +// the 32-term dot product of two packed operand word pairs, in the mma's own k order +DEVF float dot32(const uint32_t a[2][4], const uint32_t b[2][4]) +{ + float acc = 0.0f; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + acc += e4m3_to_f32((a[i][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((b[i][m] >> (8 * j)) & 0xffu); + } + } + } + return acc; +} + +// --------------------------------------------------------------------------- +// A [6][2][4] block of packed f16 pairs, and the e4m3 words E6 packs out of it. +// +// A D register d[mi][row][nt] holds row 16*mi + 8*row + g, columns 8*nt + 2t and +// 8*nt + 2t+1. The two e4m3 words the PTX builds for that row are +// w[0] = {pack(columns 2t, 2t+1), pack(columns 16+2t, 16+2t+1)} +// w[1] = {pack(columns 8+2t, 8+2t+1), pack(columns 24+2t, 24+2t+1)} +// i.e. exactly the hardware's A register for the k-halves 0 and 1, so w[h] is both an +// A register (row r) and a B fragment (row r) -- which is what E6 exploits: phase 7's +// A fragment m is {w0(16m+g), w0(16m+g+8), w1(16m+g), w1(16m+g+8)} and its B fragment +// n-tile is {w0(8n+g), w1(8n+g)} (VERIFIED against the oracle's e6a/e6b stages). +DEVF half_t dcell(const uint32_t d[6][2][4], int row, int col) +{ + const uint32_t p = d[row >> 4][(row >> 3) & 1][col >> 3]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +DEVF void row_words(const uint32_t d[6][2][4], int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_enc2_recipe.py: with +// D4R_RRSWIN_DEBUG= the same splice keeps NVIDIA's whole body and stores that +// stage's registers into the plane arena at +4,000,000, which the kernel never +// otherwise writes, and the launch dump then holds the translated values for a +// block/lane. Built with -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, +// D4R_TEX_CFLAGS), this body stores the same registers of its own phase n in the same +// order, so the two dumps compare byte for byte. The base is 4,000,000 rather than the +// family default of 46,000,000 because enc2's arg048 sits at allocation offset +// 30,146,560 of a 65,945,600-byte allocation, which the bridge dumps under arg008. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 41u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + // the block is four waves deep in z and every plane reads a different weight slab + // (the 21504-byte stride), so only plane 0 may write the slot + if (__builtin_amdgcn_workitem_id_z() != 0u) { + return; + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot, the recipe's _debug_block: 32 lanes x n x 4 bytes, at least + // 8192, rounded up to a power of two (its splice forms block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + 4000000ull + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// stage registers in the oracle's order: 24 mma, m-tile major, n-tile minor, each as +// the (row g, row g+8) pair the mma writes +DEVF void stage_regs(const uint32_t d[6][2][4], uint32_t regs[48]) +{ + int i = 0; + for (int mi = 0; mi < 6; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. Phase 1's six staged A fragments arrive in this order (the first mma's +// operand order, .f16.e4m3 fragments of 4 b32 each): +// f0 %r16120 %r16121 %r16122 %r16123 f3 %r16156 %r16157 %r16158 %r16159 +// f1 %r16132 %r16133 %r16134 %r16135 f4 %r16168 %r16169 %r16170 %r16171 +// f2 %r16144 %r16145 %r16146 %r16147 f5 %r16180 %r16181 %r16182 %r16183 +// then phase 1's four B fragments (%r3251 %r3252 %r3253 %r3254 %r3255 %r3256 %r3257 +// %r3258, read from Wz+192 and Wz+704), its zero C seed (%r8606), the weight image and +// the parameter block. +// +// The entry's own `.shared` tile holds the eighteen A fragments at +// `smem + 512*(3*m-tile + slice) + 16*laneid`, three K=32 slices of the 96x96 input +// patch that the six z-planes wrote cooperatively (s4520-s4590); the body reads all +// three back rather than taking slices 1 and 2 over the cut. It is otherwise dead +// inside the region, and E38 re-stages its own window into it after the cut. +extern "C" __attribute__((device)) void d4r_swin_enc2( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, + uint32_t a6, uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, + uint32_t a12, uint32_t a13, uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, + uint32_t a18, uint32_t a19, uint32_t a20, uint32_t a21, uint32_t a22, uint32_t a23, + uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3, uint32_t b4, uint32_t b5, + uint32_t b6, uint32_t b7, uint32_t c0, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[24] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23}; + (void)c0; + const uint32_t lane = lane_id(); + const int t = (int)(lane & 3); // the lane's two columns of each n-tile + const int g = (int)(lane >> 2); // ... and of its sixteen rows + const uint32_t tz = __builtin_amdgcn_workitem_id_z(); + // Wz: the slab pointer phases 1..7 index through (s4589-s4590, s4613-s4615) + const uint8_t* const wz = w + 21504u * tz + 16u * lane; + lds_u32* const sm = (lds_u32*)(uintptr_t)scratch; + + // ---- the three K=32 slices of the staged 96x96 input patch -------------- + // as[s] is slice s's six A fragments, m-tile major, in the order the entry reads + // them: fragment m of slice s at 512*(3*m + s) + 16*laneid. + uint32_t as[3][24]; +#pragma unroll + for (int q = 0; q < 18; ++q) { + const int s = q % 3; + const int mi = q / 3; + as[s][4 * mi + 0] = sm[128 * q + 4 * lane + 0]; + as[s][4 * mi + 1] = sm[128 * q + 4 * lane + 1]; + as[s][4 * mi + 2] = sm[128 * q + 4 * lane + 2]; + as[s][4 * mi + 3] = sm[128 * q + 4 * lane + 3]; + } +#if D4R_RRSWIN_DEBUG_STAGE == 90 + { + uint32_t regs[72]; +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { + for (int s = 0; s < 3; ++s) { + regs[12 * mi + 4 * s + 0] = as[s][4 * mi + 0]; + regs[12 * mi + 4 * s + 1] = as[s][4 * mi + 1]; + regs[12 * mi + 4 * s + 2] = as[s][4 * mi + 2]; + regs[12 * mi + 4 * s + 3] = as[s][4 * mi + 3]; + } + } + debug_store(prm, regs, 72); + } +#endif + + // ---- phases 1-6: the 96x96 -> 96x32 residual projection ------------------ + // K=32 and N=32 throughout: two K-slices are paired per input slice, each phase + // accumulates onto the phase two before it that shares its A fragment (s4621-s4799). + uint32_t zero[6][2][4] = {}; + uint32_t d1[6][2][4], d2[6][2][4], d3[6][2][4], d4[6][2][4], d5[6][2][4], d6[6][2][4]; + gemm_k32(as1, wz, 192, &zero[0][0][0], 6, t, d1); +#if D4R_RRSWIN_DEBUG_STAGE == 1 + { + uint32_t regs[48]; + stage_regs(d1, regs); + debug_store(prm, regs, 48); + } +#endif + gemm_k32(&as[0][0], wz, 3264, &zero[0][0][0], 6, t, d2); +#if D4R_RRSWIN_DEBUG_STAGE == 2 + { + uint32_t regs[48]; + stage_regs(d2, regs); + debug_store(prm, regs, 48); + } +#endif + gemm_k32(&as[1][0], wz, 1216, &d1[0][0][0], 6, t, d3); +#if D4R_RRSWIN_DEBUG_STAGE == 3 + { + uint32_t regs[48]; + stage_regs(d3, regs); + debug_store(prm, regs, 48); + } +#endif + gemm_k32(&as[1][0], wz, 4288, &d2[0][0][0], 6, t, d4); +#if D4R_RRSWIN_DEBUG_STAGE == 4 + { + uint32_t regs[48]; + stage_regs(d4, regs); + debug_store(prm, regs, 48); + } +#endif + gemm_k32(&as[2][0], wz, 2240, &d3[0][0][0], 6, t, d5); +#if D4R_RRSWIN_DEBUG_STAGE == 5 + { + uint32_t regs[48]; + stage_regs(d5, regs); + debug_store(prm, regs, 48); + } +#endif + gemm_k32(&as[2][0], wz, 5312, &d4[0][0][0], 6, t, d6); +#if D4R_RRSWIN_DEBUG_STAGE == 6 + { + uint32_t regs[48]; + stage_regs(d6, regs); + debug_store(prm, regs, 48); + } +#endif + + // ---- E6(b) and phase 7: the 64x96 attention score ----------------------- + // Both operands of the score GEMM are packs of phase 5's D: the four A fragments + // are m-tiles 0..3 (rows 0..63, the queries) and the twelve B fragments are its + // twelve n-tiles read as rows (rows 0..95, the keys) -- the score multiplies one + // projection by its own transpose. The A side needs only the lane's own rows, but + // the mma hands column n out of lane n, so the B fragments go through the shared + // tile: 32 lanes x 24 words at 1024, the first 3 KB of a tile nothing else in the + // region touches. + uint32_t as7[16]; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + uint32_t w0[2], w8[2]; + row_words(d5, 16 * mi + g, w0); + row_words(d5, 16 * mi + g + 8, w8); + as7[4 * mi + 0] = w0[0]; + as7[4 * mi + 1] = w8[0]; + as7[4 * mi + 2] = w0[1]; + as7[4 * mi + 3] = w8[1]; + } + uint32_t bf[12][2]; +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + row_words(d5, 8 * nt + g, bf[nt]); + } + { + lds_u32* const keys = sm + 256; // 1024 bytes, 24 words per lane +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + keys[24 * lane + 2 * nt + 0] = bf[nt][0]; + keys[24 * lane + 2 * nt + 1] = bf[nt][1]; + } + } + __builtin_amdgcn_wave_barrier(); +#if D4R_RRSWIN_DEBUG_STAGE == 92 + { + uint32_t regs[24]; +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + regs[2 * nt + 0] = bf[nt][0]; + regs[2 * nt + 1] = bf[nt][1]; + } + debug_store(prm, regs, 24); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 91 + { + debug_store(prm, as7, 16); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 93 + { + // the 96 C seeds: phase 7's additive 64x96 f16 score bias, one value per + // score element, 512 bytes per output tile, tile 4*(nt>>1) + m-tile + uint32_t regs[96]; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 12; ++nt) { + const uint8_t* p = wz + 6336 + 512u * (4u * (uint32_t)(nt >> 1) + (uint32_t)mi) + + 16u * lane + 8u * (uint32_t)(nt & 1); + regs[2 * (mi * 12 + nt) + 0] = *(const uint32_t*)p; + regs[2 * (mi * 12 + nt) + 1] = *(const uint32_t*)(p + 4); + } + } + debug_store(prm, regs, 96); + } +#endif + uint32_t d7[4][2][12]; + { + const lds_u32* const keys = sm + 256; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + for (int rh = 0; rh < 2; ++rh) { + uint32_t aw[2], a[2][4]; + row_words(d5, 16 * mi + 8 * rh + g, aw); + bfly2x4(aw, a); + for (int nt = 0; nt < 12; ++nt) { + const uint32_t bias = *(const uint32_t*)(wz + 6336 + + 512u * (4u * (uint32_t)(nt >> 1) + (uint32_t)mi) + + 16u * lane + 8u * (uint32_t)(nt & 1)); + float s[2] = {0.0f, 0.0f}; + for (int c = 0; c < 2; ++c) { + // the fragment of n = 8*nt + 2t + c lives in the four lanes of + // row group 2t+c; A's byte j on lane t^m pairs with B's byte j + // on lane 2t+c, t^m + uint32_t kb[2][4]; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { + kb[i][m] = keys[24 * (4 * (2 * t + c) + (t ^ m)) + 2 * nt + i]; + } + } + s[c] = dot32(a, kb); + } + d7[mi][rh][nt] = pair_of((half_t)(s[0] + h2f(bias)), + (half_t)(s[1] + h2f(bias >> 16))); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 7 + { + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 12; ++nt) { + regs[i++] = d7[mi][0][nt]; + regs[i++] = d7[mi][1][nt]; + } + } + debug_store(prm, regs, 96); + } +#endif + + // ---- handing the accumulators back ------------------------------------ + // %r16472 is param_0[0] (ld.param.v2.u32 at s13138) and %r17746 = 16*tid.z (s13139), + // both computed inside the region; %r17758 is &smem (s13852); %r17496/%r17506 are + // phase 38's accumulator pairs. Phases 8-38 are not ported yet, so the two mma + // pairs are filled with lane-distinct values: that keeps the read-back path + // observable (E38's surface output changes from the unported baseline) without + // producing wild magnitudes. + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + + 5 * (uint32_t)lane_id(); + out[0] = *(const uint32_t*)prm; // ex + out[1] = lane + 32u; // %r17496 + out[2] = lane + 64u; // %r17506 + out[3] = tz << 5; // %r17746 = 16*tid.z + out[4] = scratch; // %r17758 = &smem +} diff --git a/kernels/rr/rrswin_enc2_epilogues.md b/kernels/rr/rrswin_enc2_epilogues.md new file mode 100644 index 0000000..93ab126 --- /dev/null +++ b/kernels/rr/rrswin_enc2_epilogues.md @@ -0,0 +1,1513 @@ +# `cuda_dldn_engine_swin_enc2_kernel` — the epilogues of phases 1…38 + +Companion to `kernels/rr/rr_layer_spec.py enc2`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0015-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc2_kernel` (14199 statements, file lines 1018–34562). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. The phase table (`rr_layer_spec.py enc2`) gives the + ranges; this file names what each one *computes*. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_enc2_kernel_param_0+40]` (s8), `cvta.to.global.u64 %rd3, + %rd2` (s9). Every `ld.weak.global.ca.v4.u32` in an epilogue reads + `W + 16*laneid + imm`; every `ld.global.v2.u16` / `ld.global.u32` table load + reads `W + ((laneid<<2)&12) + imm`. +* `Wz` denotes the **per-`%tid.z` weight slab**: `%rd269 = %rd2 + 2*(%tid.z * + 10752) + 16*laneid` (s4589–s4590, s4613–s4615) = `W + 21504*%tid.z + + 16*laneid`. Phases 1…7 add offsets to *this* pointer; phases 9…36 add them to + `W + 16*laneid` directly (s8976–s8978); phase 37 to `W + 12288*%tid.z + + 16*laneid` (s13634–s13639). Every byte offset in the phase table is relative + to the pointer named here, so the phase-table numbers do **not** include the + `%tid.z` term. See §6 U5. +* `S` denotes the plane arena: `ld.param.u64 %rd383, [%rd1+-32]` (s12865) with + `%rd1 = param_0 + 80` (s4) → **`param_0+48`**, then `cvta.to.global.u64 %rd5, + %rd383` (s12866). `I` denotes the input image: `ld.param.u64 %rd10, + [param_0+8]` (s17) → `%rd4` (s18). `O` denotes the epilogue-37 destination: + `ld.param.u64 %rd6, [%rd492+56]` (s13632) → **`param_0+56`**. +* The mma fragment layouts and the weight-addressing formula are the settled ones + (see `rr_layer_spec.py --help` and the enc0 companion): C/D `reg0 = (row g, + cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, `g = laneid>>2`, `t = laneid&3`. +* **Geometry.** Writing `m = M/16`, `n = N/8`, `k = K/32` for a phase, the mma + chain fixes the three exactly: `|A fragments| = m*k`, `|B fragments| = n*k`, + accumulator chains (maximal C←D dataflow runs) `= m*n`, each of length `k`, and + `mma = m*n*k`. `rr_layer_spec.py` prints `M = 16*|A fragments|` and + `N = 8*|B fragments|`, i.e. it omits the division by `k`, so its M and N + columns are too large by a factor `K/32` whenever a phase makes more than one + k32 step. Every row is re-derived from the chain in §2. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image) | `ld.param.u64 %rd2, [param_0+40]` / `cvta.to.global.u64 %rd3, %rd2` | s8 / s9 | +| `Wz = W + 21504*%tid.z + 16*laneid` | `mul.lo.s32 %r16116, %r10, 10752` (`%r10 = %tid.z`, s22), `mul.wide.u32 %rd266, %r16116, 2`, `add.s64 %rd268, %rd2, %rd266`, `add.s64 %rd269, %rd268, %rd267` (`%rd267 = 16*laneid`) | s4589–s4590, s4613–s4615 | +| `I` = input image | `ld.param.u64 %rd10, [param_0+8]` / `cvta.to.global.u64 %rd4, %rd10` | s17–s18 | +| `S` = plane arena (`param_0+48`) | `add.s64 %rd1, %rd8, 80` (`%rd8 = param_0`, s1), `ld.param.u64 %rd383, [%rd1+-32]`, `cvta.to.global.u64 %rd5, %rd383` | s4, s12865–s12866 | +| `O` = `param_0+56` | `ld.param.u64 %rd6, [%rd492+56]` (`%rd492 = param_0`, s12803) | s13632 | +| `T` = texture (`param_0+88`) | `ld.param.u64 %rd480, [%rd491+88]` (`%rd491 = param_0`, s13941) | s13941, s14056 | +| surfaces | `ld.param.u64 [%rd491+112]` (s13953), `[+120]` (s14178), `[+128]` (s14179) | s13953, s14178–s14179 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r322, %r323}, [param_0+0]` | s14 | +| block origins | `sub.s32 %r1, %r317, %r318` (`%r317 = 8*ctaid.x`) and `sub.s32 %r2, %r321, %r319` (`%r321 = 8*ctaid.y`) | s3–s7, s11–s13 | +| patch origin offsets | `ld.param.v2.u16 {%rs126, %rs127}, [param_0+80]` | s5 | +| `%r5 = 8*ex`, `%r6 = ey*(8*ex)` | `shl.b32 %r5, %r322, 3`, `mul.lo.s32 %r6, %r323, %r5` | s15–s16 | +| `g = laneid>>2`, `t = laneid&3` | `shr.u32 %r8, %r315, 2`, `and.b32 %r9, %r315, 3` | s20–s21 | +| `%r182 = %r2 + 2*%tid.z` | `shl.b32 %r181, %r10, 1`, `add.s32 %r182, %r2, %r181` | s9184–s9185 | +| `%r17795 = %tid.z<<5` | `mov.u32 %r17745, %tid.z`, `shl.b32 %r17795, %r17745, 5` | s13135, s13139 | + +The three scalar-table forms matter and are used throughout: + +* `ld.weak.global.ca.v4.u32` at `ptr + 512*i` reads one **N-tile of a K=32 slice** + = 16 bytes/lane = 2 B fragments or 2 C pairs (the tool's own comment, + `rr_layer_spec.py:189–192`). +* `ld.global.v2.u16` at `W + ((laneid<<2)&12) + off` reads 4 bytes/lane, the four + lanes with equal `laneid&3` reading the same word, so a run of such loads at + 16-byte stride is one **per-column** vector (a 96-element f16 table is 12 such + loads: 12 × 4 bytes × 4 distinct lane offsets = 192 bytes). +* `ld.global.u32` at the same addressing reads one word = 2 f16 = one per-column + bias pair, used **in both halves** of an mma C operand, i.e. replicated across + the 16 rows of the tile (s9820 `{%r9477, %r9477}`, s13871 `{%r17465, %r17465}`). + +### 1.2 Constants that survive between epilogues + +| register | first definition | f32/f64 literal | value used (after the `cvt`) | read by | +|---|---|---|---|---| +| `%f476` | s5020 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 | E7 | +| `%fd383` | s5024 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | f16 `0xB873` = −0.55615234375 | E7 | +| `%fd385` | s5029 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | f16 `0x3873` = +0.55615234375 | E7 | +| `%f478` | s5035 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | f16 `0x3B6B` = 0.92724609375 | E7 | +| `%f480` | s5040 `mov.f32 %f480, 0f3FB00000` | 1.375 | f16 `0x3D80` = 1.375 | E7 | +| `%f861` | s9833 `mov.f32 %f861, 0f3ED306EB` | 0.4121621549129486 | f16 `0x3698` = 0.412109375 | E13…E35 | +| `%f862` | s9836 `mov.f32 %f862, 0f3DA60DD6` | 0.0810810774564743 | f16 `0x2D30` = 0.0810546875 | E13…E35 | +| `%f863` | s9839 `mov.f32 %f863, 0f3F000000` | 0.5 | f16 `0x3800` = 0.5 | E13…E35 | +| `%f864` | s9842 `mov.f32 %f864, 0f40000000` | 2.0 | f16 `0x4000` = 2.0 | E13…E35 | +| `%fd1` | s3662 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | f16 `0x0800` = 0.0001220703125 | prologue, E12 | + +`%f861…%f864` are defined **inside E13** (s9833–s9842) and re-read by the `cvt` +of every later 164-statement epilogue (E15 s10174–s10181, E17 s10422–…, and so +on to E35), so those epilogues contain `cvt.rn.f16.f32` but only 2 `mov.u32`. + +Also live across the region: `%r3037 = 1` (s3318), `%r3046 = 2` (s3611), +`%r3048 = −1` (s3604) — the delta / segmask / membermask operands of every +`shfl.sync.bfly.b32`; and `%r8606 = 0` (s4616), the zero C operand of phases 1, +2 and 8. + +### 1.3 Two quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — the *other* direction (f16x2 → e4m3x2), used only in + the prologue to quantise the input patch (s3320 ff.). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as `cvt.f32.f16 → op → cvt.rn.f16.f32` + (round each step through f16). + +## 2. Summary + +### 2.1 The 38 epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1 | s4645–s4651 | 7 | phase 2 B weight loads | +| E2 | s4676–s4682 | 7 | phase 3 B weight loads | +| E3 | s4707–s4713 | 7 | phase 4 B weight loads | +| E4 | s4738–s4744 | 7 | phase 5 B weight loads | +| E5 | s4769–s4775 | 7 | phase 6 B weight loads | +| E6 | s4800–s4970 | 171 | score-bias C-seed loads + packs of phase-5/6 D → phase 7 A and B | +| E7 | s5019–s8861 | 3843 | softmax of the 64×96 score, V transpose, packs → phase 8 A and B | +| E8 | s8910–s9078 | 169 | phase-8 D → shared, phase 9 A read, phase 9 B loads, per-column table add → phase 9 C | +| E9 | s9091–s9109 | 19 | phase 10 A from shared + phase 10 B loads | +| E10 | s9122–s9140 | 19 | phase 11 A from shared + phase 11 B loads | +| E11 | s9153–s9171 | 19 | phase 12 A from shared + phase 12 B loads | +| E12 | s9184–s9819 | 636 | RMS norm of phase-12 D + gain, packs; phase 13 A/C and phase 15 B | +| E13 | s9832–s10088 | 257 | clamped cubic on phase-13 D + packs; residual+table → phase 14 C; phase 14 B | +| E14 | s10101–s10160 | 60 | phase 15 B + C loads; 24 packs of the normed tile → phase 15 A | +| E15 | s10173–s10336 | 164 | clamped cubic on phase-15 D + packs; phase 16 B | +| E16 | s10349–s10408 | 60 | phase 17 B + C loads; packs of the normed tile → phase 17 A | +| E17 | s10421–s10584 | 164 | clamped cubic on phase-17 D + packs; phase 18 B | +| E18 | s10597–s10656 | 60 | phase 19 B + C loads; packs of the normed tile → phase 19 A | +| E19 | s10669–s10832 | 164 | clamped cubic on phase-19 D + packs; phase 20 B | +| E20 | s10845–s10904 | 60 | phase 21 B + C loads; packs of the normed tile → phase 21 A | +| E21 | s10917–s11080 | 164 | clamped cubic on phase-21 D + packs; phase 22 B | +| E22 | s11093–s11152 | 60 | phase 23 B + C loads; packs of the normed tile → phase 23 A | +| E23 | s11165–s11328 | 164 | clamped cubic on phase-23 D + packs; phase 24 B | +| E24 | s11341–s11400 | 60 | phase 25 B + C loads; packs of the normed tile → phase 25 A | +| E25 | s11413–s11576 | 164 | clamped cubic on phase-25 D + packs; phase 26 B | +| E26 | s11589–s11648 | 60 | phase 27 B + C loads; packs of the normed tile → phase 27 A | +| E27 | s11661–s11824 | 164 | clamped cubic on phase-27 D + packs; phase 28 B | +| E28 | s11837–s11896 | 60 | phase 29 B + C loads; packs of the normed tile → phase 29 A | +| E29 | s11909–s12072 | 164 | clamped cubic on phase-29 D + packs; phase 30 B | +| E30 | s12085–s12144 | 60 | phase 31 B + C loads; packs of the normed tile → phase 31 A | +| E31 | s12157–s12320 | 164 | clamped cubic on phase-31 D + packs; phase 32 B | +| E32 | s12333–s12392 | 60 | phase 33 B + C loads; packs of the normed tile → phase 33 A | +| E33 | s12405–s12568 | 164 | clamped cubic on phase-33 D + packs; phase 34 B | +| E34 | s12581–s12640 | 60 | phase 35 B + C loads; packs of the normed tile → phase 35 A | +| E35 | s12653–s12816 | 164 | clamped cubic on phase-35 D + packs; phase 36 B | +| E36 | s12829–s13698 | 870 | pack phase-36 D → arena scatter + shared staging; phase 37 A/B/C | +| E37 | s13747–s13870 | 124 | pack phase-37 D → 4 stores to `param+56`; phase 38 B/C | +| E38 | s13877–s14199 | 323 | shared staging, real row max, softmax, 9 texture reads, 3×3 gather, sigmoid/0.25/lane sum, 3 surface writes | + +### 2.2 Phase geometry re-derived from the mma chain + +`|A|` and `|B|` are the distinct A-quad and B-pair counts; +`chains`/`len` come from the C←D dataflow runs; `mma` is the emitted count. +`spec` is the phase table's (`M`, `N`, `K`, `tiles`, `mma`). + +| # | A-quads | B-pairs | chains×len | k | re-derived (M,N,K,tiles) | spec (M,N,K,tiles) | M/16·N/8·K/32 vs mma | +|---|---|---|---|---|---|---|---| +| 1–6 | 6 | 4 | 24×1 | 1 | 96,32,32,24 | 96,32,32,24 | 6·4·1 = 24 = mma ✔ | +| 7 | 4 | 12 | 48×1 | 1 | 64,96,32,48 | 64,96,32,48 | 4·12·1 = 48 = mma ✔ | +| 8 | 12 | 12 | 16×3 | 3 | **64,32,96,16** | 192,96,96,16 | 4·4·3 = 48 = mma ✔ (spec M,N too big) | +| 9–12 | 1 | 12 | 12×1 | 1 | 16,96,32,12 | 16,96,32,12 | 1·12·1 = 12 = mma ✔ | +| 13,15,…,35 | 3 | 12 | 4×3 | 3 | **16,32,96,4** | 48,96,96,4 | 1·4·3 = 12 = mma ✔ (spec M,N too big) | +| 14,16,…,36 | 1 | 12 | 12×1 | 1 | 16,96,32,12 | 16,96,32,12 | 1·12·1 = 12 = mma ✔ | +| 37 | 12 | 48 | 4×12 | 12 | **16,32,384,4** | 192,384,384,4 | 1·4·12 = 48 = mma ✔ (spec M,N too big) | +| 38 | 3 | 6 | 2×3 | 3 | **16,16,96,2** | 48,48,96,2 | 1·2·3 = 6 = mma ✔ (spec M,N too big) | + +Explicit answer to the flagged rows: **in every one of the 38 rows the identity +`mma = (M/16)·(N/8)·(K/32)` holds, and none of the phase-table rows is +arithmetically inconsistent.** What is wrong in the table is `M` and `N` (and +hence the `full`/`band` label the tool derives from them): the tool sets +`M = 16·|A|`, `N = 8·|B|` (`rr_layer_spec.py:481`, `:590–592`), which counts every +k32 step as a separate m- and n-tile, so whenever `K > 32` its M and N are too +large by exactly the factor `k = K/32` and its `dense` test +(`nmma == nA*nB*lens[0]`, `:593`) is too strict. Dividing out `k` — which the +chain's own `m·k = |A|`, `n·k = |B|`, `m·n = chains` fixes uniquely — gives the +row marked `re-derived`, and every one then satisfies the identity: + +* rows 1–7, 9–12, 14, 16, …, 36 are correct as printed (`k = 1`); +* row 8: `|A|=12, |B|=12, k=3` → **M=64, N=32, K=96** (tool: 192, 96, 96) — + dense, 4·4·3 = 48; +* rows 13, 15, …, 35: `|A|=3, |B|=12, k=3` → **M=16, N=32, K=96** (tool: 48, 96, + 96) — dense, 1·4·3 = 12; the tool's `K = 96` is right, only M and N are 3× too + large; +* row 37: `|A|=12, |B|=48, k=12` → **M=16, N=32, K=384** (tool: 192, 384, 384) — + dense, 1·4·12 = 48; again only M and N are wrong (12×); +* row 38: `|A|=3, |B|=6, k=3` → **M=16, N=16, K=96** (tool: 48, 48, 96) — dense, + 1·2·3 = 6. + +The *operand provenance* of the corrected rows is checked separately from the +counts: for row 8 the 12 A quads are E7's probability packs of a 64×96 matrix +(§3/E7(g)) and the 12 B pairs its `movmatrix` transposes of a 96×32 matrix, giving +4 m-tiles × 3 k and 4 n-tiles × 3 k directly; for rows 13…35 the 3 A quads are +E12's three 16×32 e4m3 slices of the 16×96 normed tile (§3/E12) → 1 m-tile × 3 k; +for row 37 the 12 A quads are read as 48 `ld.shared.u32` from the staged phase-36 +output and the 48 B pairs come from 24 512-byte tiles → 1 m-tile × 12 k and 4 +n-tiles × 12 k; for row 38 the 3 A quads are staged from phase 37's chain-final D +and the 6 B pairs from 3 tile loads → 1 × 3 and 2 × 3. The only thing the operand +provenance does *not* settle is which (n, k) each 512-byte B tile holds for rows +13…35 and 37 — see §6 U1. + +## 3. The epilogues + +### E1 — s4645–s4651: phase 2 B weight loads + +``` +s4645 L7837: mov.u32 %r3499, %laneid +s4646 L7839: mul.wide.u32 %rd270, %r3499, 16 +s4647 L7840: add.s64 %rd271, %rd268, %rd270 +s4648 L7841: add.s64 %rd64, %rd271, 3264 +s4649 L7843: ld.weak.global.ca.v4.u32 { %r3500,%r3501,%r3502,%r3503},[%rd64] +s4650 L7845: add.s64 %rd65, %rd271, 3776 +s4651 L7847: ld.weak.global.ca.v4.u32 { %r3504,%r3505,%r3506,%r3507},[%rd65] +``` + +Two 16-byte/lane fragments of `Wz + {3264, 3776}` = the weight block +`[3264, 4296)` — phase 2's B operand (`%r3500,%r3501` … `%r3506,%r3507`), which +phase 2 consumes at s4652–s4675. `%rd268` is the `Wz` pointer of §1.1, so this +is `W + 21504*%tid.z + 16*laneid + off`. Nothing else. + +### E2 — s4676–s4682: phase 3 B weight loads + +Same shape, base register `%rd268`, offsets `+1216` (s4679) and `+1728` (s4681) +→ `%r3749…%r3756`. Weight block `[1216, 2248)`. + +### E3 — s4707–s4713: phase 4 B weight loads + +Offsets `+4288` (s4710), `+4800` (s4712) → `%r3998…%r4005`. Block +`[4288, 5320)`. + +### E4 — s4738–s4744: phase 5 B weight loads + +Offsets `+2240` (s4741), `+2752` (s4743) → `%r4247…%r4254`. Block +`[2240, 3272)`. + +### E5 — s4769–s4775: phase 6 B weight loads + +Offsets `+5312` (s4772), `+5824` (s4774) → `%r4496…%r4503`. Block +`[5312, 6344)`. + +--- + +### E6 — s4800–s4970: score-bias seeds + packs of phases 5 and 6 + +171 statements: 24 weight loads, 80 `cvt.rn.satfinite.e4m3x2.f16x2`, 40 +`mov.b32`, and the address setup. Two independent things happen. + +**(a) The phase-7 score bias, s4800–s4850.** 24 `ld.weak.global.ca.v4.u32` at +`Wz + 16*laneid + 6336 + 512*i`, `i = 0…23`: + +``` +s4803 L8746: add.s64 %rd74, %rd281, 6336 +s4804 L8748: ld.weak.global.ca.v4.u32 { %r4745,%r4746,%r4747,%r4748},[%rd74] + … +6848, +7360, +7888, … +18112 … +s4850 L8840: ld.weak.global.ca.v4.u32 { %r4837,%r4838,%r4839,%r4840},[%rd97] +``` + +24 × 512 bytes = **12288 bytes** = 6144 f16, the byte block `[6336, 18624)` of +the slab. The 96 registers `%r4745…%r4840` are phase 7's **C operand**: each +mma uses one distinct C pair and the chain analysis of §2.2 shows all 48 pairs +are distinct (grid dump: `C frags: %r4745,%r4746 … %r4839,%r4840`). So the +score GEMM adds a **full 64×96 f16 additive bias, one value per score element**, +laid out tile-major: with `m` = m-tile 0…3 and `n` = n-tile 0…11, + +``` +C(m,n) = the register pair at Wz + 6336 + 512*(4*(n>>1) + m) + 16*laneid + 4*((n&1)*2 + j), j = 0,1 +byte base of tile (m,n) = 6336 + 512*(4*(n>>1) + m), 48 tiles × 512 B = 12288 B. +``` + +Verified directly on the emitted chain: `s4971` uses `C={%r4745,%r4746}` with +`A=%r5033…`, `B={%r5287,%r5288}`; `s4983` (the same m-tile 1 step later) uses +`C={%r4749,%r4750}`; `s4995` `C={%r4753,%r4754}`; `s5007` `C={%r4757,%r4758}` — +stride 4 registers per m-tile, 2 registers per n-tile. This is the same layout +formula enc0's E9 derived for its 12288-byte score bias +(`C(m,n) = load_tile(4*(n>>1)+m) + 4*(n&1)`); only the base differs (6336 here, +8384 there). What the table *is* cannot be decided from the PTX — see §6 U2. + +**(b) Phase 7's operands are register-resident, s4851–s4970.** 80 `cvt` + +40 `mov.b32` produce **both** A and B of phase 7 from phase 5's and phase 6's D: + +``` +s4851 L8843: cvt.rn.satfinite.e4m3x2.f16x2 %rs1462, %r4275 +s4852 L8846: cvt.rn.satfinite.e4m3x2.f16x2 %rs1461, %r4255 +s4853 L8848: mov.b32 %r5287, {%rs1461, %rs1462} // phase 7 B frag 0 + … +s4925 L9016: mov.b32 %r5033, {%rs1509, %rs1510} // phase 7 A frag 0 +``` + +`%r5287` and `%r5033` are **bit-identical**: both are +`{pack(%r4255), pack(%r4275)}` (s4852–s4853 vs s4924–s4925, with `%r4255` ← the +phase-5 D of s4745 and `%r4275` ← that of s4747). Every further pair follows +the same pattern with the two halves swapped: s4865 `%r5307 = +{pack(%r4295), pack(%r4315)}` against s4937 `%r5153 = {pack(%r4315), +pack(%r4295)}`. So phase 7's B operand carries the *same data* as its A operand +(re-ordered for the row/col fragment layouts), i.e. the score GEMM multiplies one +projection by its own transpose; and 4 A quads + 12 B pairs = 64×32 · 32×96. + +**Inputs:** phase 5's D `%r4255…%r4486`, phase 6's D `%r4504…%r4735`, `Wz`. +**Outputs:** the 48 C seeds `%r4745…%r4840`, the 4 A quads +(`%r5033…%r5036`, `%r5153…%r5156`, `%r5273…%r5276`, `%r5393…%r5396`) and the 12 +B pairs (`%r5287…%r5398`). **Memory:** 24 weight loads. + +--- + +### E7 — s5019–s8861: softmax of the 64×96 score, then the V transpose + +3843 statements, **no memory access at all** (0 `ld.*`, 0 `st.*`). Sub-sections, +verified by counting each op's first and last statement: + +| range | stmts | what | +|---|---|---| +| s5019–s7136 | 2118 | 96 per-element groups: scale, clamp, cubic, exponent extraction | +| s7137–s7222 | 86 | in-lane partial sum tree | +| s7223–s7344 | 122 | 16 `shfl.sync.bfly` → 8 row sums | +| s7345–s8117 | 773 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s8118–s8597 | 480 | 192/288 `mul.f16` → 96 probabilities | +| s8598–s8645 | 48 | `movmatrix` transpose of phase 6's D | +| s8646–s8861 | 216 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs | + +**(a) per-element exponent, s5019–s7136.** 96 groups of 22 statements. A group: + +``` +s5020 L9461: mov.f32 %f476, 0f3C8CCB50 +s5021 L9464: cvt.rn.f16.f32 low, %f476 +s5022 L9465: mov.b32 %r5402, {low,low} +s5023 L9469: mul.f16x2 %r5403,%r4921,%r5402 +s5025 L9474: cvt.rn.f16.f64 %rs1542, %fd383 // -0.55615234375 +s5028 L9483: max.f16x2 %r5406,%r5403,%r5408 +s5033 L9497: min.f16x2 %r5409,%r5406,%r5411 // +0.55615234375 +s5034 L9501: neg.f16x2 %r5412,%r5409 +s5039 L9515: fma.rn.f16x2 %r5414,%r5409,%r5412,%r5417 // 0.92724609375 +s5044 L9529: fma.rn.f16x2 %r5418,%r5409,%r5414,%r5421 // 1.375 +s5045 L9532: shl.b32 %r16192, %r5418, 5 +s5046 L9533: and.b32 %r7323, %r16192, 2145419232 // 0x7FE07FE0 +``` + +For each of phase 7's 96 f16x2 D registers, per half (an f16 value `x`): + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +t = f16(m*(-m) + 0.92724609375) +u = f16(m*t + 1.375) = f16(1.375 + m*(0.92724609375 - m^2)) +E = bits(u)[9:5] // floor(32*frac(u)) -- top five mantissa bits +F = bits(u)[4:0] // low five mantissa bits +expval = f16 from bits (E << 10) | (F << 5) // = 2^(E-15)*(1 + F/32) +``` + +Exactly the enc0 E5 scheme (`((u_bits<<5) & 0x7FE07FE0)` drops `u`'s sign and +exponent so the mantissa lands in the exponent field): `expval ≈ +2^(32·frac(u) − 15) = 2^(32u − 47)` with `u ∈ [1.03125, 1.71875]` because the +clamp `±0.55615… = √(0.92724609375/3)` is the turning point of +`0.92724609375·m − m³`. **This is not `exp`**: it is the cubic +`32·(0.375 + 0.92724609375·m − m³)` truncated to a 6-bit significand. + +**(b),(c) row sums, s7137–s7344.** 80 `add.f16x2` reduce the 96 `expval` +registers in-lane; then eight times (one per row `g`, `g+8` of the four m-tiles): + +``` +s7223 L16329: shfl.sync.bfly.b32 %r7567,%r7563,%r3037,%r7570,%r3048 // delta 1 +s7224 L16333: add.f16x2 %r7572,%r7563,%r7567 +s7229 L16344: shfl.sync.bfly.b32 %r7576,%r7572,%r3046,%r7579,%r3048 // delta 2 +s7230 L16348: add.f16x2 %r7581,%r7572,%r7576 +s7232 L16353: add.f16 %rs2309,%rs2310,%rs2311 +s7233 L16356: mov.b32 %r7778, {%rs2309, %rs2309} +``` + +Two butterfly steps over lane bits 0 (delta 1, `%r3037`) and 1 (delta 2, +`%r3046`), then `add.f16` of the two halves and a broadcast into both halves. +Result: **8 row sums** `%r7778 %r7782 %r7826 %r7830 %r7874 %r7878 %r7922 +%r7926`, one per row of the 64-row window. + +**There is no row maximum anywhere in this epilogue.** Enumerated: every one of +the 96 `max.f16x2` (s5028…s7121) is immediately followed by a `min.f16x2` +(s5033…s7125) and preceded by the `mul.f16x2` with `%r5402` (the 0.017181 scale) +— one clamp triple per element group. The 96 `neg.f16x2` (s5034…s7126) feed the +first `fma`, and the 16 `shfl.sync.bfly` are the row sums above. Nothing else +touches a D register. Contrast E38 (§3/E38), which *does* compute a real row +max. + +**(d) reciprocals, s7345–s8117.** 192 `rcp.approx.ftz.f32` = 96 f16x2 +reciprocals, each `cvt.f32.f16 → rcp.approx.ftz.f32 → cvt.rn.f16.f32` on a row +sum (`s7350 L16652: mov.b32 {hl, hu}, %r7778` / `s7353 L16655: +rcp.approx.ftz.f32 fl, fl`), duplicated four times per row sum (once per n-tile). + +**(e) probabilities, s8118–s8597.** + +``` +s8118 L17897: mov.b32 {%rs2334, %rs2337}, %r7323 // expval +s8119 L17898: mov.b32 {%rs2335, %rs2338}, %r7735 // 1/rowsum +s8120 L17900: mul.f16 %rs2336,%rs2337,%rs2338 +s8121 L17904: mul.f16 %rs2333,%rs2334,%rs2335 +s8122 L17907: mov.b32 %r8071, {%rs2333, %rs2336} +``` + +`p = expval · (1/rowsum)`; the row sums cancel the constant `2⁻⁴⁷` of (a), so +`p_ij ∝ 2^(32·u_ij)`. 96 f16x2 results. + +**(f) V transpose, s8598–s8645.** 48 `movmatrix.sync.trans.aligned.m8n8.b16`, one +per register of **phase 6's D** (`%r4504, %r4505, %r4514, %r4515, %r4544, +%r4545, … %r4734, %r4735` — exactly the 24 C/D pairs listed at s4776–s4799, each +once): + +``` +s8598 L18954: movmatrix.sync.trans.aligned.m8n8.b16 %r7927, %r4504 +s8645 L19095: movmatrix.sync.trans.aligned.m8n8.b16 %r8021, %r4735 +``` + +48 × 64 = 3072 values = the whole 96×32 tile of phase 6's D. + +**(g) packs, s8646–s8861.** 144 `cvt` / 72 `mov.b32` in two groups: + +* s8646–s8717 — from the **movmatrix** results → phase 8's 12 B pairs + (`%r8533,%r8534`, `%r8543,%r8544`, … `%r8633,%r8644`), i.e. the transposed V: + `s8646 L19098: cvt.rn.satfinite.e4m3x2.f16x2 %rs2910, %r7935` / + `s8648 L19103: mov.b32 %r8533, {%rs2909, %rs2910}`. +* s8718–s8861 — from the **probabilities** → phase 8's 12 A quads + (`%r8239…%r8242`, `%r8259…`, `%r8279…`, `%r8359…`, `%r8379…`, `%r8399…`, + `%r8479…`, `%r8499…`, `%r8519…`, `%r8599…`, `%r8619…`, `%r8639…%r8642`): + `s8720 L19271: mov.b32 %r8239, {%rs2957, %rs2958}`. + +**Inputs:** phase 7's 96 D f16x2 (`%r4921…%r5392`), phase 6's 48 D +(`%r4504…%r4735`), `%r3037/%r3046/%r3048`, the five constants of §1.2. +**Outputs:** the 5 constants + phase 8's 12 A quads and 12 B pairs. +**Memory:** none. + +--- + +### E8 — s8910–s9078: phase-8 D → shared, phase 9 A, table add → phase 9 C + +169 statements, four moves. + +**(a) stage phase 8's D into shared, s8910–s8968.** + +``` +s8910 L19937: bar.sync 0 +s8911 L19938: shl.b32 %r16320, %r10, 11 // %tid.z * 2048 +s8912 L19939: add.s32 %r16321, %r3216, %r16320 // %r3216 = smem symbol +s8915 L19944: add.s32 %r16323, %r16321, %r16322 // + 16*laneid +s8928 L19973: st.shared.v4.u32 [%r16323], {%r16327, %r16326, %r16325, %r16324} +s8941 L20002: st.shared.v4.u32 [%r16323+512], {…} +s8954 L20031: st.shared.v4.u32 [%r16323+1024], {…} +s8967 L20060: st.shared.v4.u32 [%r16323+1536], {…} +s8968 L20061: bar.sync 0 +``` + +Four v4 stores (16 bytes/lane) at `smem + 2048*%tid.z + 16*laneid + {0,512,1024, +1536}`. Each v4 word is an e4m3 pack of **two** distinct phase-8 D registers +(e.g. s8916 `cvt %rs3054, %r8267`, s8917 `cvt %rs3053, %r8207`, s8924 +`mov.b32 %r16324, {%rs3059, %rs3060}`); all 32 `cvt` in the block name distinct +registers, so **32 of phase 8's 48 D registers are staged** here, 16 words per +lane. + +**(b) phase 9's A, s8969–s8974.** + +``` +s8969 L20062: shl.b32 %r16340, %r10, 9 // %tid.z * 512 +s8970 L20063: add.s32 %r16341, %r3216, %r16340 +s8973 L20068: add.s32 %r16343, %r16341, %r16342 // + 16*laneid +s8974 L20069: ld.shared.v4.u32 {%r16344, %r16345, %r16346, %r16347}, [%r16343] +``` + +One A quad (`%r16344…%r16347`), i.e. the e4m3-packed phase-8 D, re-read through +shared. Phase 9's mma (s9079) uses exactly this quad. + +**(c) phase 9's B, s8975–s8989.** 6 `ld.weak.global.ca.v4.u32` at +`W + 16*laneid + 18624 + 512*i`, `i = 0…5` (s8978 `add.s64 %rd98, %rd283, +18624`) → `%r8682…%r8705`, the 12 B pairs of phase 9. Note the base is `%rd283 = +%rd2 + 16*laneid` (s8977) — **no `%tid.z` term**, unlike E1–E6. + +**(d) per-column residual table → phase 9's C, s8990–s9078.** + +``` +s8995 L20106: ld.global.v2.u16 {%rs4364, %rs4365}, [%rd286+86224] + … 86240, 86256, 86272, 86288, 86304, 86320, 86336, 86352, 86368, 86384, 86208 +s9007 L20119: add.f16 %rs3088,%rs4387,%rs1103 +s9008 L20123: add.f16 %rs3085,%rs4386,%rs1100 +s9009 L20126: mov.b32 %r8715, {%rs3085, %rs3088} +``` + +12 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {86208, 86224, …, 86384}` = 192 +bytes = 96 f16, a per-column vector over the 96-wide N axis. 48 `add.f16` add +them (pair-swapped) to the 48 halves of 24 **prologue** registers and 24 +`mov.b32` build the 24 registers `%r8715…%r8826` = phase 9's **C operand**. +The 48 added operands are `%rs1100 … %rs1361`, and every one of them is defined +by a prologue `mov.b32` from the *quantised input patch* — `%rs1100/%rs1103` ← +`%r2798` (s3366, source line 4684), `%rs1106/%rs1109` ← `%r2802`, … — where +`%r2798` is itself `cvt.rn.f16x2.e4m3x2 %r2798, %rs128` (s3320), i.e. the first +element of the input image read at s176. So + +``` +C9 = column_table[86208] + (the block's quantised input patch, re-read as f16) +``` + +— an *input* skip connection, **not** phase 8's D. (This is a surprising but +direct reading: the 48 `add.f16` sources are the halves of `%r2798…%r2845`, the +prologue's `cvt.rn.f16x2.e4m3x2` results, and no statement anywhere redefines +them; see §6 U9.) + +**Inputs:** phase 8's 48 D (staged in (a)), the prologue's 24 quantised input +registers `%r2798…`, table `86208`, `%tid.z`, `%r3216`, `W`. +**Outputs (live 49):** `%r16344…%r16347` (via shared), the 24 C seeds, the 12 B +pairs. **Memory:** 6 weight loads + 12 table reads + 2 barriers + 4 shared +stores + 1 shared load. + +--- + +### E9 — s9091–s9109: phase 10 A from shared + phase 10 B + +19 statements. + +``` +s9091 L20419: mov.u32 %r8827, %laneid +s9092 L20421: shl.b32 %r16349, %r8827, 4 +s9094 L20423: ld.shared.v4.u32 {%r16351, %r16352, %r16353, %r16354}, [%r16350+2048] +s9099 L20431: ld.weak.global.ca.v4.u32 { %r8829,%r8830,%r8831,%r8832},[%rd104] + … 5 more at 512 stride … +s9109 L20451: ld.weak.global.ca.v4.u32 { %r8849,%r8850,%r8851,%r8852},[%rd109] +``` + +One A quad read from `smem + 16*laneid + 2048` (i.e. the *next* staged slot of +(a) in E8), and 6 weight fragments at `W + 16*laneid + 40128 + 512*i` = phase +10's B (`%r8829…%r8852`). The shared slot is 2048 bytes above the slot phase 9 +read, so the four staged v4 words serve phases 9, 10, 11, 12 at +`base + {0, 2048, 4096, 6144}`. + +### E10 — s9122–s9140: phase 11 A from shared + phase 11 B + +Same shape; `s9125 L20542: ld.shared.v4.u32 {%r16357…%r16360}, [%r16356+4096]` and +6 weight fragments at `W + 16*laneid + 61632 + 512*i` (s9130 …) → `%r8975…%r8998`. + +### E11 — s9153–s9171: phase 12 A from shared + phase 12 B + +`s9156 L20661: ld.shared.v4.u32 {%r16363…%r16366}, [%r16362+6144]` and 6 weight +fragments at `W + 16*laneid + 83136 + 512*i` (s9161 …) → `%r9121…%r9144`. +Note phases 9–12 also chain their C: phase 12's C is +`{%r8999,%r9000}` = phase 11's D (s9141 / s9172), and likewise 10←9, 11←10. + +--- + +### E12 — s9184–s9819: the RMS norm before the MLP band + +636 statements. Structure (counts from the op histogram of s9184–s9819: 182 +`mov.b32`, 144 `mul.f16`, 50 `add.f16`, 48 each `cvt.f32.f16` / +`rsqrt.approx.ftz.f32` / `cvt.rn.f16.f32`, 26 `add.f16x2`, 24 +`cvt.rn.satfinite.e4m3x2.f16x2`, 12 `ld.global.v2.u16`, 6 weight loads, 4 +`shfl.sync.bfly`): + +| range | stmts | op | +|---|---|---| +| s9184–s9281 | 98 | 48 `mul.f16` — the squares of phase 12's D | +| s9282–s9301 | 20 | 21 `add.f16x2` — in-lane reduction tree | +| s9302–s9344 | 43 | 4 `shfl.sync.bfly` + `add.f16x2` + `add.f16` + `+ eps`, broadcast into 24 b32 | +| s9345–s9405 | 61 | 48 `add.f16` more (24 duplicated eps-bearing sums) | +| s9406–s9598 | 193 | 48 `rsqrt.approx.ftz.f32` (24 inverses) | +| s9599–s9615 | 17 | 12 gain loads `+86400 … +86576` | +| s9616–s9687 | 72 | 48 `mul.f16` — `inv · gain` | +| s9688–s9759 | 72 | 48 `mul.f16` — `x · (inv·gain)` | +| s9760–s9774 | 15 | 6 weight loads `+86632 … +89192` (phase 13's B) | +| s9775–s9783 | 9 | 4 `ld.global.u32` `+89664 … +89712` (phase 13's C seeds) | +| s9784–s9819 | 36 | 24 packs → phase 13's A | + +Evidence: + +``` +s9185 L20776: add.s32 %r182, %r2, %r181 // %r2 + 2*%tid.z +s9186 L20777: mov.b32 {%rs3838, %rs3841}, %r9145 // unpack a D register +s9187 L20779: mul.f16 %rs3232,%rs3841,%rs3841 // square (high half) +s9188 L20783: mul.f16 %rs3229,%rs3838,%rs3838 // square (low half) +s9282 L21018: add.f16x2 %r9265,%r9266,%r9267 +s9303 L21101: add.f16x2 %r9326,%r9313,%r9319 +s9308 L21112: shfl.sync.bfly.b32 %r9330,%r9326,%r3037,%r9333,%r3048 +s9317 L21136: add.f16 %rs3373,%rs3374,%rs3375 +s9333 L21179: cvt.rn.f16.f64 %rs3379, %fd1 // eps = 2^-13 +s9334 L21183: add.f16 %rs3383,%rs3373,%rs3379 +s9410 L21407: rsqrt.approx.ftz.f32 fl, fl +s9604 L21720: ld.global.v2.u16 {%rs4388, %rs4389}, [%rd295+86416] +s9616 L21732: mov.b32 {%rs3525, %rs3528}, %r9369 +s9688 L21949: mul.f16 %rs3671,%rs3841,%rs3527 // x * (inv*gain) +s9690 L21956: mov.b32 %r15561, {%rs3668, %rs3671} // the normed register +s9784 L22205: cvt.rn.satfinite.e4m3x2.f16x2 %rs3813, %r15562 +s9786 L22210: mov.b32 %r9540, {%rs3812, %rs3813} +s9780 L22200: ld.global.u32 %r9477, [%rd300+89664] +``` + +**What it computes.** Phase 12's D is 24 registers = 48 f16/lane; each register +pairs `(row g, cols 2t,2t+1)` with `(row g+8, cols 2t,2t+1)`, and two registers +(`%r9145`,`%r9146`) are one n-tile. For each of the two rows a lane holds: + +``` +sumsq[row] = Σ_{c=0..95} x[row,c]^2 (f16, one shfl.bfly pair) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2^-13))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` + +* **There is no mean subtraction and no `1/N`**: `%rs3232/%rs3229` are raw + squares (`mul.f16 %rs3232,%rs3841,%rs3841`), the tree only adds, and the only + constant added is `%fd1 = 2⁻¹³` (s9333/s9334). The quantity is the raw sum of + 96 squares plus `2⁻¹³`; the mean is never formed. This is an **RMS norm**, not + a mean-subtracting LayerNorm. +* `gain[c]` is read from `W + ((laneid<<2)&12) + {86400, 86416, …, 86576}` (12 + `v2.u16` at 16-byte stride = 192 bytes = 96 f16), i.e. a per-column vector over + the 96 columns, constant across rows. +* the two butterfly steps (`%r3037 = 1`, `%r3046 = 2`, segmask 31, membermask + −1 at s9307/s9313) reduce over the four lanes with equal `laneid>>2`, which + between them hold all 96 columns of the row; `add.f16 %rs3373,%rs3374,%rs3375` + folds the two column halves. The inverse is broadcast into both halves + (`mov.b32 %r9370, {%rs3380, %rs3383}`) so one row value serves all n-tiles. +* the norm's *bias* is **not** added here. It is the 4 `ld.global.u32` at the end + (s9780–s9783), which become phase 13's C seeds as `{%r9477, %r9477}` etc. — + a per-column bias replicated over the 16 rows. + +**The prologue's `normalise:96@s3812` is the same function.** Its op block +(s3250–s4497) has the same shape and the same missing pieces: 48 +`cvt.rn.f16x2.e4m3x2` quantise the 24 `ld.global.v2.u16` input loads (s176, +s328, … s3316, all through `%rd12 = %rd4 + 4*index`, `%rd4 = param_0+8`, i.e. +the input image); 96 `mul.f16` square them in place +(`s3431 L4846: mul.f16 %rs321,%rs1199,%rs1199`); 52 `add.f16x2` + 8 +`shfl.sync.bfly` + `add.f16` reduce; `s3662 L5488: mov.f64 %fd1, +0d3F20000000000000` / `s3664 L5494: add.f16 %rs526,%rs510,%rs522` add the +*same* `2⁻¹³`; 96 `rsqrt.approx.ftz.f32` (48 pairs, `s3812 L5934: +rsqrt.approx.ftz.f32 fl, fl`) invert; the 96 products are multiplied by a +per-column gain read as 12 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + +{16, 32, …, 176, 0}` (s4198–s4209, 192 bytes = 96 f16); 96 more `mul.f16` +(`s4211 L6573: mul.f16 %rs811,%rs812,%rs1459`) apply the gain; 48 +`cvt.rn.satfinite.e4m3x2.f16x2` (s4498–s4521) requantise and six +`st.shared.v4.u32` (s4540, s4553, s4566, s4576, s4581, s4586) stage the 18 A +quads. No mean, no `1/N`, no bias add — **also an RMS norm**, with its bias +deferred to a later GEMM's C exactly as in E12. + +**The normed tile is the A operand of every odd phase 13…35.** E12's output +registers `%r15561…%r15584` (24 b32) are re-packed not only here (s9784–s9819, +→ `%r9540,%r9541,%r9542,%r9543` … `%r9580…%r9583`, i.e. three 16×32 A slices) +but again in **every even-numbered epilogue E14, E16, …, E34**: +`%r15561` is read by exactly the s9785 (E12), s10126 (E14), s10374 (E16), +s10622 (E18), s10870 (E20), s11118 (E22), s11366 (E24), s11614 (E26), s11862 +(E28), s12110 (E30), s12358 (E32), s12606 (E34) — twelve repacks, one per band +phase. So all twelve odd phases 13, 15, …, 35 share **one** input tile. + +**Inputs:** phase 12's 24 D, `%fd1`, the gain table, `W`. **Outputs (54 live):** +phase 13's 3 A quads (`%r9540…%r9543`, `%r9560…%r9563`, `%r9580…%r9583`), phase +13's 4 C seeds (`%r9477, %r9487, %r9537, %r9547`) and 12 B pairs (`%r9419…%r9442`, +6 loads at `+86592…+89152`), the 24 normed registers `%r15561…%r15584` (re-read by +E14, E16, …, E34). **Memory:** 12 table + 6 weight loads. + +--- + +### E13 — s9832–s10088: clamped cubic + residual/table, packs + +257 statements. This is the epilogue that materialises `%f861…%f864`. + +**(a) the activation, s9832–s10076.** 8 groups (one per chain-final D register of +phase 13: `%r9508 %r9518 %r9509 %r9519 %r9568 %r9578 %r9569 %r9579`), 17 +statements each: + +``` +s9833 L22375: mov.f32 %f861, 0f3ED306EB +s9836 L22382: mov.f32 %f862, 0f3DA60DD6 +s9839 L22389: mov.f32 %f863, 0f3F000000 +s9842 L22396: mov.f32 %f864, 0f40000000 +s9845 L22404: neg.f16x2 %r9593,%r9592 // -2.0 +s9846 L22408: max.f16x2 %r9595,%r9508,%r9593 // max(x, -2) +s9847 L22412: min.f16x2 %r9598,%r9595,%r9592 // min(·, +2) +s9848 L22416: abs.f16x2 %r9601,%r9598 // |y| +s9849 L22420: mul.f16x2 %r9603,%r9590,%r9601 // 0.0810546875*|y| +s9850 L22424: sub.f16x2 %r9606,%r9589,%r9603 // 0.412109375 - that +s9851 L22428: mul.f16x2 %r9609,%r9598,%r9606 // y * that +s9852 L22432: add.f16x2 %r9612,%r9591,%r9609 // 0.5 + that +s9853 L22436: mul.f16x2 %r9615,%r9508,%r9612 // x * g +``` + +Per element, `y = clamp(x, −2, +2)` and + +``` +g = 0.5 + y * (0.412109375 − 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a cubic ramp: `g(+2) = 1` so `out = x` for `x ≥ 2`; `g(−2) = 0` so +`out = 0` for `x ≤ −2`. The constants and the op order are **byte-identical to +enc0's E13** (`0f3ED306EB`, `0f3DA60DD6`, `0.5`, `2.0`, `neg/max/min/abs/mul/ +sub/mul/add/mul`): this is the same clamped cubic, not a GELU, not a sigmoid and +not a polynomial in `x`. Reproduce the formula, not `x·sigmoid(x)`. + +**(b) the residual + per-column table → phase 14's C, s9990–s10076.** + +``` +s9993 L22895: ld.global.v2.u16 {%rs4412, %rs4413}, [%rd305+92816] + … 92832, 92848, 92864, 92880, 92896, 92912, 92928, 92944, 92960, 92976, 92800 +s10005 L22908: add.f16 %rs3839,%rs4435,%rs3841 +s10006 L22912: add.f16 %rs3836,%rs4434,%rs3838 +s10007 L22915: mov.b32 %r9863, {%rs3836, %rs3839} +``` + +12 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + {92800…92976}` (192 bytes = 96 +f16, one per column), then 48 `add.f16` and 24 `mov.b32` producing +`%r9863…%r9974`, the 24 registers phase 14 uses as its C operand. `%rs3838/ +%rs3841` are the two halves of `%r9145` — **phase 12's D**, not phase 13's, so + +``` +C14 = D12 + column_table[92800] (a residual, added to all 16 rows) +``` + +**(c) phase 14's B, s9977–s9989.** 6 `ld.weak.global.ca.v4.u32` at +`W + 16*laneid + 89728 + 512*i` → `%r9822…%r9845`. + +**(d) packs, s10077–s10088.** 8 `cvt` + 4 `mov.b32` → `%r9967, %r9969, %r9968, +%r9970` = phase 14's A quad, from the activation outputs (`%r9615`, `%r9644`, +`%r9673`, `%r9731`, `%r9760`, `%r9789`, `%r9818`, `%r9702`): + +``` +s10077 L23124: cvt.rn.satfinite.e4m3x2.f16x2 %rs3981, %r9731 +s10078 L23127: cvt.rn.satfinite.e4m3x2.f16x2 %rs3980, %r9615 +s10079 L23129: mov.b32 %r9967, {%rs3980, %rs3981} +``` + +**Inputs:** phase 13's 8 chain-final D, phase 12's 24 D, table `92800`, `W`. +**Outputs (24 live):** `%f861…%f864`, `%r9967…%r9970`, `%r9863…%r9974`, +`%r9822…%r9845`. **Memory:** 6 weight + 12 table loads. + +### E14 — s10101–s10160: phase 15 B/C + packs of the normed tile + +60 statements: 6 weight loads at `+92992…+95552` → `%r9976…%r9999` (phase 15's +B); 4 `ld.global.u32` at `+96064, +96080, +96096, +96112` → `%r10034, %r10044, +%r10094, %r10104` (phase 15's C seeds, each used as `{%rX, %rX}`); and 24 packs +of **E12's normed registers** into phase 15's 3 A quads: + +``` +s10126 L23279: cvt.rn.satfinite.e4m3x2.f16x2 %rs3988, %r15561 +s10127 L23281: mov.b32 %r10097, {%rs3988, %rs3989} + … %r10098, %r10099, %r10100 (quad 1) ; %r10117…%r10120; %r10137…%r10140 +``` + +Note the pack order is `%r10097←(%r15561,%r15562)`, `%r10099←(%r15563,%r15564)`, +`%r10098←(%r15565,%r15566)`, `%r10100←(%r15567,%r15568)` (s10125–s10136), i.e. +the whole 16×96 normed tile is re-quantised into 12 b32 = three 16×32 A slices. + +### E15 — s10173–s10336: clamped cubic on phase 15's D + +164 statements = 8 activation groups + 6 weight loads + 4 packed b32. Identical +to E13(a) but on phase 15's chain-final D (`%r10065 %r10075 %r10066 %r10076 +%r10125 %r10135 %r10126 %r10136`) and with **no constants of its own** and **no +`ld.global`** — the four `cvt.rn.f16.f32` read `%f861…%f864` defined in E13: + +``` +s10174 L23448: cvt.rn.f16.f32 low, %f861 +s10183 L23475: max.f16x2 %r10152,%r10065,%r10150 +s10190 L23503: mul.f16x2 %r10172,%r10065,%r10169 +s10314 L23933: ld.weak.global.ca.v4.u32 { %r10379,…},[%rd140] // +96128 +s10325 L23956: cvt.rn.satfinite.e4m3x2.f16x2 %rs4013, %r10288 +s10327 L23961: mov.b32 %r10523, {%rs4012, %rs4013} +``` + +Outputs phase 16's A quad (`%r10523…%r10526`) and phase 16's B (6 loads at +`+96128…+98688`). **No column-bias add.** + +### E16 — s10349–s10408: phase 17 B/C + packs of the normed tile + +Identical in shape to E14: B at `+99200 … +101760`, C words at +`+102272, +102288, +102304, +102320` (`s10369 L24103: ld.global.u32 %r10590, +[%rd317+102272]`), and 24 packs of `%r15561…%r15584` (s10373 ff.) → phase 17's +three A quads `%r10653…%r10656`, `%r10673…%r10676`, `%r10693…%r10696`. + +### E17 — s10421–s10584: clamped cubic on phase 17's D + +164 statements. 8 activation groups (17 statements each, the E13(a) shape) on +phase 17's chain-final D registers `%r10621 %r10631 %r10622 %r10632 %r10681 +%r10691 %r10682 %r10692`; no constants of its own (`cvt.rn.f16.f32 low, %f861` +opens the first group at s10422); 6 weight loads at `W + 16*laneid + +102336 + 512*i` = phase 18's B; 8 `cvt` + 4 `mov.b32` → phase 18's A quad +`%r11079…%r11082`. + +### E18 — s10597–s10656: phase 19 B/C loads + packs of the normed tile + +60 statements: 6 weight loads at `+105408 … +107968` (phase 19's B), 4 +`ld.global.u32` at `+108480, +108496, +108512, +108528` (phase 19's C seeds, +each used as `{%rX, %rX}`), and 24 `cvt` / 12 `mov.b32` of `%r15561…%r15584` → +phase 19's three A quads `%r11209…%r11212`, `%r11229…%r11232`, +`%r11249…%r11252`. Evidence: +`s10601 L24906: ld.weak.global.ca.v4.u32 { %r11088,…},[%rd158]`; +`s10617 L24935: ld.global.u32 %r11146, [%rd324+108480]`. + +### E19 — s10669–s10832: clamped cubic on phase 19's D + +164 statements, identical to E17. Chain-final D `%r11177 %r11187 %r11178 +%r11188 %r11237 %r11247 %r11238 %r11248`; phase 20's B at `+108544 … +111104`; +phase 20's A quad `%r11635…%r11638`. + +### E20 — s10845–s10904: phase 21 B/C loads + packs of the normed tile + +60 statements. B `+111616 … +114176`; C `+114688, +114704, +114720, +114736`; +A quads `%r11765…%r11768`, `%r11785…%r11788`, `%r11805…%r11808`. Evidence: +`s10849 L25738: ld.weak.global.ca.v4.u32 { %r11644,…},[%rd170]`; +`s10865 L25767: ld.global.u32 %r11702, [%rd331+114688]`. + +### E21 — s10917–s11080: clamped cubic on phase 21's D + +164 statements. Chain-final D `%r11733 %r11743 %r11734 %r11744 %r11793 +%r11803 %r11794 %r11804`; phase 22's B at `+114752 … +117312`; phase 22's A +quad `%r12191…%r12194`. + +### E22 — s11093–s11152: phase 23 B/C loads + packs of the normed tile + +60 statements. B `+117824 … +120384`; C `+120896, +120912, +120928, +120944`; +A quads `%r12321…%r12324`, `%r12341…%r12344`, `%r12361…%r12364`. Evidence: +`s11097 L26570: ld.weak.global.ca.v4.u32 { %r12200,…},[%rd182]`; +`s11113 L26599: ld.global.u32 %r12258, [%rd338+120896]`. + +### E23 — s11165–s11328: clamped cubic on phase 23's D + +164 statements. Chain-final D `%r12289 %r12299 %r12290 %r12300 %r12349 +%r12359 %r12350 %r12360`; phase 24's B at `+120960 … +123520`; phase 24's A +quad `%r12747…%r12750`. + +### E24 — s11341–s11400: phase 25 B/C loads + packs of the normed tile + +60 statements. B `+124032 … +126592`; C `+127104, +127120, +127136, +127152`; +A quads `%r12877…%r12880`, `%r12897…%r12900`, `%r12917…%r12920`. Evidence: +`s11345 L27402: ld.weak.global.ca.v4.u32 { %r12756,…},[%rd194]`; +`s11361 L27431: ld.global.u32 %r12814, [%rd345+127104]`. + +### E25 — s11413–s11576: clamped cubic on phase 25's D + +164 statements. Chain-final D `%r12845 %r12855 %r12846 %r12856 %r12905 +%r12915 %r12906 %r12916`; phase 26's B at `+127168 … +129728`; phase 26's A +quad `%r13303…%r13306`. + +### E26 — s11589–s11648: phase 27 B/C loads + packs of the normed tile + +60 statements. B `+130240 … +132800`; C `+133312, +133328, +133344, +133360`; +A quads `%r13433…%r13436`, `%r13453…%r13456`, `%r13473…%r13476`. Evidence: +`s11593 L28234: ld.weak.global.ca.v4.u32 { %r13312,…},[%rd206]`; +`s11609 L28263: ld.global.u32 %r13370, [%rd352+133312]`. + +### E27 — s11661–s11824: clamped cubic on phase 27's D + +164 statements. Chain-final D `%r13401 %r13411 %r13402 %r13412 %r13461 +%r13471 %r13462 %r13472`; phase 28's B at `+133376 … +135936`; phase 28's A +quad `%r13859…%r13862`. + +### E28 — s11837–s11896: phase 29 B/C loads + packs of the normed tile + +60 statements. B `+136448 … +139008`; C `+139520, +139536, +139552, +139568`; +A quads `%r13989…%r13992`, `%r14009…%r14012`, `%r14029…%r14032`. Evidence: +`s11841 L29066: ld.weak.global.ca.v4.u32 { %r13868,…},[%rd218]`; +`s11857 L29095: ld.global.u32 %r13926, [%rd359+139520]`. + +### E29 — s11909–s12072: clamped cubic on phase 29's D + +164 statements. Chain-final D `%r13957 %r13967 %r13958 %r13968 %r14017 +%r14027 %r14018 %r14028`; phase 30's B at `+139584 … +142144`; phase 30's A +quad `%r14415…%r14418`. + +### E30 — s12085–s12144: phase 31 B/C loads + packs of the normed tile + +60 statements. B `+142656 … +145216`; C `+145728, +145744, +145760, +145776`; +A quads `%r14545…%r14548`, `%r14565…%r14568`, `%r14585…%r14588`. Evidence: +`s12089 L29898: ld.weak.global.ca.v4.u32 { %r14424,…},[%rd230]`; +`s12105 L29927: ld.global.u32 %r14482, [%rd366+145728]`. + +### E31 — s12157–s12320: clamped cubic on phase 31's D + +164 statements. Chain-final D `%r14513 %r14523 %r14514 %r14524 %r14573 +%r14583 %r14574 %r14584`; phase 32's B at `+145792 … +148352`; phase 32's A +quad `%r14971…%r14974`. + +### E32 — s12333–s12392: phase 33 B/C loads + packs of the normed tile + +60 statements. B `+148864 … +151424`; C `+151936, +151952, +151968, +151984`; +A quads `%r15101…%r15104`, `%r15121…%r15124`, `%r15141…%r15144`. Evidence: +`s12337 L30730: ld.weak.global.ca.v4.u32 { %r14980,…},[%rd242]`; +`s12353 L30759: ld.global.u32 %r15038, [%rd373+151936]`. + +### E33 — s12405–s12568: clamped cubic on phase 33's D + +164 statements. Chain-final D `%r15069 %r15079 %r15070 %r15080 %r15129 +%r15139 %r15130 %r15140`; phase 34's B at `+152000 … +154560`; phase 34's A +quad `%r15527…%r15530`. + +### E34 — s12581–s12640: phase 35 B/C loads + packs of the normed tile + +60 statements. B `+155072 … +157632`; C `+158144, +158160, +158176, +158192`; +A quads `%r15657…%r15660`, `%r15677…%r15680`, `%r15697…%r15700`. Evidence: +`s12585 L31562: ld.weak.global.ca.v4.u32 { %r15536,…},[%rd254]`; +`s12601 L31591: ld.global.u32 %r15594, [%rd380+158144]`. + +### E35 — s12653–s12816: clamped cubic on phase 35's D + +164 statements. Chain-final D `%r15625 %r15635 %r15626 %r15636 %r15685 +%r15695 %r15686 %r15696`; phase 36's B at `+158208 … +160768` +(`s12794 L32253: ld.weak.global.ca.v4.u32 { %r15939,…},[%rd260]`); phase 36's A +quad `%r16083…%r16086`. This is the last of the twelve band activations; its +output feeds phase 36, whose output E36 packs (and this is where the A-quad +chain from the normed tile ends). + +#### Shape of the whole MLP band (E12–E36) + +``` +E12 normed tile N (24 b32, %r15561…%r15584) — RMS norm of the attention output + ├─ pack → P13 A (s9784) P13 : A = N, B = W+86592, C = bias@89664 → D13 + │ E13: clamped cubic(D13) pack → P14 A; D12 + table@92800 → P14 C; P14 B = W+89728 + ├─ pack → P15 A (s10126) P15 : A = N, B = W+92992, C = bias@96064 → D15 + │ E15: clamped cubic(D15) pack → P16 A; P16 B = W+96128, C = D14 + ├─ pack → P17 A (s10373) P17 : A = N, B = W+99240, C = bias@102272 → D17 + │ E17: clamped cubic(D17) pack → P18 A; P18 B = W+102336, C = D16 + ⋮ (twenty-four phases, twelve repetitions of the pair) + ├─ pack → P35 A (s12606) P35 : A = N, B = W+155072, C = bias@158144 → D35 + │ E35: clamped cubic(D35) pack → P36 A + └───────────────────────── P36 : A = act(D35), B = W+158208, C = D34 → D36 +``` + +So the band is **twelve branches off one shared normed tile**, each branch being +the pair (odd phase: 48×96×32 banded GEMM with clamped cubic and a per-column +bias; even phase: 16×96×32 GEMM whose C is the running residual `D12 + table` +and whose output is fed to the next odd phase as `B`), and the residual chain +runs `D12 → D14 → D16 → … → D36`. `D36` (12 registers, 16×96) is the band's +output and is the input to E36. + +--- + +### E36 — s12829–s13698: arena scatter, shared staging, phase 37 A/B/C + +870 statements. Four sequential moves. + +**(a) requantise, s12829–s12864.** 24 `cvt.rn.satfinite.e4m3x2.f16x2` + 12 +`mov.b32` → `%r183…%r194` (12 b32), the requantised 16×96 output of phase 36. +Each pair of e4m3 registers is built from `(reg0, reg2)` / `(reg1, reg3)` of a +phase-36 D brace group: + +``` +s12829 L32388: cvt.rn.satfinite.e4m3x2.f16x2 %rs4341, %r15991 +s12830 L32391: cvt.rn.satfinite.e4m3x2.f16x2 %rs4340, %r15971 +s12831 L32393: mov.b32 %r183, {%rs4340, %rs4341} +``` + +**(b) plane-arena scatter to `param+48`, s12865–s13009.** + +``` +s12865 L32471: ld.param.u64 %rd383, [%rd1+-32] // %rd1 = param_0+80 → param_0+48 +s12866 L32472: cvta.to.global.u64 %rd5, %rd383 +s12868 L32476: shr.u32 %r195, %r16115, 2 // g = laneid>>2 +s12869 L32477: and.b32 %r196, %r16115, 3 // t = laneid&3 +s12870 L32478: shr.u32 %r16389, %r16115, 5 +s12872 L32480: add.s32 %r16391, %r182, %r16389 // y = %r182 + (laneid>>5) +s12878 L32486: add.s32 %r16392, %r1, %r16390 // x = %r1 + (g&7) +s12884 L32492: mad.lo.s32 %r197, %r5, %r16391, %r16393 // %r5 = 8*ex +s12885 L32493: add.s32 %r16394, %r196, %r197 // + t (+ guard bit) +s12886 L32494: selp.b32 %r198, -1, %r16394, %p1 +s12887 L32495: setp.lt.s32 %p197, %r198, 0 +s12888 L32496: @%p197 bra $L__BB1_196 +s12889 L32498: mul.wide.s32 %rd384, %r198, 4 +s12890 L32499: add.s64 %rd385, %rd5, %rd384 +s12891 L32500: st.global.u32 [%rd385], %r183 +``` + +Twelve `st.global.u32`, all with `idx = 8·ex·y + 8·x + d` in units of 4 bytes: + +| # | stmt | value | index base | guard | d | +|---|---|---|---|---|---| +| 1 | s12891 | `%r183` | `%r197 = 8*ex*(%r182 + (laneid>>5)) + 8*(%r1 + (g&7))` | p1 | `t` | +| 2 | s12900 | `%r184` | `%r197` | p1 | `t\|4` | +| 3 | s12933 | `%r185` | `%r201 = 8*ex*(%r182 + ((g+8)>>3)) + 8*(%r1 + ((g+8)&7))` | p2 | `t` | +| 4 | s12941 | `%r186` | `%r201` | p2 | `t\|4` | +| 5 | s12950 | `%r187` | `%r204 = %r197 + %r6` | p1 | `t` | +| 6 | s12958 | `%r188` | `%r204` | p1 | `t\|4` | +| 7 | s12967 | `%r189` | `%r207 = %r201 + %r6` | p2 | `t` | +| 8 | s12975 | `%r190` | `%r207` | p2 | `t\|4` | +| 9 | s12984 | `%r191` | `%r210 = %r204 + %r6` | p1 | `t` | +| 10 | s12992 | `%r192` | `%r210` | p1 | `t\|4` | +| 11 | s13001 | `%r193` | `%r213 = %r207 + %r6` | p2 | `t` | +| 12 | s13009 | `%r194` | `%r213` | p2 | `t\|4` | + +with `%r5 = 8*ex` (s15), `%r6 = ey·8·ex` (s16, one image plane), `%r182 = +%r2 + 2·%tid.z` (s9185), `g = laneid>>2`, `t = laneid&3`. Each store block is +guarded by `p1`/`p2` = `(y<0)|(y≥ey)|(laneid>63)|(x<0)|(x≥ex)` (s12874–s12882, +s12916–s12924) and a guard failure stores `-1` as the index, which the following +`setp.lt.s32 %p, %idx, 0` + `bra` turns into "skip the store" (the pattern of +s12886–s12888). Note the index also has the guard *bit* added +(`add.s32 %r16394, %r196, %r197` at s12885 uses `%r196` — a predicate register +read as 0/1), which the `selp`/`bra` pair makes harmless. + +**(c) shared staging, s13013–s13131.** + +``` +s13013 L32645: bar.sync 0 +s13014 L32647: mov.u32 %r16412, %laneid +s13018 L32652: add.s32 %r16414, %r17741, %r16413 // %r17741 = 2*%tid.z, %r16413 = laneid>>5 +s13022 L32656: shl.b32 %r16415, %r16414, 5 +s13023 L32657: and.b32 %r16416, %r16412, 28 +s13025 L32659: or.b32 %r218, %r217, %r16417 +s13031 L32666: st.shared.u32 [%r16420], %r183 +s13039 L32676: st.shared.u32 [%r16424], %r184 // index + 256 +s13059 L32698: st.shared.u32 [%r16434], %r185 // group 2, base from (laneid>>2)+8 +s13067 L32708: st.shared.u32 [%r16438], %r186 + … +512, +768, +1024, +1280 variants for %r187…%r194 … +s13131 L32788: st.shared.u32 [%r16470], %r194 +``` + +Twelve `st.shared.u32`, word index for the first six +`(2·%tid.z)·32 + (laneid & 28)` and `+256`, and for the last six +`((2·%tid.z)+((laneid>>2)+8)>>3)·32 + (((laneid>>2)+8)<<2 & 28)` and `+256` +(s13043–s13058, s13061–s13074). See §6 U3 for the address collision this +produces. A second `bar.sync 0` follows at s13136. + +**(d) phase 37's A operand from shared, s13138–s13625.** + +``` +s13138 L32798: ld.param.v2.u32 {%r16472, %r16473}, [%rd489+-80] // param_0+0 = (ex, ey) +s13143 L32804: shr.u32 %r16475, %r16471, 2 +s13146 L32807: and.b32 %r16478, %r16477, -64 +s13148 L32809: and.b32 %r16480, %r16479, 24 +s13150 L32811: or.b32 %r16482, %r16476, %r16481 +s13151 L32812: shl.b32 %r16483, %r16482, 2 +s13152 L32813: add.s32 %r16485, %r3216, %r16483 +s13153 L32814: ld.shared.u32 %r235, [%r16485] +s13165 L32826: ld.shared.u32 %r236, [%r16490] + … 48 loads total, %r235…%r282 … +s13625 L33286: ld.shared.u32 %r282, [%r16812+144] +``` + +48 `ld.shared.u32` = 12 A quads (one `{a0,a2,a1,a3}`-ordered quad each). The +first word's index is + +``` +word = ((laneid<<2) & ~63) | ((laneid<<1) & 24) | ((laneid>>2)&3) + = 64·(laneid>>4) + 8·((laneid>>2)&1) + ((laneid>>2)&3) +byte = smem + 4·word +``` + +and the remaining 47 use the same base plus `+4, +8, +12, +16, +20` and a +divisor-by-24 decomposition of `(laneid&3)|4` / `|8` / `|12` … (`s13156 +mul.wide.u16 %r16486, %rs4437, -21845` / `s13157 shr.u32 %r16487, %r16486, 20` +computes `⌊x/24⌋`, `s13159–s13160` the remainder, `s13161–s13163` select the +byte plane), with the whole block guarded by `setp.gt.u32 %p233, %r17795, 127` +(s13140) and by bounds checks against `(ex, ey)` at s13287–s13295. + +**(e) phase 37's B, s13634–s13687.** + +``` +s13634 L33296: mul.lo.s32 %r17412, %r17795, 384 // %r17795 = %tid.z<<5 +s13635 L33297: cvt.u64.u32 %rd433, %r17412 +s13636 L33298: add.s64 %rd434, %rd2, %rd433 +s13638 L33302: mul.wide.u32 %rd435, %r16825, 16 +s13639 L33303: add.s64 %rd436, %rd434, %rd435 +s13640 L33304: add.s64 %rd409, %rd436, 161280 +s13641 L33306: ld.weak.global.ca.v4.u32 { %r16826,%r16827,%r16828,%r16829},[%rd409] + … 24 loads at 512 stride, last at +173056 … +s13687 L33398: ld.weak.global.ca.v4.u32 { %r16918,%r16919,%r16920,%r16921},[%rd432] +``` + +24 weight fragments at `W + 12288·%tid.z + 16·laneid + 161280 + 512·i`, `i = +0…23` = 12288 bytes = 48 B pairs = phase 37's B. The whole block is inside the +loop `$L__BB1_244` (s13633) which advances `%r17795` by 128 and branches back at +s13847–s13850 while `%r17795 < 128`; with `%r17795 = %tid.z<<5` this is a single +iteration for `%tid.z ≤ 3`. + +**(f) phase 37's C, s13688–s13698.** 4 `ld.global.u32` at +`W + ((laneid*4)&12) + {210432, 210448, 210464, 210480}` → `%r16932, %r16942, +%r17172, %r17182`, each used as `{%rX, %rX}` — a per-column bias replicated over +the 16 rows, seeding the four chains of phase 37. + +**Inputs:** phase 36's 24 D, `%r3216`, `W`, `(ex,ey)`. **Outputs:** the 12 arena +stores (side effect), `%r183…%r194`, phase 37's 12 A quads, 48 B pairs, 4 C +seeds. **Memory:** 12 global stores, 12 shared stores, 48 shared loads, 24 +weight loads, 4 table loads, 2 barriers. + +--- + +### E37 — s13747–s13870: packs + 4 stores to `param+56` + +124 statements. + +**(a) packs, s13747–s13756.** 8 `cvt` + 3 `mov.b32` from phase 37's chain-final +D registers → `%r287` (2 b32), `%rs4534/%rs4535`, `%rs4540/%rs4541`: + +``` +s13747 L33750: cvt.rn.satfinite.e4m3x2.f16x2 %rs4534, %r17143 +s13748 L33753: cvt.rn.satfinite.e4m3x2.f16x2 %rs4535, %r17383 +s13749 L33756: cvt.rn.satfinite.e4m3x2.f16x2 %rs4537, %r17393 +s13750 L33759: cvt.rn.satfinite.e4m3x2.f16x2 %rs4536, %r17153 +s13751 L33761: mov.b32 %r287, {%rs4536, %rs4537} +``` + +**(b) the four stores to `param+56` (`O`), s13757–s13845.** + +``` +s13763 L33783: shr.u32 %r17418, %r16473, 1 // ey>>1 +s13764 L33784: shr.u32 %r17419, %r16472, 1 // ex>>1 +s13765 L33785: shl.b32 %r17420, %r17419, 3 // 8*(ex>>1) +s13766 L33786: mul.lo.s32 %r17421, %r17418, %r17420 +s13767 L33787: shr.u32 %r17422, %r17795, 5 // %tid.z (loop-carried) +s13768 L33788: mul.lo.s32 %r290, %r17421, %r17422 +s13769 L33789: add.s32 %r17423, %r283, %r17416 // y = (%r2>>1) + (laneid>>4) +s13776 L33796: mad.lo.s32 %r17424, %r17420, %r17423, %r290 +s13777 L33797: add.s32 %r17425, %r284, %r17417 // x = (%r1>>1) + ((laneid>>2)&3) +s13783 L33803: add.s32 %r291, %r17426, %r17424 +s13784 L33804: or.b32 %r17427, %r17415, %r291 // + t +s13791 L33812: st.global.v2.u16 [%rd445], {%rs4534, %rs4535} +s13802 L33825: st.global.u32 [%rd448], %r287 +s13836 L33861: st.global.u32 [%rd451], %r288 +s13845 L33872: st.global.v2.u16 [%rd454], {%rs4540, %rs4541} +``` + +`%r283 = %r2>>1` (s13628), `%r284 = %r1>>1` (s13631), `%r17416 = laneid>>4`, +`%r17417 = (laneid>>2)&3`, `t = laneid&3`; the second pair recomputes +`y' = (%r2>>1) + (((laneid>>2)+8)>>2)`, `x' = (%r1>>1) + (((laneid>>2)+8)&3)` +(s13811–s13822) at the same base `%r290`. Extents are **halved** (`ex>>1`, +`ey>>1`) and the destination is `param+56`, not the plane arena. Guards are +`p6 = (y<0)|(y≥(ey>>1))|(laneid>63)|(y-constrained tid.z>127)|(x<0)|(x≥(ex>>1))` +(s13762–s13781), with the same `selp −1` + `bra` skip. + +**(c) loop close and phase 38's operands, s13846–s13870.** + +``` +s13847 L33875: add.s32 %r299, %r17795, 128 +s13848 L33876: setp.gt.u32 %p256, %r17795, -129 +s13849 L33877: mov.u32 %r17795, %r299 +s13850 L33878: @%p256 bra $L__BB1_244 +s13852 L33881: mov.u32 %r17758, _ZZ…E4smem +s13858 L33889: add.s64 %rd455, %rd459, 210688 +s13859 L33891: ld.weak.global.ca.v4.u32 { %r17443,%r17444,%r17445,%r17446},[%rd455] +s13861 L33895: ld.weak.global.ca.v4.u32 { %r17447,…},[%rd456] // +211200 +s13863 L33899: ld.weak.global.ca.v4.u32 { %r17451,…},[%rd457] // +211712 +s13869 L33908: ld.global.u32 %r17465, [%rd463+212224] +s13870 L33909: ld.global.u32 %r17475, [%rd463+212240] +``` + +Three weight fragments at `W + 16*laneid + {210688, 211200, 211712}` = phase +38's 6 B pairs, and 2 `ld.global.u32` at `W + ((laneid*4)&12) + {212224, 212240}` += phase 38's C seeds (each used as `{%rX, %rX}`). + +--- + +### E38 — s13877–s14199: the final epilogue + +323 statements: 4 `st.shared.u32` (staging phase 38's D), 5 `ld.shared.u32` + +1 `ld.shared.v2.u16` (the softmax window), 1 real row max over 5 values, 5 +`ex2.approx.ftz.f32` + 5 `div.approx.ftz.f32`… no — 9 `tex.base.2d.v4.f16.s32`, +3 `sust.b.2d.v4.b16.zero`, 4 `shfl.sync.down.b32`, 3 `ld.param.u64`, 1 `ret`. + +**(a) stage phase 38's D for the softmax, s13877–s13907.** + +``` +s13877 L33952: bar.sync 0 +s13878 L33954: mov.u32 %r17516, %laneid +s13882 L33959: add.s32 %r17521, %r304, %r17746 // g + 16*tid.z +s13883 L33960: and.b32 %r17522, %r17521, 1073741816 // & 0x40000008 +s13884 L33961: or.b32 %r17523, %r17522, %r17518 // | (laneid>>2)&7 +s13885 L33962: mad.lo.s32 %r17524, %r17523, 6, %r305 // *6 + t +s13887 L33964: add.s32 %r306, %r17758, %r17525 // *4 → byte address +s13888 L33965: st.shared.u32 [%r306], %r17496 +s13892 L33970: st.shared.u32 [%r306+16], %r17506 +s13905 L33984: st.shared.u32 [%r308], %r17497 +s13907 L33987: st.shared.u32 [%r308+16], %r17507 +``` + +Four words staged: the phase-38 chain-final pairs `{%r17496,%r17497}` and +`{%r17506,%r17507}`, at a 6-word row pitch (`*6`) plus `t`, in two banks 16 bytes +apart for the two rows `g` and `g+8`. + +**(b) bounds gate, s13909–s13939.** `%r311 = %r17766 + (tid.x&7)` with +`%r17766 = 8*ctaid.x - rs126` (the x origin) and `%r312 = %r17762 + +(tid.x>>3)`; `p265 = (tid.z>1)|((%r312|%r311)<0)|(%r311≥ex)|(%r312≥ey)` (s13931–s13939) +skips the whole softmax/gather. Note `(tid.x + 32*tid.z)` is first reduced mod 8 +into `%r309 = ... & -8` and `%r310 = ... >>3` (s13922–s13928). + +**(c) the softmax window, s13940–s14038.** + +``` +s13946 L34028: ld.shared.u32 %r17554, [%r17703] +s13948 L34030: ld.shared.u32 %r17555, [%r17703+4] +s13950 L34032: ld.shared.u32 %r17558, [%r17703+8] +s13951 L34033: ld.shared.u32 %r17561, [%r17703+12] +s13952 L34034: ld.shared.v2.u16 {%rs4674, %rs4675}, [%r17703+20] +s13954 L34036: ld.shared.u32 %r17575, [%r17703+16] +s13957 L34040: cvt.f32.f16 %f865, %rs4542 +s13958 L34043: mul.ftz.f32 %f893, %f865, 0fBFB8AA3B // -log2 e +s13959 L34044: ex2.approx.ftz.f32 %f894, %f893 +s13960 L34045: add.ftz.f32 %f895, %f894, 0f3F800000 +s13962 L34047: div.approx.ftz.f32 %f866, %f896, %f895 // %f896 = 1.0 +s13964 L34053: max.f16x2 %r17553,%r17554,%r17555 +s13965 L34057: max.f16x2 %r17556,%r17553,%r17558 +s13966 L34061: max.f16x2 %r17559,%r17556,%r17561 +s13968 L34066: max.f16 %rs4544,%rs4545,%rs4546 +s13969 L34070: max.f16 %rs4547,%rs4544,%rs4549 +s13970 L34073: mov.b32 %r17576, {%rs4547, %rs4547} +s13971 L34075: sub.f16x2 %r17562,%r17554,%r17576 +s13974 L34083: mul.ftz.f32 %f897, %f867, 0f3FB8AA3B // +log2 e +s13975 L34084: ex2.approx.ftz.f32 %f869, %f897 +``` + +**This epilogue does have a real row maximum.** `max.f16x2` twice and `max.f16` +twice (s13964–s13969) reduce the *low* halves of the five words +`%r17554, %r17555, %r17558, %r17561, %r17575` (the last through `%rs4549`) into +`%r17576`, which is broadcast to both halves and subtracted +(`s13971: sub.f16x2 %r17562,%r17554,%r17576`). Then a textbook f16 softmax: +`2^((x−max)·log2e)` per element through `ex2.approx.ftz.f32` (s13974–s14029), +the row sum accumulated in f32 (s13979, s13983, s13996, s14009, s14022, s14030), +inverted with `div.approx.ftz.f32 1.0/…` (s14031 +`div.approx.ftz.f32 %f885, %f896, %f914`), and the five f16x2 registers scaled +(s14034–s14038 `mul.f16x2 %r17577…%r17589,%…,%r17591`). + +**(d) the 3×3 texture gather, s14039–s14121.** The nine +`tex.base.2d.v4.f16.s32` (s14058, s14060, s14077, s14079, s14087, s14089, s14102, +s14104, s14117) sample the surface `param+88` (`%rd480`, s14056) at the nine +combinations of `(x−1, x, x+1)` × `(y−1, y, y+1)`: + +``` +s14044 L34234: setp.lt.s32 %p267, %r311, 1 +s14045 L34235: selp.b32 %r17640, 1, %r17706, %p267 // xm +s14051 L34241: selp.b32 %r17609, 1, %r17709, %p269 // ym +s14055 L34245: selp.b32 %r17642, 1, %r17710, %p271 // xp +s14058 L34249: tex.base.2d.v4.f16.s32 {%rs4569,%rs4570,%rs4571,%rs4572}, [%rd464, {%r17640,%r17609}] +``` + +`%rd464…%rd480` are all `mov.u64` copies of `%rd480` (s14057, s14059, …). The +sampled values are combined with the five softmax weights by `fma.rn.f16x2` +(s14062, s14064, s14066, s14081, s14083, s14085, s14091, s14093, s14095, s14106, +s14109, s14112) and the 2×2 accumulator halves folded with `add.f16` (s14114, +s14115, s14116), then one more shared value `%rs4610` folded with `fma.rn.f16` +(s14119–s14121). + +**(e) sigmoid, difference, scale, cross-lane sum, s14122–s14179.** + +``` +s14122 L34385: cvt.f32.f16 %f886, %rs4674 +s14123 L34388: mul.ftz.f32 %f915, %f886, 0fBFB8AA3B +s14125 L34390: add.ftz.f32 %f917, %f916, 0f3F800000 +s14126 L34391: div.approx.ftz.f32 %f887, %f896, %f917 // sigmoid +s14134 L34409: mul.f16 %rs4630,%rs4543,%rs4614 +s14137 L34421: sub.f16 %rs4645,%rs4622,%rs4636 // acc - sigmoid*acc +s14138 L34424: mov.f32 %f892, 0f3E800000 // 0.25 +s14145 L34444: mul.f16x2 %r17658,%r17659,%r17660 // * 0.25 +s14152 L34463: shfl.sync.down.b32 %r17662,%r17658,%r17683,%r17665,%r17693 // delta 1 +s14153 L34467: add.f16x2 %r17667,%r17658,%r17662 +s14158 L34478: shfl.sync.down.b32 %r17671,%r17667,%r17691,%r17674,%r17693 // delta 8 +s14159 L34482: add.f16x2 %r17676,%r17667,%r17671 +s14168 L34506: add.f16 %rs4657,%rs4651,%rs4656 +s14177 L34530: add.f16 %rs4663,%rs4657,%rs4662 +``` + +`sigmoid(v) = 1/(1 + 2^(−log2e·v))` on two more shared values +(`%rs4674/%rs4675`, the v2.u16 at `+20`), then three `acc − sigmoid·acc` +differences scaled by `0.25` (f16), then a two-step partial warp reduction: +`shfl.sync.down` delta 1 (`%r17683`, s13956) then delta 8 (`%r17691`, s13949), +each followed by an `add.f16x2`; the scalar path repeats the same two deltas with +`add.f16` (s14168, s14177). Segmask `%r17665`/`%r17674` is `(WARP_SZ<<8)−8192|31` += 31 in both, membermask `%r17693 = −1`: a partial (not five-step) reduction. + +**(f) the three surface writes, s14178–s14199.** + +``` +s14178 L34533: ld.param.u64 %rd484, [%rd491+120] +s14179 L34534: ld.param.u64 %rd487, [%rd491+128] +s14180 L34535: shl.b32 %r17697, %r311, 3 +s14181 L34537: sust.b.2d.v4.b16.zero [%rd482, {%r17697,%r312}], {%rs4639,%rs4642,%rs4645,%rs4676} +s14182 L34540: sust.b.2d.v4.b16.zero [%rd484, {%r17697,%r312}], {%rs4630,%rs4633,%rs4636,%rs4677} +s14183 L34542: and.b32 %r17724, %r313, 1 +s14185 L34544: mov.pred %p279, 0 +s14186 L34545: xor.pred %p280, %p278, %p279 +s14187 L34546: @%p280 bra $L__BB1_260 +s14191 L34551: shl.b32 %r17729, %r17728, 2 +s14192 L34552: and.b32 %r17725, %r17729, -8 +s14197 L34558: sust.b.2d.v4.b16.zero [%rd487, {%r17725,%r17726}], {%rs4678,%rs4679,%rs4663,%rs4681} +s14199 L34562: ret +``` + +Three four-channel b16 surface writes to `param+112`, `param+120` and +`param+128`; the third is taken only when `(x|y)` is odd +(`and.b32 %r17724, %r313, 1` at s14183, `@%p280 bra`) and stores +`mov.u16 %rs4681, 0` (s14196) in its fourth channel. `%r17725 = (x<<2) & −8`, +`%r17726 = y>>1` for that one, versus the plain `(x<<3, y)` of the first two. + +**Inputs:** the four staged phase-38 D words, `%rd480` (texture), `(ex,ey)`, +`%r1/%r2/%tid.z/%tid.x`, constants `0fBFB8AA3B`, `0f3FB8AA3B`, `0f3F800000`, +`0f3E800000`. **Outputs:** none (the kernel returns). + +--- + +## 4. The plane arena (`param_0+48`) and the other `ld.param` buffers + +The four `ld.param` that matter, quoted verbatim: + +``` +s4 L1032: add.s64 %rd1, %rd8, 80 +s5 L1033: ld.param.v2.u16 {%rs126, %rs127}, [cuda_dldn_engine_swin_enc2_kernel_param_0+80] +s8 L1036: ld.param.u64 %rd2, [cuda_dldn_engine_swin_enc2_kernel_param_0+40] +s14 L1042: ld.param.v2.u32 {%r322, %r323}, [cuda_dldn_engine_swin_enc2_kernel_param_0] +s17 L1045: ld.param.u64 %rd10, [cuda_dldn_engine_swin_enc2_kernel_param_0+8] +s12865 L32471: ld.param.u64 %rd383, [%rd1+-32] // = param_0 + 48 +s13632 L33293: ld.param.u64 %rd6, [%rd492+56] // = param_0 + 56 +s13941 L34023: mov.b64 %rd491, cuda_dldn_engine_swin_enc2_kernel_param_0 +s13953 L34035: ld.param.u64 %rd482, [%rd491+112] +s14056 L34246: ld.param.u64 %rd480, [%rd491+88] +s14178 L34533: ld.param.u64 %rd484, [%rd491+120] +s14179 L34534: ld.param.u64 %rd487, [%rd491+128] +``` + +| offset | role | read by | written by | +|---|---|---|---| +| 0 | `(ex, ey)` v2.u32 | s14 (`%r322/%r323`), s13138 (`%r16472/%r16473`) | — | +| 8 | **input image** `I` | prologue: 24 × `ld.global.v2.u16 [%rd12]` (s176, s328, … s3316) via `%rd4` | — | +| 40 | **weight image** `W` | every weight load, §1.1 | — | +| 48 | **plane arena** `S` | **never** | 12 × `st.global.u32` (s12891…s13009) | +| 56 | phase-37 output buffer `O` | **never** | 4 stores (s13791, s13802, s13836, s13845) | +| 80 | patch origins v2.u16 | s5 (`%rs126/%rs127`), reused at s13910–s13915 | — | +| 88 | input texture | 9 × `tex.base.2d.v4.f16.s32` (s14058…s14117) | — | +| 112, 120, 128 | output surfaces | — | 3 × `sust.b.2d.v4.b16.zero` (s14181, s14182, s14197) | + +**Is anything generated into the plane arena?** Yes, exactly one thing: +E36(b) writes phase 36's requantised 16×96 output — 12 `st.global.u32`, 4 bytes × +32 lanes × 12 = **1536 bytes per block** — into `S` at +`4·(8·ex·y + 8·x + d)`. Nothing in the entry ever *reads* `param_0+48`: + +``` +$ grep -n '%rd5\b\|%rd383' 0015-PREPASS_ENTRYPOINT_NAME.ptx +32471:ld.param.u64 %rd383, [%rd1+-32]; +32472:cvta.to.global.u64 %rd5, %rd383; +32499:add.s64 %rd385, %rd5, %rd384; + … 11 more add.s64 %rd5, all feeding st.global.u32 … +``` + +`%rd5` appears only in the twelve `st.global.u32` (there is **no** `ld.*` with +`%rd5` as base) and `%rd383` only at s12865. So the arena write is a pure +side effect for the next launch; the same 12 registers are *also* consumed +inside this kernel via the shared staging of E36(c). + +The one `surface-write`-style marker the brief attributes to a "phase 30 +epilogue" (`surface-write:32@s25247`) has no counterpart here: s25247 does not +exist (the entry ends at s14199) and **E30 is a 60-statement load/pack epilogue +with no store of any kind** (§3/E30; verified by enumerating every `st.*` in the +entry — the only `st.global` are s12891–s13009 and s13791–s13845, and the only +`st.shared` are the prologue's six, E8's four, E36's twelve and E38's four). +That marker belongs to a different linearisation — see §6 U6. + +## 5. Cross-lane reductions worth calling out + +Introduction: the entry contains exactly **32** `shfl.sync.bfly.b32` and **4** +`shfl.sync.down.b32`; 8 of the former are in the prologue, 16 in E7, 4 in E12 and +4 in E38. Each butterfly uses the shared delta operands `%r3037 = 1` (s3318), +`%r3046 = 2` (s3611) and membermask `%r3048 = −1` (s3604), with a segmask built as +`((WARP_SZ<<8) − 8192) | 31` = 31. + +1. **The prologue's RMS reduction** (s3605, s3612, s3621, s3627, s3637, s3643, + s3652, s3658): four butterfly pairs over lane bits 0 (`%r3037`) and 1 + (`%r3046`), each followed by `add.f16x2` and a final `add.f16` + (`s3646 L5446: add.f16 %rs516,%rs517,%rs518`) — four row sums from the + prologue's 96 squared input values. +2. **E7's row sums** (s7223–s7344): 16 `shfl.sync.bfly.b32` = eight such pairs, + each followed by `add.f16x2` and a final `add.f16` of the two halves — 8 row + sums over 96 columns of the score window. +3. **E12's RMS reduction** (s9308–s9330): the same two butterfly steps + (`delta 1` at s9308, `delta 2` at s9314) over the four lanes with equal + `laneid>>2`, folding the 96 squares of one row; then `add.f16` of the two + column halves (s9317, s9332). This is the whole cross-lane traffic of the + norm. +4. **E36's and E38's `bar.sync` pairs** (s8910/s8968, s13013/s13136, + s13877/s13920): block-wide, guarding the shared tiles. The seventh + `bar.sync` is the prologue's, s4588. +5. **E38's partial lane sums** (s14152–s14177): four `shfl.sync.down.b32`, two + on the f16x2 path (`delta 1` = `%r17683`, `delta 8` = `%r17691`) and two on the + scalar path, segmask 31, membermask −1. + +There is no `red.*` or `atom.*` anywhere in the entry, and `movmatrix` occurs only +in E7 (the 48 of §3/E7(f)). + +## 6. Uncharacterised + +**U1. The (n,k) indexing of the 512-byte B tiles of phases 13…35 and 37.** +The *geometry* of these phases is not in doubt: the chain fixes `m·k = |A|`, +`n·k = |B|`, `m·n = chains`, `k =` chain length, so phase 13 (and 15…35) is +`m=1, n=4, k=3` → M=16, N=32, K=96 and phase 37 is `m=1, n=4, k=12` → M=16, +N=32, K=384 (§2.2); every row then satisfies `mma = (M/16)(N/8)(K/32)`. What I +cannot derive is *which* (n-tile, k-step) each 512-byte tile holds. For phase 13 +the 12 B pairs sit in six tiles at `W + 86592 + 512*i` (E12's six loads), and the +emitted chains pair them as chain 0 = tiles {0,2,4} at byte `+0`, chain 1 = tiles +{0,2,4} at byte `+8`, chain 2 = tiles {3,4,5} at `+0`, chain 3 = tiles {3,4,5} at +`+8` (mma s9820/s9822/s9824, s9821/s9823/s9825, s9826/s9828/s9830, +s9827/s9829/s9831). If a chain is one n-tile's three k-slices, its three tiles +would have to be the same tile — they are not; so either the weight image's tile +stride is not the `(n,k)`-major layout `rr_layer_spec.py` assumes +(`:189–192`, `:491–498`), or `m·n` counts something other than the chains. The +register/byte evidence above is exact and sufficient to reproduce the *operands*; +only their (n,k) naming is unresolved. *Missing:* the `_NAME_prep` permutation +that built the weight image, or a run of the kernel with a weight-image dump. + +**U2. The identity of the 12288-byte score bias.** Phase 7 adds the f16 table +at `W + 6336 … W + 18624` as its mma C operand, one value per element of the +64×96 score, tile-major at 512 bytes per output tile (§3/E6(a)). Whether it is a +relative-position bias, a learned score bias, or something else cannot be decided +from the PTX: it is an opaque blob in a permuted weight image. *Missing:* the +weight image's layout description (the `_prep` permutation) or the parameter +names from the model file. + +**U3. E36(c)'s shared staging produces 4-way write collisions.** The word index +is `(2·%tid.z)·32 + (laneid & 28)` for the first six stores and +`((2·%tid.z) + ((laneid>>2)+8)>>3)·32 + (((laneid>>2)+8)<<2 & 28)` for the last +six, plus `+256` for the alternating pair. `laneid & 28` takes only the eight +values 0,4,…,28, so lanes 0…3, 4…7, … all write the *same* word, with *different* +data (`%r183` vs `%r184` are the two halves of the same D pair, and `%r185` is +the other half of `%r183`'s source). Either the four colliding lanes are +guaranteed to hold equal data in this kernel's inputs (unlikely — they are +distinct e4m3 packs of distinct D registers) or the staging is racy and the +issued values come from whichever lane wins. I could not decide which from the +PTX. *Missing:* a run with a shared-memory dump, or the high-level source of the +phase-36→37 hand-off. (The corresponding *read* side, E36(d), is 48 +`ld.shared.u32` with the swizzle of §3/E36(d) and is complete.) + +**U4. E8's shared slot layout.** E8 stages four words at +`smem + 2048*%tid.z + 16*laneid + {0,512,1024,1536}` (s8911–s8967), but phases 9, +10, 11 read single quads at `smem + 16*laneid + {2048, 4096, 6144}` (s8974, +s9094, s9125) and phase 12 at `smem + %tid.z*512 + 16*laneid` (s8969–s8974 uses +`%tid.z*512` for phase 9's *other* read). For `%tid.z = 0` the written slots are +{0,512,1024,1536} while phase 9 reads 2048, phase 10 4096, phase 11 6144 — +disjoint. The union over `%tid.z ∈ {0,1,2,3}` of the writes is the 16 slots +{0…15}, which *does* contain 4, 8 and 12 (i.e. the reads 2048/4096/6144 are +slots 4/8/12). This is consistent only if `blockDim.z = 4` and the four z-planes +write the block's shared tile cooperatively; the module has **no `.maxntid` +declaration** so I cannot confirm the launch shape. *Missing:* the harness's +launch configuration (gridDim/blockDim), or whatever `.maxntid`/`.reqntid` the +unstripped cubin carries. + +**U5. The `%tid.z` weight-slab strides are mutually inconsistent.** +Phases 1–7 index the weight image through `W + 21504*%tid.z + 16*laneid` +(s4589–s4590, s4613–s4615); phases 9–36 index it through `W + 16*laneid` with no +`%tid.z` term at all (s8976–s8978); phase 37 through `W + 12288*%tid.z + +16*laneid` (s13634–s13639); phase 38's bias again without a `%tid.z` term +(s13688–s13694). Since phase 9's very first weight offset (18624) is smaller +than the 21504-byte stride of phases 1–7, the two regions overlap for `%tid.z ≥ 1` +whatever the value of `%tid.z`. The addresses are as quoted and are sufficient +to reproduce each load; the *reason* they differ is not derivable from the PTX. +*Missing:* the launcher's `gridDim.z` and the weight-image builder. For +`%tid.z = 0` the touched byte range of the image is `[192, 212244)` (see below). + +**Weight-image extent.** Relative to the pointer named in U5 (i.e. excluding any +`%tid.z` term and the `16*laneid` lane stride): + +* the highest weight-fragment offset is `173056 + 16` (phase 37's last + `ld.weak.global.ca.v4.u32`, s13687, `add.s64 %rd432, %rd436, 173056`); +* the highest scalar-table offset is `212240 + 4` (phase 38's second C seed, + `ld.global.u32 [%rd463+212240]`, s13870), and `%rd463 = %rd3 + + ((laneid*4)&12)` so the true last byte is `212240 + 12 + 4 = 212256`. + +**The weight image therefore spans at least 212256 bytes**, and per block the +touched range is `[16*laneid + 192, 16*laneid + 212256)`. Per-`%tid.z` slabs add +`21504*%tid.z` (phases 1–7) and `12288*%tid.z` (phase 37) on top (U5). + +**U6. The brief's stale landmarks.** Three statement indices given with this +ticket do not exist in this linearisation: `s25247` (the entry has 14199 +statements), and the range markers "phase 30's epilogue has +`surface-write:32@s25247`". `s12891` (`surface-write:12`) and `s13791` +(`surface-write:4`) do match, and `s13959` / `s14058` match the reported +`softmax:12` and `texture-read:9`. So only the `s25247` landmark is foreign; it +is most likely from an enc0-era numbering. *Missing:* the numbering that +produced `s25247`, if it is meant to be in this layer. + +**U7. The semantic names of the per-column tables.** `W + 0 … 192` (the +prologue's norm gain, 12 loads at `+0,16,…,176`: s4198–s4209), `W + 86208 … 86400` +(E8's residual add), `W + 86400 … 86592` (E12's norm gain), `W + 92800 … 92992` +(E13's residual add), and the four-word biases at `89664`, `96064`, `102272`, …, +`158144`, `210432`, `212224` are all read with the same +`W + ((laneid<<2)&12) + off` pattern and are 96 f16 or 32 f16 wide. Their *roles* +are computable from the arithmetic (gain in the two RMS norms, additive per-column +bias elsewhere) but their *names* are not. *Missing:* the weight-image layout or +the model's parameter names. + +**U8. Phase 37's K = 384 against a 96-wide A.** The chain gives phase 37 +`m=1, n=4, k=12` → M=16, N=32, K=384, and 48 mma (verified: 4 chains of 12, each +step a distinct A quad and a distinct B pair). But the A operand is 12 quads = +48 registers read from a shared tile whose source (E36(c)) stages only 12 words +per lane, and E36(a) packs only 12 of phase 36's 24 D registers — i.e. one of the +twelve 16×8 n-tiles of phase 36's output is staged per staged word. The +mechanical relation between the 12 staged words, the 48 A registers, and a +384-deep k axis is not determined without the swizzle's intent. *Missing:* the +high-level structure of the phase-36→37 merge, or a shared-memory dump. + +**U9. The residual operand added into phase 9's C.** E8(d) adds a per-column +table (at `W+86208`) to 48 f16 values that are the halves of the prologue's +quantised-input registers `%r2798…%r2845`. The mechanics are unambiguous (the +defining `mov.b32 {%rs1100, %rs1103}, %r2798` at s3366 has no successor +anywhere in the entry, and `%r2798` is `cvt.rn.f16x2.e4m3x2 %r2798, %rs128` of +the input element loaded at s176). What is *not* derivable from the PTX is +whether this really is a semantic skip connection from the block input (which +would require the input patch's per-lane layout to coincide with an mma C +operand), or whether the input patch registers happen to alias a value the +compiler could have recomputed from phase 8's D. *Missing:* the high-level +source, or a numeric run showing whether phase 9's output equals +`pack(D8)·W9 + table + input`. + +## 7. Quick acceptance index + +| requirement | where | +|---|---| +| phase table for all 38 phases, M/16·N/8·K/32 == mma checked, mismatches named | §2.2: the identity holds on **all 38** once the tool's `M = 16·\|A\|`, `N = 8·\|B\|` are divided by `k = K/32`; the flagged rows 8, 13…35, 37, 38 are re-derived there (the tool's `K` column is right, its `M`,`N` and `full`/`band` label wrong) | +| weight image extent | §6 U5 (212256 bytes, per-block) | +| phases that read no weight operand | §2.2 and §3/E6(b), E7(f): phases 7 and 8 — phase 7's A and B operands both come from E6's packs of phase 5's D, with A frag 0 **bit-identical** to B frag 0 (s4853 vs s4925) and the later ones the same data with the two halves swapped (s4865 vs s4937); phase 8's A is E7's probability packs (s8720 ff.) and its B is E7's `movmatrix` transposes of phase 6's D (s8598 ff.) | +| every epilogue named | §2.1 (38 rows), §3 (38 `###` sections) | +| the norms: mean-subtracting LN or RMS? | §3/E12: raw sum of squares, only `2⁻¹³` added, no mean and no `1/N`; prologue (s3812 ff.) identical structure → **both are RMS norms**, with a per-column gain and the bias deferred to the next GEMM's C | +| attention: does the score have a row max? | §3/E7(b),(c): **no** — all 96 `max.f16x2` are the clamp lower bound `−0.55615234375`, all 96 `min.f16x2` the upper; the only warp shuffles are the 16 `shfl.sync.bfly` row sums | +| attention: the score's bias operand | §3/E6(a): the mma C operand, 48 distinct pairs from the 12288-byte f16 table at `W+6336`, tile-major `512*(4*(n>>1)+m)`, one value per score element; identity → §6 U2 | +| activations | §3/E13(a), E15, E17…E33: `out = x·(0.5 + y·(0.412109375 − 0.0810546875·|y|))`, `y = clamp(x,±2)` — the **same clamped cubic as enc0's E13**, byte-identical constants | +| patch merge / surface writes | §3/E36(b) (12 stores to `param+48`), E37(b) (4 stores to `param+56`), E38(f) (3 `sust` to `param+112/+120/+128`) | +| final texture-reading epilogue | §3/E38: 4 staged words, real 5-value row max, softmax, 9 `tex.2d`, 3×3 `fma` gather, sigmoid, 0.25 scale, two `shfl.sync.down` steps | +| per-launch table into the plane arena | §4: exactly one — E36's 1536 bytes per block; `param+48` is written and never read | +| cross-lane reductions | §5 | +| uncharacterised | §6 U1–U9 | diff --git a/kernels/rr/rrswin_enc3.hip b/kernels/rr/rrswin_enc3.hip new file mode 100644 index 0000000..df7fe8b --- /dev/null +++ b/kernels/rr/rrswin_enc3.hip @@ -0,0 +1,656 @@ +// Native replacement for the Ray Reconstruction denoiser's third Swin +// encoder, cuda_dldn_engine_swin_enc3_kernel (nvngx_dlssd.dll 310.7). +// +// STATE: phases 1..10 are implemented and bit-exact against the debug oracle +// (see "Ground truth" below): stages 1,2,3,4,6,7,8 verified byte-identical with +// a proven control. Phases 11..48 are NOT implemented -- their accumulators are +// zero -- so the layer's three output surfaces still differ from the translated +// reference and the four accumulators handed back through the arena are zero. +// The missing work is the whole block §3 of rrswin_enc3_epilogues.md describes +// after E10: E11..E13 (shared re-read), E14 (row-RMS norm), E15/E17 (clamped +// cubic activation), E16/E18 (table+residual, re-pack), the 15 repeats of the +// P15..P46 MLP pairs, then E46 (arena scatter), E47 (surface scatter) and E48 +// (softmax, 3x3 texture gather, three sust.b surface writes). +// +// --------------------------------------------------------------------------- +// The kernel is one warp per (8x8 token patch, wave): grid (21, 13, 1), +// block (32, 1, 4), four waves per block. The waves are *not* redundant: +// wave z reads its own 24576-byte slice of the prepared weight image (line 9765 +// `mul.lo.s32 %r21780, %r12, 12288` -> `mul.wide.u32 %rd406, %r21780, 2`), +// while all four read the *same* staged A operands out of shared memory (the +// staging is a cooperative cross-wave shuffle, lines 9614-9763: wave z stages +// the fragments of m-tile z and z+4, the reads at 9771-9794 carry no %tid.z +// term, and the `bar.sync 0` at 9764 separates the two). +// +// The PTX this file replaces is kernels/extracted/rr/0016-PREPASS_ENTRYPOINT_NAME.ptx. +// kernels/rr/swin_enc3_recipe.py's recipe keeps NVIDIA's prologue (lines +// 1-9811: the texture/plane reads, the A staging, the C register setup) and +// the epilogue (from line 41984: E48's texture gather and surface stores) and +// replaces the 936 mma of the 48 phases with the call below. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so +// tex_common.h's helpers and ZLUDA's own device functions are available. +// Compiled with -nogpuinc, so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinEnc3Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinEnc3Params) == 144, "parameter block"); + +enum : int +{ + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // plane arena pointer, as make_ptx.py's debug splice reads it +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (VERIFIED on all 1024 (n, k) pairs of a tile; the 64*(n&7) term is what keeps +// columns 16..31 from silently reading as zero.) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and +// laneid ^ 2): the two shfl.sync.bfly steps the PTX's reductions perform. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +// add.f16x2 on a packed pair (the PTX's reduction and requantisation steps) +DEVF uint32_t pair_add(uint32_t a, uint32_t b) +{ + return __builtin_bit_cast(uint32_t, __builtin_bit_cast(hv2, a) + __builtin_bit_cast(hv2, b)); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// One stem GEMM: 96 rows (six m-tiles of 16) x 32 columns, K=32, f16 output. +// +// A lane's four A registers hold, for each of its two rows, the eight e4m3 +// values of k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3 of register 0) and of +// k + 8 (register 2); the four lanes that differ in t hold the four disjoint +// eighths of the 32 k's, so two butterfly steps broadcast the other three +// eighths in. The B operand is read from the weight image (waddr) for the lane's +// own two columns of each n-tile. The dot product runs in f32 and is rounded to +// f16 once, which is what the translated mma does: e4m3 x e4m3 products are +// exact and 32 of them sum exactly in f32, so this reproduces the translated +// kernel bit for bit. +// +// `cd` is the phase's C operand, six m-tiles x two row halves x four n-tiles of +// packed f16 pairs (48 words), or null for the chain's first phase (whose C is +// the zero register %r10141). `d` is written in the same layout. +DEVF void stem_gemm(const uint32_t (*as)[4], const uint8_t* w, int base, + const uint32_t* cd, uint32_t* d) +{ + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + for (int nt = 0; nt < 4; ++nt) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + for (int mi = 0; mi < 6; ++mi) { + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + const uint32_t p0 = as[mi][2 * reg + row]; + uint32_t p[4]; + p[0] = p0; + p[1] = bfly1_bits(p0); + p[2] = bfly2_bits(p0); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + // the accumulator is d[mi][row][nt] in memory order, so the + // (mi, row, nt) entry sits at (2*mi + row)*4 + nt + const uint32_t seed = cd ? cd[(2 * mi + row) * 4 + nt] : 0u; + d[(2 * mi + row) * 4 + nt] = pair_of((half_t)(acc[row][0] + h2f(seed)), + (half_t)(acc[row][1] + h2f(seed >> 16))); + } + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_enc3_recipe.py's debug +// recipe: with D4R_RRSWIN_DEBUG=w (n = 1..48) the splice keeps NVIDIA's +// whole body and stores that phase's accumulator registers into the plane arena +// (param_0+48) at D4R_RRSWIN_DEBUG_BASE, and the launch dump then holds the +// translated values for a block/wave/lane. Built with +// -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this +// body stores the same registers of its own phase n in the same order, so the +// two payload regions compare byte for byte. +// +// Two things about that arena are measured, not assumed, and both silently +// void a comparison if you get them wrong: +// +// * param_0+48 is a *window* inside the 65,945,600-byte block the launcher +// dumps under the name arg008 (the replay manifest gives arg048 = +// alloc+37,683,200), so the payload is read from the arg008 file at +// 37,683,200 + base, not at base. +// * the base must clear the arena bytes the rest of the frame rewrites. At +// 524,288 the payload window comes back byte-identical to the plain +// translated run -- something later in the frame overwrites arena bytes +// 524,288..2,473,984 -- so a "MATCH" there is ambient memory. 4,194,304 is +// above that, and 4 MiB + 64 * 16384 stays inside the arena. The shared +// default of 46,000,000 is past the end of enc3's allocation entirely. +// +// So every verdict below is stated with its control: the oracle's window has to +// differ from the same window of a reference run (same layer, translated, no +// D4R_RRSWIN_DEBUG) before a match means anything. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 4194304 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + // Four waves per block, and each reads a different slice of the weight image, + // so the oracle's per-block slot carries %tid.z too: block = + // (ctaid.x + 21*ctaid.y)*4 + tid.z, first 64 of those. + const uint32_t block = (__builtin_amdgcn_workgroup_id_x() + + 21u * __builtin_amdgcn_workgroup_id_y()) * 4u + + (uint32_t)__builtin_amdgcn_workitem_id_z(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot, swin_enc3_recipe.debug_slot: 32 lanes x n x 4 bytes, at + // least 8192, rounded up to a power of two + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + D4R_RRSWIN_DEBUG_BASE + + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// stage registers in the oracle's order: the phase's mma in order, each writing +// the (row g, row g+8) f16 pair. +DEVF void stage_regs(const uint32_t* d, uint32_t regs[48]) +{ + int i = 0; + for (int mi = 0; mi < 6; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[(2 * mi + 0) * 4 + nt]; + regs[i++] = d[(2 * mi + 1) * 4 + nt]; + } + } +} + +// --------------------------------------------------------------------------- +// The attention window: phases 9 and 10. +// +// Phase 9 (64x96x32, the score GEMM Q·Kᵀ) takes *both* operands from P7's +// accumulators: its four A fragments are the query rows 16*mi + g + 8*row +// (mi = 0..3) and its twelve B fragments the key rows 16*(nb>>1) + 8*(nb&1) + g +// (nb = 0..11, i.e. all six m-tiles of the 96-row stem output). That is the +// same row split enc0's phase 5 uses, and the packs are built the same way: +// word 0 of a row packs n-tiles 0 and 2, word 1 packs 1 and 3, and the four +// lanes t = 0..3 of a group hold the four disjoint eighths of the 32 k's, which +// the two butterfly steps bring together. +// +// A lane therefore owns one row group of the queries and one of the keys and +// can only dot each with itself, so every lane *publishes* its two key words +// per n-tile into the shared arena -- 12 x 2 x 32 lanes = 768 words, which +// fits the wave's 3200-byte share of the 12800-byte arena -- and then forms the +// dots its own D registers hold: query row 16*mi + g + 8*row against key rows +// 16*(nb>>1) + 8*(nb&1) + 2t + c, published by the lanes 4*(2t + c) + 0..3. +// +// The C operand is the 11792-byte f16 score bias at weight bytes 8448..20240, +// 24 tiles of 512 bytes: the seed of (m-tile, n-tile) is in tile +// 4*(nb>>1) + mi, at the lane's 16-byte record + 8*(nb&1) + 4*row. (s6368: +// `add.s64 %rd94, %rd425, 8448` with %rd425 = the wave's slice + 16*laneid.) + +// the f16 the PTX's literals carry: 0f3C8CCB50, 0dBFE1CC0000000000, 0f3F6D6000, 0f3FB00000 +DEVF half_t hf16(uint16_t bits) +{ + return __builtin_bit_cast(half_t, bits); +} + +DEVF hv2 hv2_of(uint32_t p) +{ + return __builtin_bit_cast(hv2, p); +} + +DEVF uint32_t u32_of(hv2 v) +{ + return __builtin_bit_cast(uint32_t, v); +} + +// ZLUDA's own rcp.approx.ftz.f32 helper: calling it is what makes the reciprocal bit-exact. +extern "C" __attribute__((device)) float __zluda_ptx_impl_rcp_approx_f32(float); + +// the e4m3 code of one f16 (cvt.rn.satfinite.e4m3x2.f16x2 of a pair of equal halves) +DEVF uint32_t q8(half_t v) +{ + return e4m3x2(pair_of(v, v)); +} + +// the f16 at (row, col) of the stem's 96x32 block, col = 8*n-tile + 2t + c +DEVF half_t dcell(const uint32_t* d, int row, int col) +{ + const uint32_t p = d[(2 * (row >> 4) + ((row >> 3) & 1)) * 4 + (col >> 3)]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +// the lane's two e4m3-packed words for row r: word 0 packs n-tiles 0 and 2, +// word 1 packs 1 and 3 +DEVF void row_words(const uint32_t* d, int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// out[i][m]: word i as lane t^m holds it, which is what the mma pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + +// word i at butterfly index m (0..3), without the dynamic index into the pair +DEVF uint32_t word_at(const uint32_t out[2][4], int i, int m) +{ + return m == 0 ? out[i][0] : (m == 1 ? out[i][1] : (m == 2 ? out[i][2] : out[i][3])); +} + +// the 32-term dot product of two packed operand word pairs, in the mma's own k order +DEVF float dot32(const uint32_t a[2][4], const uint32_t b[2][4]) +{ + float acc = 0.0f; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + acc += e4m3_to_f32((a[i][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((b[i][m] >> (8 * j)) & 0xffu); + } + } + } + return acc; +} + +// E9(a), one element: the scale, the clamp, the two clamped-cubic fma pairs and the trick +// that moves the mantissa into the exponent field ((u << 5) & 0x7FE07FE0 over the pair). +DEVF uint32_t expval_pair(uint32_t score) +{ + hv2 m = hv2_of(score) * __builtin_bit_cast(hv2, pair_of(hf16(0x2466), hf16(0x2466))); + m = __builtin_elementwise_max(m, __builtin_bit_cast(hv2, pair_of(hf16(0xb873), hf16(0xb873)))); + m = __builtin_elementwise_min(m, __builtin_bit_cast(hv2, pair_of(hf16(0x3873), hf16(0x3873)))); + const hv2 tt = __builtin_elementwise_fma(m, -m, + __builtin_bit_cast(hv2, pair_of(hf16(0x3b6b), hf16(0x3b6b)))); + const uint32_t u = u32_of(__builtin_elementwise_fma(m, tt, + __builtin_bit_cast(hv2, pair_of(hf16(0x3d80), hf16(0x3d80))))); + return (u << 5) & 0x7fe07fe0u; +} + +// E9(a)-(c), one row: the twelve exponent pairs, the in-lane sum tree +// (((e0+e2)+(e4+e6))+(e8+e10)) + (((e1+e3)+(e5+e7))+(e9+e11)), the two butterfly steps +// that finish the row's 96 columns, the two halves' add, the reciprocal and the +// twelve products. There is no row maximum in this epilogue (the `max.f16x2` +// of E9(a) is the clamp), which the oracle's stage 9 confirms. +DEVF void row_probs(const uint32_t* d9, int mi, int rh, uint32_t prob[12]) +{ + hv2 ev[6], eo[6]; +#pragma unroll + for (int i = 0; i < 6; ++i) { + const uint32_t a = d9[(2 * mi + rh) * 12 + 2 * i]; + const uint32_t b = d9[(2 * mi + rh) * 12 + 2 * i + 1]; + ev[i] = hv2_of(expval_pair(a)); + eo[i] = hv2_of(expval_pair(b)); + } + const hv2 even = ((ev[0] + ev[1]) + (ev[2] + ev[3])) + (ev[4] + ev[5]); + const hv2 odd = ((eo[0] + eo[1]) + (eo[2] + eo[3])) + (eo[4] + eo[5]); + hv2 s = even + odd; + s = s + hv2_of(bfly1_bits(u32_of(s))); + s = s + hv2_of(bfly2_bits(u32_of(s))); + const uint32_t p = u32_of(s); + // the PTX broadcasts the f16 sum of the two halves (add.f16) and takes + // cvt.f32.f16 of it: the value, not its bits + const half_t r = (half_t)__zluda_ptx_impl_rcp_approx_f32((float)(half_lo(p) + half_hi(p))); + const uint32_t rcp = pair_of(r, r); +#pragma unroll + for (int i = 0; i < 6; ++i) { + prob[2 * i] = u32_of(ev[i] * hv2_of(rcp)); + prob[2 * i + 1] = u32_of(eo[i] * hv2_of(rcp)); + } +} + +// --------------------------------------------------------------------------- +// The native body. +// +// Nothing crosses the cut in: the 24 staged A fragments are still in the shared +// arena when the splice is taken (their last ld.shared is line 9794 and the +// arena's next writer is E10 at line 22563), so the body reads them itself at +// `smem + 16*laneid + 512*k`. The B operands come from the weight image and +// the C seeds are zero or a previous phase's accumulator, so both are +// recomputed here. +// +// Phase 48's four accumulators cross the cut back through shared memory, not +// `call.uni`'s return parameters: ZLUDA lowers those to the function's LLVM +// return type (emit.rs's emit_call makes one value, or an +// get_or_create_struct_type struct for several, and distributes them with +// LLVMBuildExtractValue), so there is no .param-space object and no pointer is +// formed -- the callee reads 0x0 in all four slots, and a 4 x i32 C++ struct +// return is an sret pointer, a different LLVM signature that will not link. +// `scratch` is the base of the arena (`.shared 12800 bytes`), dead after the cut +// except for the window the splice itself reads back, 16 bytes apart per lane. +extern "C" __attribute__((device)) void d4r_swin_enc3( + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t z = (uint32_t)__builtin_amdgcn_workitem_id_z(); + const uint8_t* wz = w + z * 24576u; // the wave's own weight slice + + // the 24 staged A fragments: four shift groups of six m-tiles, read at + // `smem + 16*laneid + 512*k` exactly as the PTX does at lines 9771-9794 + const lds_u32* sm = (const lds_u32*)(uintptr_t)scratch; + uint32_t as[24][4]; +#pragma unroll + for (int k = 0; k < 24; ++k) { +#pragma unroll + for (int i = 0; i < 4; ++i) { + as[k][i] = sm[4 * lane_id() + 128 * k + i]; + } + } + + // ---- the stem: two chains of four phases, P1..P8 ------------------- + // + // Phase p (1-based) uses chain (p-1)&1 and group (p-1)>>1. Its B block sits + // at 256 + 1024*group + 4096*chain from the wave's slice -- the eight + // `add.s64 %rdNN, %rd409, ` of the prologue and E1..E7 give exactly + // P1 256, P2 4352, P3 1280, P4 5376, P5 2304, P6 6400, P7 3328, P8 7424 -- + // and its m-tile mi takes A fragment 4*mi + group, i.e. the four groups are + // four shifted views of one 96-row tile (the shift structure of note U6). + // + // Each chain accumulates: P3's C is P1's D pair for the same (mi, nt) + // (s6186 `C={%r4296,%r4297}`, P1's first mma), P5's is P3's, P7's is P5's, + // and P1's and P2's C is the zero register %r10141. + uint32_t d[2][48] = {}; + for (int chain = 0; chain < 2; ++chain) { + for (int g = 0; g < 4; ++g) { + uint32_t a[6][4]; +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { +#pragma unroll + for (int i = 0; i < 4; ++i) { + a[mi][i] = as[4 * mi + g][i]; + } + } + stem_gemm(a, wz, 256 + 1024 * g + 4096 * chain, d[chain], d[chain]); +#if D4R_RRSWIN_DEBUG_STAGE + if (D4R_RRSWIN_DEBUG_STAGE == 2 * g + 1 + chain) { + uint32_t regs[48]; + stage_regs(d[chain], regs); + debug_store(prm, regs, 48); + } +#endif + } + } + + // ---- phase 9: the score GEMM, Q·Kᵀ over the 96-row stem output ---- + // The arena's 12800 bytes are split four ways (3200 per wave); the stem's + // A fragments have already been read into registers above, so the wave's + // whole share is free from here on. + const int g = (int)(lane_id() >> 2); + const int t = (int)(lane_id() & 3); + lds_u32* const pub = (lds_u32*)(uintptr_t)scratch + 800 * (int)z; + { + const uint32_t* qk = d[0]; // P7's output: queries and keys alike +#pragma unroll + for (int nb = 0; nb < 12; ++nb) { + uint32_t kw[2]; + row_words(qk, 16 * (nb >> 1) + 8 * (nb & 1) + g, kw); + pub[64 * nb + lane_id()] = kw[0]; + pub[64 * nb + 32 + lane_id()] = kw[1]; + } + } + __builtin_amdgcn_s_barrier(); + uint32_t d9[48] = {}; + { + const uint32_t* qk = d[0]; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + for (int row = 0; row < 2; ++row) { + uint32_t aw[2], a[2][4]; + row_words(qk, 16 * mi + g + 8 * row, aw); + bfly2x4(aw, a); + for (int nb = 0; nb < 12; ++nb) { + float s[2] = {0.0f, 0.0f}; + for (int c = 0; c < 2; ++c) { + // the mma's eight n-index rows are the key rows + // 16*(nb>>1) + 8*(nb&1) + n, and the lane's two D columns + // are n = 2t + c: each half dots a *different* key row + uint32_t kb[2][4]; + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { + kb[i][m] = pub[64 * nb + 32 * i + 4 * (2 * t + c) + (t ^ m)]; + } + } + s[c] = dot32(a, kb); + } + const uint32_t bias = *(const uint32_t*)(wz + 8448 + + 512 * (4 * (nb >> 1) + mi) + + 16 * lane_id() + 8 * (nb & 1) + 4 * row); + d9[(2 * mi + row) * 12 + nb] = pair_of((half_t)(s[0] + h2f(bias)), + (half_t)(s[1] + h2f(bias >> 16))); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 9 + { + uint32_t regs[96]; + for (int mi = 0; mi < 4; ++mi) { + for (int nb = 0; nb < 12; ++nb) { + regs[2 * (mi * 12 + nb)] = d9[(2 * mi + 0) * 12 + nb]; + regs[2 * (mi * 12 + nb) + 1] = d9[(2 * mi + 1) * 12 + nb]; + } + } + debug_store(prm, regs, 96); + } +#endif + + // ---- E9 and phase 10: the softmax and P·V -------------------------- + // E9's V transpose is a movmatrix of P8's accumulators (the even chain); + // the scalar body reaches it by publishing the 96x32 tile as one e4m3 byte + // per element (3072 bytes, the same window the score keys used) and letting + // every lane walk all 96 k's. k-step ks packs key columns {4ks, 4ks+2} of + // the probabilities into the A fragment's first word and {4ks+1, 4ks+3} + // into its second, which is the same packing enc0's phase 6 uses. + { + lds_u8* const vs = (lds_u8*)(uintptr_t)scratch + 3200 * (int)z; + const uint32_t* v = d[1]; // P8's output +#pragma unroll + for (int mi4 = 0; mi4 < 6; ++mi4) { + for (int rh4 = 0; rh4 < 2; ++rh4) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + for (int c = 0; c < 2; ++c) { + const int r = 16 * mi4 + 8 * rh4 + g; + vs[r * 32 + 8 * nt + 2 * t + c] = + (uint8_t)q8(dcell(v, r, 8 * nt + 2 * t + c)); + } + } + } + } + } + __builtin_amdgcn_s_barrier(); + uint32_t d10[48] = {}; + { + const lds_u8* const vs = (const lds_u8*)(uintptr_t)scratch + 3200 * (int)z; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + for (int rh = 0; rh < 2; ++rh) { + uint32_t prob[12]; + row_probs(d9, mi, rh, prob); +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + half_t prev0 = hf16(0x0000), prev1 = hf16(0x0000); +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + uint32_t aw[2], a[2][4]; + aw[0] = e4m3x2(prob[4 * ks]) | (e4m3x2(prob[4 * ks + 2]) << 16); + aw[1] = e4m3x2(prob[4 * ks + 1]) | (e4m3x2(prob[4 * ks + 3]) << 16); + bfly2x4(aw, a); + float acc0 = 0.0f, acc1 = 0.0f; +#pragma unroll + for (int kk = 0; kk < 32; ++kk) { + const float pv = e4m3_to_f32( + (word_at(a, (kk >> 3) & 1, t ^ ((kk >> 1) & 3)) + >> (8 * (2 * (kk >> 4) + (kk & 1)))) & 0xffu); + const int r = (32 * ks + kk) * 32 + 8 * nt + 2 * t; + acc0 += pv * e4m3_to_f32(vs[r]); + acc1 += pv * e4m3_to_f32(vs[r + 1]); + } + // each k-step rounds to f16 before the next adds to it, + // which is why the chain has three separate mma + prev0 = (half_t)(acc0 + (float)prev0); + prev1 = (half_t)(acc1 + (float)prev1); + } + d10[(2 * mi + rh) * 4 + nt] = pair_of(prev0, prev1); + } + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 10 + { + uint32_t regs[48]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d10[(2 * mi + 0) * 4 + nt]; + regs[i++] = d10[(2 * mi + 1) * 4 + nt]; + } + } + debug_store(prm, regs, 48); + } +#endif + // ---- handing the accumulators back ---------------------------------- + // Phase 48's last two mma D pairs; the other forty-six phases are not + // implemented yet, so the four slots carry zero. + __attribute__((address_space(3))) uint32_t* out = + ((__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch) + 12288 / 4 + + 4 * (uint32_t)lane_id(); + out[0] = 0; + out[1] = 0; + out[2] = 0; + out[3] = 0; +} + +// --------------------------------------------------------------------------- +// Weight image layout of the stem, as byte offsets from the wave's slice +// (wave z's slice starts at z*24576): +// P1 256 P2 4352 P3 1280 P4 5376 P5 2304 P6 6400 P7 3328 P8 7424 +// i.e. phase p (1..8) uses 256 + 1024*((p-1)/2) + 4096*((p-1) and 1); each reads +// two 512-byte tiles (n-tiles 0..1 and 2..3) of 8 bytes per n-tile. +// +// Fragment maps (VERIFIED against the debug oracle, see below; g = lane>>2, +// t = lane&3). The hardware order of an m16n8k32 .e4m3 fragment is *not* the +// order the PTX ISA figures suggest. NVIDIA's own epilogue settles it: it +// builds phase 2's A operand as `%r1207 = {cvt(%r877), cvt(%r897)}` where +// %r877/%r897 are the D halves of mma rows 2231/2233, i.e. (row g, n-tile 0, +// cols 2t, 2t+1) and (row g, n-tile 2, cols 2t, 2t+1). So with the four bytes of +// an A register in memory order: +// A reg 0 -> row g, k = 2t + (j&1) + 16*((j>>1)&1) +// A reg 1 -> row g+8, same k +// A reg 2 -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// A reg 3 -> row g+8, same k +// and the B half that must pair with it (a0/a1 with b0, a2/a3 with b1) is +// B byte j (j<4) -> n = 16*tt + 8*(b>>3) + g, k = 2t + (j&1) + 16*((j>>1)&1) +// B byte j (j>=4) -> n = 16*tt + 8*(b>>3) + g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// with b the byte index within the lane's 16 and tt the 512-byte tile. Inverted, +// that is waddr() above. C/D: +// C/D reg 0 -> row g, cols t*2, t*2+1 +// C/D reg 1 -> row g+8, cols t*2, t*2+1 +// +// A plain f32 dot product over K plus C, rounded to f16 once, reproduces the +// translated kernel's phase-1 output exactly, so the phases need no +// operand-layout gymnastics and no WMMA intrinsics: every GEMM here is exact in +// f32 before the f16 rounding. \ No newline at end of file diff --git a/kernels/rr/rrswin_enc3_epilogues.md b/kernels/rr/rrswin_enc3_epilogues.md new file mode 100644 index 0000000..8bf400f --- /dev/null +++ b/kernels/rr/rrswin_enc3_epilogues.md @@ -0,0 +1,845 @@ +# `cuda_dldn_engine_swin_enc3_kernel` — the epilogues of phases 1…48 + +Companion to `kernels/rr/rr_layer_spec.py enc3`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0016-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc3_kernel`. + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at its first line). **`LNNNNN` is + the physical line** of the same instruction in the corpus file, so every claim + can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. The phase table gives the ranges; this file names + what each one *computes*. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_enc3_kernel_param_0+40]` (s8). Every + `ld.weak.global.ca.v4.u32` in an epilogue reads `W + 16*laneid + imm`, and the + global alias `%rd74 = cvta.to.global.u64 %rd2` (s5564) is what the table loads + in the epilogues use. +* `S` denotes the plane arena: `param_0+48`, reached as + `ld.param.u64 %rd556, [%rd1+-32]` with `%rd1 = param_0+80` (`add.s64 %rd1, + %rd7, 80`, s4) then `cvta.to.global.u64 %rd4, %rd556` (s16148–s16149). +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, + `g = laneid>>2`, `t = laneid&3`. +* `rr_layer_spec.py`'s printed `M`/`N`/`K` come from `geom()`, i.e. from the + distinct A-fragment count (`M = 16·nA`), the distinct B-fragment count + (`N = 8·nB`) and the accumulator-chain length (`K = 32·len`). The phase + object's own `w_min..w_max`/`n_tiles`/`k_slots` fields use a *different* + (512-byte-block) convention and disagree with `geom()` on the stem phases; §2 + uses `geom()` and checks the arithmetic explicitly. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, 315732 bytes) | `ld.param.u64 %rd2, [param_0+40]` | s8 | +| `W`(global alias) | `cvta.to.global.u64 %rd74, %rd2` | s5564 | +| `S` (plane arena, `param+48`) | `ld.param.u64 %rd556, [%rd1+-32]` → `cvta.to.global.u64 %rd4, %rd556` | s16148–s16149 | +| output buffer (`param+56`) | `ld.param.u64 %rd5, [%rd682+56]` | s16581 | +| input plane (`param+8`) | `ld.param.u64 %rd9, [param_0+8]` → `cvta.to.global.u64 %rd3, %rd9` | s16–s17 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r407, %r408}, [param_0+0]` | s13 | +| block origin `(x0, y0)` | `%r402 = ctaid.x<<3`, `%r1 = %r402 - %rs166`; `%r406 = ctaid.y<<3`, `%r2 = %r406 - %rs167`; `%rs166/%rs167` from `ld.param.v2.u16 [param_0+80]` | s2, s3, s7, s10, s11, s12, s5 | +| `%rd7` = `param_0` | `mov.b64 %rd7, cuda_dldn_engine_swin_enc3_kernel_param_0` | s1 | +| shared arena base `%r4244` | `mov.u32 %r4244, _ZZ33cuda_dldn_engine_swin_enc3_kernel33DldnEngineSwinEncParamsStructBaseE4smem` | s6002 | +| `%r235` = `%r4244 + (tid.z<<11)` | `shl.b32 %r4243, %r12, 11` then `add.s32 %r235, %r4244, %r4243` | s6001, s6003 | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, %rd2, %rd` | e.g. s6115–s6117 | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd74, %rd` = `W + ((laneid<<2)&12)` | e.g. s10558–s10561 | + +The last line matters exactly as in enc0: a `ld.global.v2.u16` / `ld.global.u32` +with that addressing reads **the same 16-byte record from the four lanes with +equal `laneid&3`**, so those tables are indexed by column, not by row. + +The shadow copy `ld.param.u64 %rd947, [param_0+40]` appears again at s20229 in the +final epilogue — the weight image pointer is re-read, not cached. + +### 1.2 Constants that survive between epilogues + +| register | first definition | literal | meaning | +|---|---|---|---| +| `%f476` | s6585 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 (softmax input scale) | +| `%fd383` | s6589 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | f16 clamp lower bound | +| `%fd385` | s6594 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | f16 clamp upper bound | +| `%f478` | s6600 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | cubic coefficient | +| `%f480` | s6605 `mov.f32 %f480, 0f3FB00000` | 1.375 | cubic constant term | +| `%fd1` | s4856 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | norm epsilon | +| `%f989` | s11656 `mov.f32 %f989, 0f3ED306EB` | 0.4121621549129486 | activation coefficient | +| `%f990` | s11659 `mov.f32 %f990, 0f3DA60DD6` | 0.0810810774564743 | activation coefficient | +| `%f991` | s11662 `mov.f32 %f991, 0f3F000000` | 0.5 | activation offset | +| `%f992` | s11665 `mov.f32 %f992, 0f40000000` | 2.0 | activation clamp | + +`%f989…%f992` are defined inside phase 15's epilogue and re-materialised (as +`mov.f32` + `cvt.rn.f16.f32` pairs) inside the epilogue of every odd phase +17…45, e.g. s12054–s12064 (E17) — unlike enc0 the *f32* constants are not reused, +only their values. + +Live across the whole mma region (defined in the prologue, read by every warp +reduction): + +| register | statement | value | used as | +|---|---|---|---| +| `%r4016` | s4416 | 1 | `shfl.sync.bfly` `b` operand, bit 0 | +| `%r4025` | s4805 | 2 | `shfl.sync.bfly` `b` operand, bit 1 | +| `%r4027` | s4798 | −1 | `shfl.sync.bfly` membermask | + +The `c` (clamp/segment) operand of every butterfly is built as +`%r = (WARP_SZ << 8) - 8192` then `or.b32 %r, %r, 31` (e.g. s8785–s8787), i.e. +31 for a 32-lane warp. + +The long-lived **residual vector**: 48 `mov.b32 {%rsA, %rsB}, %r3713+4k` +statements at s4480 ff. split `%r3713, %r3717, %r3721 …` into f16 halves +(`%rs1460/%rs1463`, `%rs1466/%rs1469`, `%rs1472/%rs1475`, …). Each `%r3713+4k` is +`cvt.rn.f16x2.e4m3x2 %r3713, %rs168` (s4415), i.e. the dequantisation of two +packed e4m3 bytes loaded from the input plane by `ld.global.v2.u16 {%rs168, +%rs169}, [%rd11]` with `%rd11 = %rd3 + …` and `%rd3 = cvta.to.global.param_0+8` +(s173–s175). These halves are added to the column tables in E10 (§3/E10) and +read nowhere else. + +### 1.3 Quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — its inverse, used only in the prologue (s4415 ff.). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (each step rounded through f16). + +### 1.4 The shared arena + +`_ZZ…E4smem` is declared 12800 bytes. The mma A operands of phases 1…8 come from +24 `ld.shared.v4.u32` at `%r4244 + 16*laneid + 512*k`, `k = 0…23` +(s6090–s6113, lines 9771–9794); phases 11…14 come from 4 such loads at +`%r4244 + (tid.z<<9) + 16*laneid + {0, 2048, 4096, 6144}` (s10537, s10693, s10732, +s10770); phase 47 comes from 64 `ld.shared.u32` (s16502–s16574). The arena is +written by the prologue (s6054–s6083), by the P*V epilogue E10 (s10491–s10530) +and by E46 (s16348–s16480). See §6/U3. + +## 2. Phase table summary + +Reproduced from `rr_layer_spec.py enc3` with `M`, `N`, `K` from `geom()` (fragment +counts and chain lengths), and `check = (M/16)·(N/8)·(K/32)`: + +| # | stmt range | lines | M | N | K | nA | nB | chains | klens | mma | check | =? | weight bytes | C bias bytes | epi | +|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +| 1 | s6124–s6147 | L9812–9973 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 256..780 | – | 7 | +| 2 | s6155–s6178 | L9993–10154 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 4352..4876 | – | 7 | +| 3 | s6186–s6209 | L10174–10335 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 1280..1804 | – | 7 | +| 4 | s6217–s6240 | L10355–10516 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 5376..5900 | – | 7 | +| 5 | s6248–s6271 | L10536–10697 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 2304..2828 | – | 7 | +| 6 | s6279–s6302 | L10717–10878 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 6400..6924 | – | 7 | +| 7 | s6310–s6333 | L10898–11059 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 3328..3852 | – | 7 | +| 8 | s6341–s6364 | L11079–11240 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 7424..7948 | – | 171 | +| 9 | s6536–s6583 | L11628–11957 | 64 | 96 | 32 | 4 | 12 | 48 | 1 | 48 | 48 | Y | – | 8448..20236 | 3843 | +| 10 | s10427–s10474 | L22107–22436 | 192 | 96 | 96 | 12 | 12 | 16 | 3 | 48 | 432 | **N** | – | – | 199 | +| 11 | s10674–s10689 | L22922–23027 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 20736..24332 | – | 23 | +| 12 | s10713–s10728 | L23077–23182 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 45312..48908 | – | 23 | +| 13 | s10752–s10767 | L23232–23337 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 69888..73484 | – | 23 | +| 14 | s10791–s10806 | L23387–23492 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 94464..98060 | – | 832 | +| 15 | s11639–s11654 | L25484–25589 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 99072..102668 | 103168..103216 | 289 | +| 16 | s11944–s11959 | L26459–26564 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 103232..106828 | – | 76 | +| 17 | s12036–s12051 | L26731–26836 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 107584..111180 | 111680..111728 | 168 | +| 18 | s12220–s12235 | L27391–27496 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 111744..115340 | – | 76 | +| 19 | s12312–s12327 | L27663–27768 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 115840..119436 | 119936..119984 | 168 | +| 20 | s12496–s12511 | L28323–28428 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 120000..123596 | – | 76 | +| 21 | s12588–s12603 | L28595–28700 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 124096..127692 | 128192..128240 | 168 | +| 22 | s12772–s12787 | L29255–29360 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 128256..131852 | – | 76 | +| 23 | s12864–s12879 | L29527–29632 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 132352..135948 | 136448..136496 | 168 | +| 24 | s13048–s13063 | L30187–30292 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 136512..140108 | – | 76 | +| 25 | s13140–s13155 | L30459–30564 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 140608..144204 | 144704..144752 | 168 | +| 26 | s13324–s13339 | L31119–31224 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 144768..148364 | – | 76 | +| 27 | s13416–s13431 | L31391–31496 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 148864..152460 | 152960..153008 | 168 | +| 28 | s13600–s13615 | L32051–32156 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 153024..156620 | – | 76 | +| 29 | s13692–s13707 | L32323–32428 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 157120..160716 | 161216..161264 | 168 | +| 30 | s13876–s13891 | L32983–33088 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 161280..164876 | – | 76 | +| 31 | s13968–s13983 | L33255–33360 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 165376..168972 | 169472..169520 | 168 | +| 32 | s14152–s14167 | L33915–34020 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 169536..173132 | – | 76 | +| 33 | s14244–s14259 | L34187–34292 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 173632..177228 | 177728..177776 | 168 | +| 34 | s14428–s14443 | L34847–34952 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 177792..181388 | – | 76 | +| 35 | s14520–s14535 | L35119–35224 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 181888..185484 | 185984..186032 | 168 | +| 36 | s14704–s14719 | L35779–35884 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 186048..189644 | – | 76 | +| 37 | s14796–s14811 | L36051–36156 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 190144..193740 | 194240..194288 | 168 | +| 38 | s14980–s14995 | L36711–36816 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 194304..197900 | – | 76 | +| 39 | s15072–s15087 | L36983–37088 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 198400..201996 | 202496..202544 | 168 | +| 40 | s15256–s15271 | L37643–37748 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 202560..206156 | – | 76 | +| 41 | s15348–s15363 | L37915–38020 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 206656..210252 | 210752..210800 | 168 | +| 42 | s15532–s15547 | L38575–38680 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 210816..214412 | – | 76 | +| 43 | s15624–s15639 | L38847–38952 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 214912..218508 | 219008..219056 | 168 | +| 44 | s15808–s15823 | L39507–39612 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 219072..222668 | – | 76 | +| 45 | s15900–s15915 | L39779–39884 | 64 | 128 | 128 | 4 | 16 | 4 | 4 | 16 | 256 | **N** | 223168..226764 | 227264..227312 | 168 | +| 46 | s16084–s16099 | L40439–40544 | 16 | 128 | 32 | 1 | 16 | 16 | 1 | 16 | 16 | Y | 227328..230924 | – | 564 | +| 47 | s16664–s16727 | L41319–41760 | 256 | 512 | 512 | 16 | 64 | 4 | 16 | 64 | 16384 | **N** | 231424..247308 | 313344..313392 | 125 | +| 48 | s16853–s16860 | L41931–41980 | 64 | 64 | 128 | 4 | 8 | 2 | 4 | 8 | 128 | **N** | 313664..315212 | 315712..315728 | 323 | + +**Arithmetic check.** Rows 1–9, 11–16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, +38, 40, 42, 44 and 46 satisfy +`M/16 · N/8 · K/32 == mma`, i.e. every A×B tile of the M×N tile grid is +evaluated exactly once, so `M`/`N`/`K` are the true GEMM shape. + +Rows 10, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47 and 48 +do **not**: the phase is *banded* (a diagonal block of the M×N grid) and the +printed `M`, `N` are the *extents spanned by the fragment operands*, not the shape +of the result. The chain structure makes the real shape explicit: + +* **P10** (`48 mma`, 16 chains of 3): chain `c` is + `(A_{3·(c>>2)+k}, B_{2·(c&3)+k})` for `k = 0,1,2` — 4 row tiles × 4 column-pair + groups, each accumulating 3 k-steps. Real shape **64×32×96**, all + 4×4 = 16 output tiles evaluated. (Same shape as enc0's P6.) +* **P15/17/…/45** (`16 mma`, 4 chains of 4): chain 0 is + `(A0,B0) (A1,B2) (A2,B4) (A3,B6)`, chain 1 is `(A0,B1) (A1,B3) (A2,B5) (A3,B7)`, + chain 2 repeats with `B8…B15`, chain 3 with `B9…B15` — 4 row tiles × 2 column + tiles per 8-B group, 4 k-steps. Real shape **64×64×128** with only the + 4×2 = 8 diagonal output tiles evaluated (of a 4×8 grid). +* **P47** (`64 mma`, 4 chains of 16): chain 0 is + `(A_j, B_{2j})`, chain 1 `(A_j, B_{2j+1})`, chains 2/3 `B_{32+2j}`, `B_{32+2j+1}`, + `j = 0…15`. 16 k-steps. Real shape **256×256×512** over 4 output tiles. +* **P48** (`8 mma`, 2 chains of 4): `(A_j, B_{2j})` / `(A_j, B_{2j+1})`, + `j = 0…3`. Real shape **64×32×128** over 2 tiles. +* **P15…P45 odd** likewise. + +**Phases that read no weight-image B operand:** **P9** (`Bo = [None, None]` on all +48 mma — its `B` is a register operand packed from P7's D, §3/E8) and **P10** +(its `B` is packed from the `movmatrix` of P8's D, §3/E9(f)). Every other phase's +`B` is loaded from `W`. + +**Weight-image extent.** The largest byte offset used anywhere is 315728 (P48's +second C seed, `ld.global.u32 [%rd653+315728]`, s16852; the first is `+315712`, +s16851). With the 4-byte read that makes the image **315732 bytes**; 1654 +distinct weight-image byte offsets are touched (`weight_image_size`). The single largest interior gap is +`247308…313344` — 66036 bytes between the end of P47's B block and P47's bias that +no phase in this entry reads (the analogous hole in enc4 is 82420 bytes, §5/U9 of +`rrswin_enc4_epilogues.md`). + +## 3. The epilogues + +Phases 1…8 (the stem), 11…45 (the norm + MLP block) and 46…48 (the merge) are +highly repetitive; each distinct body is written out once and the repeats are +tabulated. + +### E1…E7 — s6148–s6154, s6179–s6185, s6210–s6216, s6241–s6247, s6272–s6278, s6303–s6309, s6334–s6340: next-B loads + +Seven identical 7-statement epilogues (`add.s64`×3, 2 `ld.weak.global.ca.v4.u32`, +`mov.u32`, `mul.wide.u32`). Each issues the two `v4.u32` fragments of the *next* +phase's B operand at `W + 16*laneid + {base, base+512}`: + +| epilogue | range | loads (statement / line) | offsets | next phase's W block | +|---|---|---|---|---| +| E1 | s6148–s6154 | s6152 / L9986, s6154 / L9990 | 4352, 4864 | P2 `4352..4876` | +| E2 | s6179–s6185 | s6183 / L10167, s6185 / L10171 | 1280, 1792 | P3 `1280..1804` | +| E3 | s6210–s6216 | s6214 / L10348, s6216 / L10352 | 5376, 5888 | P4 `5376..5900` | +| E4 | s6241–s6247 | s6245 / L10529, s6247 / L10533 | 2304, 2816 | P5 `2304..2828` | +| E5 | s6272–s6278 | s6276 / L10710, s6278 / L10714 | 6400, 6912 | P6 `6400..6924` | +| E6 | s6303–s6309 | s6307 / L10891, s6309 / L10895 | 3328, 3840 | P7 `3328..3852` | +| E7 | s6334–s6340 | s6338 / L11072, s6340 / L11076 | 7424, 7936 | P8 `7424..7948` | + +Nothing else. **Outputs:** the 8 registers of the next phase's B. + +### E8 — s6365–s6535: the score-phase bias tiles and the phase-9 operands + +171 statements: 24 `ld.weak.global.ca.v4.u32`, 80 +`cvt.rn.satfinite.e4m3x2.f16x2`, 40 `mov.b32`, 25 `add.s64`, plus one +`mov.u32`/`mul.wide.u32` per-lane address pair. + +``` +s6368 L11249: add.s64 %rd94, %rd425, 8448 +s6369 L11253: ld.weak.global.ca.v4.u32 { %r6280,%r6281,%r6282,%r6283},[%rd94] +s6415 L11345: ld.weak.global.ca.v4.u32 { %r6372,…%r6375},[%rd117] // 8448+23*512 = +20224 +s6416 L11348: cvt.rn.satfinite.e4m3x2.f16x2 %rs1942, %r5810 +s6489 L11522: cvt.rn.satfinite.e4m3x2.f16x2 %rs1989, %r5790 +s6535 L11626: mov.b32 %r6933, {%rs2034, %rs2035} +``` + +1. **Score-bias C seeds** (s6368–s6415): 24 `v4.u32` loads at + `W + 16*laneid + 8448 + 512*i`, `i = 0…23` → `%r6280 … %r6375` + (96 registers = the 96 `C` operands of phase 9). The index is the same + `4*(n>>1) + m` scheme enc0 documents: `4*(n>>1)+m` runs 0…23 for the 4 m-tiles + and 6 `(n>>1)` groups, and phase 9's own mma confirm the assignment + (`s6536 C=%r6280,%r6281` first, `s6538 C=%r6296,%r6297` = the `+2048` tile). + Byte block `[8448, 20236]` = 11792 bytes of f16, structurally identical to + enc0's `[8384, 20672)`. +2. **B packs** (s6418–s6487, sources from s6416): the first 24 `mov.b32` + destinations + (`%r6822 %r6823 %r6832 %r6833 … %r6932 %r6933`) = phase 9's twelve B fragments + (24 b32). Every source pair is + `cvt.rn.satfinite.e4m3x2.f16x2` of two registers written by **phase 7's mma** + (`%r5790 … %r6021`), verified by walking each `mov.b32`'s operands through its + two `cvt` statements (e.g. `s6417: cvt %rs1941, %r5790`, `s6416: cvt %rs1942, + %r5810`, `s6418: mov.b32 %r6822, {%rs1941, %rs1942}`). +3. **A packs** (s6490–s6535): the remaining 16 `mov.b32` destinations + (`%r6568 %r6569 %r6570 %r6571`, `%r6688…%r6691`, `%r6808…%r6811`, + `%r6928…%r6931`) = phase 9's four A fragments (16 b32), also from phase 7's D + (`s6489: cvt %rs1989, %r5790`). + +**Phase 9's A fragment 0 and B fragment 0 are bit-identical**: both are +`{pack(%r5790,%r5810), …}` — `%r6568` (s6489–s6491) and `%r6822` (s6416–s6418) +read the same two source registers. Whatever the score GEMM's two operands mean, +fragment 0 of each is the same value, exactly as in enc0 (E9). + +**Inputs:** phase 7's 48 D registers, phase 8's `%r10141`-adjacent state. +**Outputs:** phase 9's 16 A + 24 B registers and its 96 C seeds. + +### E9 — s6584–s10426: the 64×96 score softmax + +3843 statements, **zero memory access**. This is the enc0 E5 block verbatim with +shifted registers; the op histogram is the same (1048 `mov.b32`, 672 +`cvt.rn.f16.f32`, 384 `cvt.rn.f16.f64`, 192 each `fma.rn.f16x2` / +`cvt.f32.f16` / `rcp.approx.ftz.f32` / `mul.f16`, 96 each `max.f16x2`/`min.f16x2`/ +`neg.f16x2`/`mul.f16x2`/`and.b32`, 48 `movmatrix`, 16 `shfl.sync.bfly`, 144 packs). + +Sub-ranges (first/last statement with the physical line): + +| range | statements | what | +|---|---|---| +| s6584–s8701 | 2118 | 96 per-element exponent groups (scale, clamp, cubic, mantissa shift/and) | +| s8702–s8781 | 80 | in-lane partial sum trees (`add.f16x2`) | +| s8782–s8916 | 135 | 16 `shfl.sync.bfly.b32` (s8788/L18834 … s8909/L19138) → 8 row sums | +| s8918–s9679 | 769 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s9685–s10161 | 477 | 192 `mul.f16` → 96 probabilities | +| s10163–s10210 | 48 | `movmatrix.sync.trans.aligned.m8n8.b16` of **phase 8's** 48 D registers | +| s10211–s10425 | 216 | 144 `cvt.rn.satfinite.e4m3x2.f16x2` packs | + +**(a) per-element exponent, s6584–s8701.** Per f16 half `x` of each of phase 9's +96 D f16x2 registers: + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) + s6588 mul.f16x2, s6593 max.f16x2, s6598 min.f16x2 +u = f16(1.375 + m*(0.92724609375 - m^2)) + s6604 fma.rn.f16x2 (m*(-m) + 0.92724609375), s6609 fma.rn.f16x2 (m*u + 1.375) +E = (u_bits << 5) & 0x7FE07FE0 // s6610 shl.b32, s6611 and.b32 +``` + +i.e. the same "cubic in the exponent field" approximation enc0's E5(a) derives and +which the acceptance text asks about. The constants are re-materialised per group +(`s6585 mov.f32 %f476 …`, `s6589/s6594 mov.f64 %fd383/%fd385 …`) — unlike enc0, +this layer's E9 does not hoist them. + +**(b) row sums, s8702–s8781 + s8782–s8916.** 96 `expval` registers are added in +eight groups of six (`add.f16x2`), then across lane bits 0 and 1 with +`shfl.sync.bfly` using `%r4016 = 1` and `%r4025 = 2`, then the f16x2 halves are +folded with `add.f16` and broadcast (`s8796 mov.b32 {%rs2790,%rs2791}, %r9116` / +`s8797 add.f16` / `s8798 mov.b32 %r9313, {%rs2789,%rs2789}`). + +**There is no row maximum anywhere in this epilogue.** `max.f16x2`/`min.f16x2` +(96 each, s6593…s8691) are the clamp of (a); the only shuffles are the 16 +`shfl.sync.bfly` above. (Contrast E48(b), which *does* take a row max.) + +**(c) reciprocal / probability, s8918–s10161.** 192 `rcp.approx.ftz.f32` wrapped +as `cvt.f32.f16 → rcp → cvt.rn.f16.f32` on the 8 row sums (each inverted once per +row-tile), then 192 `mul.f16` giving `p = expval * (1/rowsum)`. + +**(d) V transpose, s10163–s10210.** Exactly 48 +`movmatrix.sync.trans.aligned.m8n8.b16` on phase **8**'s 48 D registers +(`%r6039 %r6040 %r6049 %r6050 … %r6270`; `s10163 L21459: movmatrix… %r9462, +%r6039`, `s10210 L21600: … %r9556, %r6270`) → 48 b32 of transposed V. + +**(e) packs, s10211–s10425.** 144 packs: s10211–s10314 from the movmatrix +results → phase 10's 12 B fragments (`%r10068 …%r10179`, e.g. `s10213: mov.b32 +%r10068, {%rs3389, %rs3390}`); the rest from the probabilities → phase 10's 12 A +fragments (`%r9774 …%r10177`, e.g. `s10427 A={%r9774,%r9775,%r9776,%r9777}`). + +**Inputs:** phase 9's 96 D, phase 8's 48 D, `%r4016/%r4025/%r4027`. +**Outputs:** phase 10's 48 A / 24 B registers (plus the `%f476`, `%fd383`, +`%fd385`, `%f478`, `%f480` constants). **Memory:** none. + +### E10 — s10475–s10673: P·V epilogue — pack, shared staging, residual table, next B/C + +199 statements. Histogram: `add.f16`×64, `mov.b32`×48, +`cvt.rn.satfinite.e4m3x2.f16x2`×32, `ld.global.v2.u16`×16, `add.s64`×10, +`ld.weak.global.ca.v4.u32`×8, `mov.u32`×4, `shl.b32`×4, `st.shared.v4.u32`×4, +`add.s32`×3, `bar.sync`×2, `ld.shared.v4.u32`×1, `mul.wide.u32`×1, +`cvt.u64.u32`×1, `and.b64`×1. + +**(a) require, s10479–s10530.** 32 packs of phase 10's D → 16 b32 +(`%r22010 … %r22025`, `s10487 L22472: mov.b32 %r22010, {%rs3539, %rs3540}`), +stored one `v4.u32` per 512 bytes at +`%r22009 = %r235 + (laneid<<4)` (`s10478 add.s32 %r22009, %r235, %r22008`, +`%r22008 = laneid<<4` s10477): +`s10491 st.shared.v4.u32 [%r22009], …`, `s10504 [+512]`, `s10517 [+1024]`, +`s10530 [+1536]`. + +**(b) stage read-back, s10531–s10541.** `s10531 bar.sync 0`, then one +`ld.shared.v4.u32 [%r22029]` at +`%r22029 = %r4244 + (tid.z<<9) + (laneid<<4)` (`s10532–s10536`) → `%r22030 … +%r22033` (one 16-byte A fragment). These are **phase 11's A operand** (P11 +`A = %r22030,%r22031,%r22032,%r22033`). + +**(c) next B, s10541–s10556.** 8 `v4.u32` at `W + 16*laneid + 20736 + 512*j`, +`j = 0..7` → phase 11's 16 B fragments (block `[20736, 24332)`). + +**(d) residual column table, s10557–s10577.** 16 `ld.global.v2.u16` at +`W + ((laneid<<2)&12) + {98560 + 16*i}`, `i = 0…15` → 32 f16 +(`%rs5396 … %rs5427`) covering the 128 columns of phase 11's output. + +**(e) residual add, s10578–s10673.** 64 `add.f16` — two per f16x2 — each +`table[column] + `, e.g. + +``` +s10579 L22638: add.f16 %rs3565,%rs5426,%rs1460 // %rs5426 = W+98560, %rs1460 = residual +s10578 L22634: add.f16 %rs3568,%rs5427,%rs1463 +s10580 L22641: mov.b32 %r10258, {%rs3565, %rs3568} +``` + +The 32 results `%r10258 %r10259 %r10268 … %r10409` are **phase 11's C operands** +(`s10674 C={%r10258,%r10259}`). So P11 computes +`D11 = A11·B11 + (table + residual)`. + +**Inputs:** phase 10's D, phase 8's D staging, `%r4244/%r235`, `W`. +**Outputs:** phase 11's A (4 regs), B (32 regs) and C (32 regs). + +### E11…E13 — s10690–s10712, s10729–s10751, s10768–s10790: next-A from shared, next-B from W + +Three identical 23-statement epilogues (`add.s64`×9, 8 `v4.u32`, `mov.u32`×2, +`shl.b32`, `add.s32`, 1 `ld.shared.v4.u32`, `mul.wide.u32`): + +``` +s10692 L23037: add.s32 %r22036, %r22027, %r22035 // %r22027 = %r4244 + (tid.z<<9) +s10693 L23038: ld.shared.v4.u32 {…}, [%r22036+2048] +s10697 L23044: add.s64 %rd126, %rd433, 45312 +s10698 L23046: ld.weak.global.ca.v4.u32 { %r10412,…},[%rd126] +``` + +| epilogue | range | shared read (offset) | becomes | B offsets | next phase's W block | +|---|---|---|---|---|---| +| E11 | s10690–s10712 | s10693, `+2048` | P12 A | 45312 … 48896 step 512 (8 loads) | P12 `45312..48908` | +| E12 | s10729–s10751 | s10732, `+4096` | P13 A | 69888 … 73472 | P13 `69888..73484` | +| E13 | s10768–s10790 | s10771, `+6144` | P14 A | 94464 … 98048 | P14 `94464..98060` | + +So phases 11…14 (which all have `nA = 1`) each take their single 16×32 A fragment +from one 512-byte slot of the shared arena and their B from `W`. + +### E14 — s10807–s11638: the RMS norm before the MLP + +832 statements: 242 `mov.b32`, 192 `mul.f16`, 66 `add.f16`, 64 `cvt.f32.f16`, +64 `rsqrt.approx.ftz.f32`, 64 `cvt.rn.f16.f32`, 34 `add.f16x2`, 4 +`shfl.sync.bfly`, 32 packs, 16 `ld.global.v2.u16`, 8 weight `v4.u32`, 4 +`ld.global.u32`. + +| range | what | +|---|---| +| s10810–s10935 | 64 `mul.f16` — squares of phase 14's 32 D f16x2 (`s10809 L23500: mov.b32 {%rs4566,%rs4569}, %r10832`, `s10810 mul.f16 %rs3760,%rs4569,%rs4569`) | +| s10937–s10999 | 34 `add.f16x2` — in-lane reduction, with the 4 `shfl.sync.bfly` over lane bits 0,1 at s10971/L23947, s10977, s10983, s10989 | +| s10996–s11001 | `add.f16x2` + `add.f16` — the two row sums per lane | +| s11002–s11097 | `+ 2⁻¹³` (`s11003 add.f16 %rs3959,%rs3949,%rs3955`, `%rs3955 = cvt.rn.f16.f64 %fd1` s11002), broadcast into 32 f16x2 | +| s11102–s11351 | 64 `rsqrt.approx.ftz.f32` (2 halves each) → 32 reciprocals | +| s11355–s11370 | 16 `ld.global.v2.u16` gain at `W + ((laneid<<2)&12) + {98816 + 16*i}` | +| s11372–s11466 | 64 `mul.f16` — `inv · gain` (e.g. `s11372 L24749: mul.f16 %rs4148,%rs4149,%rs5458` with `%rs5458 = W+98816`) | +| s11467–s11561 | 64 `mul.f16` — `x · (inv·gain)` (`s11468 mul.f16 %rs4340,%rs4566,%rs4148`) | +| s11567–s11581 | 8 weight `v4.u32` = phase 15's B (`99072 + 512*j`) | +| s11587–s11590 | 4 `ld.global.u32` at `W + ((laneid<<2)&12) + {103168,103184,103200,103216}` = phase 15's C bias | +| s11591–s11637 | 32 packs of the normalised values → phase 15's A | + +**What it computes.** One RMS reduction per **row** over all 128 columns, with +no mean subtraction and no `1/N`: the lane's 16 one-per-n-tile partials for that +row are tree-summed in-lane (s10937–s10965), the 4 lanes holding the four +`t = laneid&3` column pairs are folded with two butterfly steps, and the f16x2 +halves are added (`s10998 add.f16 %rs3949,%rs3950,%rs3951`). Then + +``` +inv = f16(rsqrt.approx(f32(f16(sumsq + 2^-13)))) +out[row,c] = x[row,c] · inv · gain[c] +``` + +32 `rsqrt` results are produced because the compiler re-emits the reciprocal once +per (row, n-tile) pair, not because there are 32 distinct sums: the 32 `mov.b32` +that feed them copy only **two** distinct halves (`%rs3949` row `g`, `%rs3952` row +`g+8`, e.g. `s11005 mov.b32 %r11121, {%rs3956, %rs3959}` where `%rs3956 = %rs3959 += %rs3949 + 2^-13`). + +`gain[c]` is per column and constant across rows (the four lanes with equal +`laneid&3` read the same 16-byte record). **The norm's bias is not applied +here** — it is phase 15's C operand, loaded at the end of this epilogue +(`+103168 … +103216`). + +**Outputs:** phase 15's B (8 regs) and C (4 regs), 16 packed A registers, and the +32 normalised f16x2 registers that E15/E17/E19 re-read as `%rs4566 …`. + +### E15 — s11655–s11943: clamped cubic activation + column table + pack + +289 statements: `mov.b32`×68, `add.f16`×64, `cvt.rn.f16.f32`×32, `mul.f16x2`×24, +16 `ld.global.v2.u16`, 8 each `neg/max/min/abs/sub/add.f16x2`, 8 weight `v4.u32`, +8 packs, `mov.f32`×4. + +**(a) the constants and the activation, s11656–s11795.** Eight groups, each +materialising `%f989…%f992` (`s11656 L25598: mov.f32 %f989, 0f3ED306EB`, `s11659 +mov.f32 %f990, 0f3DA60DD6`, `s11662 mov.f32 %f991, 0f3F000000`, `s11665 mov.f32 +%f992, 0f40000000`) and then doing, on **phase 15's D** +(`%r11311 %r11321 …`): + +``` +y = clamp(x, -2, +2) // s11668 neg, s11669 max, s11670 min +g = 0.5 + y*(0.412109375 - 0.0810546875*|y|) // s11671 abs, s11672 mul, s11673 sub, + // s11674 mul, s11675 add +out = x * g // s11676 mul.f16x2 +``` + +`g` is the same cubic ramp as enc0's E13 (`g(+2) = 1`, `g(-2) = 0`), **not** a +sigmoid/SiLU. 8 groups cover the 8 register-pairs of the 4 chains of P15. + +**(b) column bias, s11815–s11931.** 16 `ld.global.v2.u16` at +`W + ((laneid<<2)&12) + {107328 + 16*i}` then 64 `add.f16`, e.g. +`s11837 L26147: add.f16 %rs4564,%rs5490,%rs4566` — the second addend is a half of +phase **14**'s D (`%rs4566/%rs4569` ← `%r10832`, s10809), i.e. a residual. The +48 results `%r11694 … %r11845` are **phase 16's C operand**. + +**(c) pack, s11932–s11943.** 8 packs of the **activation outputs** +(`s11932 cvt %rs4757, %r11554`, `s11933 cvt %rs4756, %r11438`, `s11934 mov.b32 +%r11838, {%rs4756,%rs4757}`, …) → phase 16's A fragment (`s11944 +A={%r11838,%r11839,%r11840,%r11841}`). + +**(d) next B, s11800–s11814.** 8 `v4.u32` at `103232 + 512*j` → phase 16's B. + +**No stores, no `ld.global` other than the two tables.** Inputs: phase 15's D, +phase 14's D, `W`. Outputs: phase 16's A (4 regs), B (32), C (32). + +### E16 / E18 / … / E44 — s11960–s12035 and its 14 repeats: next B/C loads + pack + +76 statements, identical shape, for every even phase 16…44: + +``` +s11964 L26577: ld.weak.global.ca.v4.u32 { %r11847,…},[%rd166] // B 103232 + 512*j, 8 loads +s11984 L26614: ld.global.u32 %r11921, [%rd455+111680] // C bias, 4 words at +111680+16*i +s11988 L26619: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r… // 32 packs +s11990 L26624: mov.b32 %r…, {%rs…, %rs…} // 16 b32 = 4 A fragments +``` + +The 32 pack sources (`%r21120 %r21121 %r21122 …`, `s11988 L26619: cvt +%rs4765, %r21121`) are the **normalised values** E14 produced with the second of +its multi-sets (`s11469 mov.b32 %r21120, {%rs4340, %rs4343}`), i.e. phase 17's A +operand is the *same* normed tile that phase 15's A was built from — phases 15 +and 17 are two parallel GEMMs off one normed tile, each with its own weight block +and bias. The 4 C words are `W + ((laneid<<2)&12) + {bias_base + 16*i}`, and +each is used in **both halves** of the *odd* phase's mma C operand: +`s12036 C={%r11921,%r11921}` with `[%r11921=W+111680]`, `s12037 +C={%r11931,%r11931}` with `W+111696`. + +| epilogue | range | next-B block | next-C bytes | +|---|---|---|---| +| E16 | s11960–s12035 | 103232..106828 | 111680..111728 | +| E18 | s12236–s12311 | 111744..115340 | 119936..119984 | +| E20 | s12512–s12587 | 120000..123596 | 128192..128240 | +| E22 | s12788–s12863 | 128256..131852 | 136448..136496 | +| E24 | s13064–s13139 | 136512..140108 | 144704..144752 | +| E26 | s13340–s13415 | 144768..148364 | 152960..153008 | +| E28 | s13616–s13691 | 153024..156620 | 161216..161264 | +| E30 | s13892–s13967 | 161280..164876 | 169472..169520 | +| E32 | s14168–s14243 | 169536..173132 | 177728..177776 | +| E34 | s14444–s14519 | 177792..181388 | 185984..186032 | +| E36 | s14720–s14795 | 186048..189644 | 194240..194288 | +| E38 | s14996–s15071 | 194304..197900 | 202496..202544 | +| E40 | s15272–s15347 | 202560..206156 | 210752..210800 | +| E42 | s15548–s15623 | 210816..214412 | 219008..219056 | +| E44 | s15824–s15899 | 219072..222668 | 227264..227312 | + +### E17 / E19 / … / E45 — s12052–s12219 and its 15 repeats: clamped cubic activation + pack + +168 statements; identical op mix to E15 minus the table loads and the `mov.f32` +block (36 `mov.b32`, 32 `cvt.rn.f16.f32`, 24 `mul.f16x2`, 8 each +`neg/max/min/abs/sub/add.f16x2`, 8 weight `v4.u32`, 8 packs): + +``` +s12061 L26870: neg.f16x2 %r…,%r… +s12062 L26874: max.f16x2 %r…,%r11912,%r… +s12065 L26886: mul.f16x2 %r…,%r…,%r… +s12193 L27332: ld.weak.global.ca.v4.u32 { …},[%rd174] // next B, 8 loads +s12208 L27363: cvt.rn.satfinite.e4m3x2.f16x2 … // 8 packs of activation outputs +``` + +Same function as E15(a) on the odd phase's D (`%r11912 %r11922 …`), 8 packs of the +activation *outputs* → the next even phase's A, and 2 weight groups → the next even +phase's B. **No column bias, no `ld.global`.** The 15 repeats are at +s12052, s12328, s12604, s12880, s13156, s13432, s13708, s13984, s14260, s14536, +s14812, s15088, s15364, s15640, s15916 (one per odd phase 17…45). + +#### Shape of the attention + MLP region, E10–E46 + +``` +P9 A = pack(P7.D) B = pack(P7.D) C = bias@8448+512i → scores 64×96 + E9: cubic-exponent softmax (no row max), 48 movmatrix(P8.D) + packs +P10 A = pack(scores) B = pack(transpose(P8.D)) C = 0 → 64×32 + E10: pack → shared slot, read back as P11 A; table@98560 + residual → P11 C +P11 A = shared, B = W@20736, C = table+residual → D11 + E11: read shared slot +2048 → P12 A; load P12 B +P12 A = shared, B = W@45312, C = D11 → D12 E12: same for P13 +P13 A = shared, B = W@69888, C = D12 → D13 E13: same for P14 +P14 A = shared, B = W@94464, C = D13 → D14 (16×128) + E14: row-RMS norm over 128 columns (+2^-13, rsqrt, gain@98816), pack → P15 A +P15 A = normed tile, B = W@99072, C = bias@103168 → D15 (banded 64×64×128) + E15: cubic activation(D15); table@107328 + D14 → P16 C; pack → P16 A +P16 A = pack(activation), B = W@103232, C = D14+table → D16 + E16: pack of the *normed* tile → P17 A; load P17 B and C +P17 A = normed tile, B = W@107584, C = bias@111680 → D17 + …the P15/P16 pair then repeats 15 more times (P17/P18 … P45/P46), + each odd phase with its own weight block + bias and each even phase + re-using the same normed tile as A and the previous even phase's D as C. +P46 A = pack(activation P45), B = W@227328, C = D44 → D46 (16×128) + E46: arena scatter, shared staging, next B/C +P47 A = 16 shared slots, B = W@231424, C = bias@313344 → 4×16 k-steps + E47: pack + surface scatter to param+56, next B/C +P48 A = pack(E47), B = W@313664, C = bias@315712 → D48 + E48: the final epilogue +``` + +### E46 — s16100–s16663: pack → plane-arena scatter → shared staging → next B/C + +564 statements. Histogram: `add.s32`×66, `ld.shared.u32`×64, `add.s64`×53, +`setp.lt.s32`×36, `shl.b32`×35, `bra`×33, `cvt.rn.satfinite.e4m3x2.f16x2`×32, +`selp.b32`×32, `ld.weak.global.ca.v4.u32`×32, `mov.b32`×16, `mul.wide.s32`×16, +`st.global.u32`×16, `st.shared.u32`×16, `and.b32`×11, `mov.u32`×10, `shr.u32`×10, +`or.b32`×9, `setp.ge.u32`×4, `ld.global.u32`×4, `ld.param.u64`×2, `bar.sync`×2. + +**(a) packs, s16100–s16147.** 32 `cvt.rn.satfinite.e4m3x2.f16x2` + 16 `mov.b32` +→ `%r238 … %r253` = phase 46's 16×128 output as 16 b32 = 32 e4m3 per lane. + +**(b) plane-arena scatter, s16148–s16326.** `%rd4 = cvta(ld.param.u64 [%rd1+-32])` +(s16148–s16149, `%rd1 = param_0+80` ⇒ **`param_0+48`**), lane decomposition +`s16151 shr %r254, laneid, 2` (`g`), `s16152 and %r255, laneid, 3` (`t`), and 8 +index bases formed from `(%r1 + ((g+8j)&7))`, `(%r6' + ((g+8j)>>3))` and +`(%r255 | 4)`, each guarded by `setp.lt.s32 %p, idx, 0` + `bra`: + +| store | value | index | +|---|---|---| +| s16174 / L40691 | `%r238` | `t + 4*(g&7) + 32*(y)` | +| s16183 / L40702 | `%r239` | same, `t` or 4 | +| s16216 / L40737 | `%r240` | second base (`y2 = tid.z*2 + ((g+8)>>3)`) | +| s16224 | `%r241` | `t` or 4 | +| s16233 / s16241 | `%r242`, `%r243` | `+512` of the two bases | +| s16250 / s16258 | `%r244`, `%r245` | | +| s16267 / s16275 | `%r246`, `%r247` | `+1024` | +| s16284 / s16292 | `%r248`, `%r249` | | +| s16301 / s16309 | `%r250`, `%r251` | `+1536` | +| s16318 / s16326 | `%r252`, `%r253` | | + +The exact index algebra is in §6/U4 — the *base* splits as +`t + 4*(g&7) + 32*y` with `y = (tid.z<<1) + (laneid>>5)` for the first group and +`y = (tid.z<<1) + ((g+8)>>3)` for the second, and the second group's `+512` +strides. What is certain: 16 guarded 4-byte stores, i.e. `8*32 = 256` bytes per +row-stride unit of the arena. + +**(c) shared staging, s16330–s16480.** 16 `st.shared.u32` at +`%r22114 = %r4244 + (idx<<2)` with `idx = t | ((laneid&28) | (y<<5))` and +`y = (tid.z<<1) + (laneid>>5)`, then `+256` and `+512*j`, `j = 0…7` +(`s16348 L40899: st.shared.u32 [%r22114], %r238`, `s16356 [+256] …`). A +`bar.sync 0` at s16485 separates the two halves. + +**(d) staging read-back, s16486–s16574.** 64 `ld.shared.u32` at +`%r4244 + (idx2<<2)` with +`idx2 = ((laneid&12)<<1) | ((laneid&~15)<<2) | (laneid&3) (= 16*g + t)` for the +first 32 and `idx2 + 128` for the second 32, at byte offsets `{0, 1024, 2048, +3072, 4096, 5120, 6144, 7168}` (`s16502 L41087: ld.shared.u32 %r304, [%r22196]`, +`s16503 [+1024]`, `s16503–s16522`, then `s16527 [+16] … s16542`). These 64 values +`%r304 … %r367` are **phase 47's 16 A fragments**. + +**(e) next B/C, s16581–s16663.** Inside a loop `$L__BB1_324` (`s16582`), +`s16583 shl.b32 %r22998, %r23413, 9` then 32 `v4.u32` at +`W + 16*laneid + 231424 + 512*(%r23413 + j)`, `j = 0…31` (`s16590 – s16652`) = +phase 47's 64 B fragments, and 4 `ld.global.u32` at +`W + ((laneid<<2)&12) + {313344, 313360, 313376, 313392}` (s16660–s16663) = +phase 47's C bias. + +**Outputs:** `%r238…%r253` (read again by (c)), phase 47's A/B/C. + +### E47 — s16728–s16852: pack → surface scatter → next B/C + +125 statements: 8 packs + 2 `mov.b32` (s16728–s16737), 4 guarded stores to +**`param_0+56`** (s16772 `st.global.v2.u16`, s16783 `st.global.u32`, +s16817 `st.global.u32`, s16826 `st.global.v2.u16`), then 4 weight `v4.u32` +(s16839–s16845) and 2 `ld.global.u32` (s16851–s16852). + +``` +s16738 L41793: mov.u32 %r22997, %laneid +s16744 L41800: shr.u32 %r23004, %r22183, 1 // ey>>1 +s16745 L41801: shr.u32 %r23005, %r22182, 1 // ex>>1 +s16746 L41802: shl.b32 %r23006, %r23005, 3 // 8*(ex>>1) +s16747 L41803: mul.lo.s32 %r23007, %r23004, %r23006 // row stride +s16769 L41826: cvta.to.global.u64 %rd632, %rd5 // %rd5 = param_0+56 (s16581) +s16772 L41829: st.global.v2.u16 [%rd634], {%rs5492, %rs5493} +``` + +The destination is `param+56`, **not** the plane arena; extents come from +`ld.param.v2.u32 [param_0+0]` re-read as `%r22182/%r22183` in E46 (s16487) and are +**halved**. Two index bases are formed, each guarded by +`(y<0)|(y≥(ey>>1))|(laneid>63)|(x<0)|(x≥(ex>>1))|(%r23413>159)`: base 1 +`y = (%r2>>1) + (laneid>>4)`, `x = (%r1>>1) + ((laneid>>2)&3)`; base 2 uses +`(g+8)`. The loop at s16828–s16830 steps `%r23413` by 128 while `< 160`, so the +8-pack/4-store body runs once or twice depending on `tid.z` (§6/U4). + +Then phase 48's B (4 `v4.u32` at `313664 + 512*j`) and C (2 `ld.global.u32` at +`315712`, `315728`). + +### E48 — s16861–s17183: the final epilogue + +323 statements: 4 `st.shared.u32` (s16872–s16891), 2 `bar.sync`, 5 `ld.shared.u32` +(s16930–s16938), 12 `mul.ftz.f32`/`ex2.approx`/`add.ftz.f32`/`div.approx`, +4 `shfl.sync.down.b32`, 9 `tex.base.2d.v4.f16.s32` (s17042–s17101), 3 +`sust.b.2d.v4.b16.zero` (s17165, s17166, s17181). + +**(a) shared staging, s16861–s16891.** Phase 48's D (`%r23106/%r23107` and +`%r23116/%r23117`) is written to a shared array at +`%r391 = %r23368 + 4*(6*((laneid>>2) + (tid.z<<4) ... ) + t)` and `%r393` (the +`(g+8)` variant), two `u32` per lane with a `%r392 > 5` guard on the second. + +**(b) row max, then softmax, s16904–s17022.** After `bar.sync 0` (s16904) +`%tid.x` picks a 6-element row inside a shared array +(`s16930–s16936: ld.shared.u32 [%r23313] … [+20]`, with `%r23313 = %r23380 + +4*(6*x + 48*y)`), and: + +``` +s16948 L42087: max.f16x2 %r23163,%r23164,%r23165 // 5-element row max +s16952 L42100: max.f16 %rs5502,%rs5503,%rs5504 +s16954 L42107: mov.b32 %r23186, {%rs5505, %rs5505} +s16955 L42109: sub.f16x2 %r23172,%r23164,%r23186 // x - rowmax +s16959 L42118: ex2.approx.ftz.f32 %f997, %f1025 // 2^((x-max)*log2e) +s17015 L42237: div.approx.ftz.f32 %f1013, %f1024, %f1042 // 1/rowsum +s17018 L42244: mul.f16x2 %r23187,%r23188,%r23201 +``` + +**This one has a real row maximum** (unlike E9). The `ex2` is a *true* `2^u` via +`mul.ftz.f32` by `0f3FB8AA3B` (= log2 e) plus `ex2.approx.ftz.f32`, not the cubic +mantissa trick. Note the extra `add.ftz.f32 %f1028, %f1027, 0f00000000` at +s16967 (a zero add the compiler left in). + +**(c) texture gather + weighted sum, s17023–s17105.** A 3×3 spatial stencil of +`tex.base.2d.v4.f16.s32` reads from the texture at `param_0+88` +(`s16937 ld.param.u64 %rd672, [%rd681+112]` is a surface; the texture is +`s17040 ld.param.u64 %rd670, [%rd681+88]`), with the 8 neighbour coordinates +clamped by `selp` chains (`s17024–s17035`: `x-1`, `x+1`, `y-1`, `y+1`, both with +`1` as the out-of-range sentinel). Each 3×3 texel is multiplied by one of the +five softmax values with `fma.rn.f16x2` (`s17046 fma.rn.f16x2 %r23206,%r23207, +%r23187,%r23217` with `%r23217 = 0`), the halves are summed +(`s17098 add.f16 %rs5559,%rs5560,%rs5561`) and one more texel is folded with +`fma.rn.f16` (s17103–s17105). + +**(d) second sigmoid and difference, s17106–s17161.** Two more +`1/(1+2^(-log2e·v))` reciprocals (`s17107–s17111`, `s17113–s17117`), three +`mul.f16` products (`s17118–s17120`) and three `sub.f16` differences +(`s17121–s17124`), the `0.25` (`s17122 mov.f32 %f1020, 0f3E800000`) scale +(s17129 `mul.f16x2 %r23268, %r23269, %r23270`), then a **two-step cross-lane +sum**: `shfl.sync.down.b32` with `delta = %r23293 = 1` (s16940) and +`delta = %r23301 = 8` (s16933), each followed by `add.f16x2`, and the same two +steps again on the scalar path (s17149 with delta 1, s17158 with delta 8, then +`add.f16` at s17152 and s17161). The clamp/segment operand is again +`(WARP_SZ<<8)-8192 | 31` and the membermask `%r23303 = -1` (s17026). + +**(e) surface stores, s17162–s17183.** + +``` +s17162 L42567: ld.param.u64 %rd674, [%rd681+120] +s17163 L42568: ld.param.u64 %rd677, [%rd681+128] +s17165 L42571: sust.b.2d.v4.b16.zero [%rd672, {%r23307,%r397}], {%rs5597,%rs5600,%rs5603,%rs5634} +s17166 L42574: sust.b.2d.v4.b16.zero [%rd674, {%r23307,%r397}], {%rs5588,%rs5591,%rs5594,%rs5635} +s17181 L42592: sust.b.2d.v4.b16.zero [%rd677, {%r23335,%r23336}], {%rs5636,%rs5637,%rs5621,%rs5639} +``` + +Three 4-channel b16 surface writes (`param_0+112`, `+120`, `+128`); the third is +taken only for odd `%r398 & 1` (`s17167 and.b32 %r23334, %r398, 1`, `s17169 +mov.pred %p347, 0`, `s17170 xor.pred %p348, %p346, %p347`, s17171 `@%p348 bra`) and +stores `0` in its fourth channel (`s17180 mov.u16 %rs5639, 0`). + +**Inputs:** phase 48's D, the 18 cut values, `param+0/+88/+112/+120/+128`, the +shared staging of (a) and the normed tile's leftovers. +**Outputs:** none (the kernel `ret`s at s17183 / L42596). + +## 4. The plane-arena and surface writes + +`param_0+48` is reached once (`s16148 ld.param.u64 %rd556, [%rd1+-32]` with +`%rd1 = param_0+80` at s4) and is never the base of an `ld.*` in this entry: the +arena is write-only within a launch. The complete set of `st.global.*` / +`sust.b.*` in the entry is: + +* **E46, 16 × `st.global.u32 [%rd4 + 4*idx], v`** — s16174, s16183, s16216, + s16224, s16233, s16241, s16250, s16258, s16267, s16275, s16284, s16292, s16301, + s16309, s16318, s16326 (§3/E46(b)). Value: phase 46's requantised 16×128 + output, 16 b32 per lane. +* **E47, 4 stores to `param_0+56`** — s16772 (`v2.u16`), s16783 (`u32`), + s16817 (`u32`), s16826 (`v2.u16`). +* **E48, 3 `sust.b.2d.v4.b16.zero`** — s17165, s17166, s17181 to surfaces at + `param_0+112/+120/+128`. + +Nothing else in the 17183-statement entry writes to global memory. + +## 5. Uncharacterised + +**U1. The identity of the 11792-byte score bias (P9's C operand).** Phase 9 adds +the f16 table `[8448, 20236)` indexed as +`byte = 8448 + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1)` (verified against phase +9's own C operands: `s6536 C=%r6280,%r6281` ↔ `i=0`, `s6538 C=%r6296,%r6297` ↔ +`i=4`, both loaded by `s6369`/`s6377`). Whether it is a relative position bias, a +learned score bias or a per-lane constant cannot be decided from the PTX. +*Missing:* the weight image's layout description (the `_prep` permutation). + +**U2. The identity of the per-column tables.** `W+98560` (E10's C seed add), +`W+98816` (E14's norm gain), `W+107328` (E15's post-activation add) and +`W+103168`/`111680`/… (the odd phases' GEMM bias) are all read through the same +`W + ((laneid<<2)&12) + off` pattern. Their *role* is computable (see §3) but +their model names are not. + +**U3. The shared-arena layout.** The arena is written by the prologue +(s6054–s6083), by E10 (s10491–s10530) and by E46 (s16348–s16480), and read by +P1–P8 (s6090–s6113), P11–P14 (s10537, s10693, s10732, s10770) and P47 +(s16502–s16574). The prologue writes at `%r235 + 16*laneid + {0,512,1024,1536}` +and `%r235 + 16*laneid + {8192…9728}` (s6058, s6068–s6083) while the P1–P8 reads +use `%r4244 + 16*laneid + 512*k` with **no** `tid.z` term (s6090 ff.) — so at +least one of the two index derivations is not reconstructible without the +`_prep`/launch geometry. *Missing:* the launch's `%tid.z`/`ctaid` ranges, or a +memory dump. + +**U4. E46's/E47's index algebra.** E46(b)'s arena stores and E47's +`param+56` stores each form two index bases from `(laneid&28) | (y<<5)` and +`((g+8)<<2)&28 | (y2<<5)` plus `+512*j`, with `y`/`y2` differing by one in the +row (they are derived from `%r23351` and `%r23353`, both `tid.z<<1`); the shared +staging read in E46(d) uses a *different* index +(`16*g + t` and `16*g + t + 128`). I could not prove the store↔load permutation +from the PTX alone, nor whether `%r23413`'s loop in E47 (s16828–s16830) executes +once or twice per `tid.z` (the guard `%r23413 > 159` at s16489/s16743 is checked +before the first body). *Missing:* a run of the kernel with a plane-arena dump. + +**U5. The MLP block's shape.** §3 establishes, from the pack sources and each +phase's C operand, that the MLP region is: one normed tile feeding every *odd* +phase (P15, P17, …, P45) as its `A`, each odd phase's activation feeding its +*paired* even phase as `A`, and the even phases' `C` chaining (`D16 = … + D14 + +table@107328`, `D18 = … + D16`, …, verified from `P18 C` tracing to P16's mma). +Only the **first** even phase adds the column table `@107328` to the residual +(s11837 versus the table-free `E18`/`E20`/…); every later even phase's `C` is the +previous even phase's `D` alone (E18's `C` operands have no `ld.` in their def-use +chain). Whether the 16 pairs are one wide MLP, a stack of residual blocks, or +something else is a model-level question the PTX cannot answer. +*Missing:* the model source. + +**U6. The stem's shift structure.** Phases 1…8 read the same 24 shared A +fragments in four shift groups (P1/P2 at `+0/1536/…`, P3/P4 at `+512/2048/…`, +P5/P6 at `+1024/…`, P7/P8 at `+1536/…`, s6090–s6113) and accumulate in two +chains (`P1→P3→P5→P7` and `P2→P4→P6→P8`, verified from each phase's C operands: +`s6186 C={%r4296,%r4297}` = P1's D). Whether that is a 2×2 stencil, a 4-tap +1-D convolution, or something else is a property of the high-level model, not of +the PTX. (enc4 has five shift groups and ten phases, so the tap count is a +per-stage constant.) *Missing:* the model source. + +**U7. The meaning of the prologue residual vector.** §1.2 tracks the f16 halves +`%rs1460 …` back to `cvt.rn.f16x2.e4m3x2` of e4m3 values loaded from the plane at +`param_0+8` (`s175`, `s480`, …). What that plane holds (an input colour buffer, +a noise texture, a previous frame) is not determinable from the PTX. + +**U8. The logical meaning of E48's final expression.** The tail computes +`out = (acc − sigmoid(acc)) * 0.25` on three channels gathered by texture from a +3×3 stencil (same shape as enc0's E22(e), whose §6/U6 flags the same gap). + +## 6. Quick acceptance index + +| requirement | where | +|---|---| +| every phase's M/N/K with the arithmetic checked | §2 (rows flagged **N** are banded; the real shapes are derived there) | +| weight image extent | §2 (315732 bytes, max offset 315728 at s16852) | +| phases that read no weight operand | §2 (P9, P10) | +| score epilogue: row max? | **none** — §3/E9, 16 `shfl.sync.bfly` only, no `max` used for a maximum | +| score bias operand | §3/E8 (24 `v4.u32` at `W+8448+512*i`, indexed `4*(n>>1)+m`) | +| attention Q/K/V | §3/E8 (P9 A and B both from P7's D), §3/E9(d) (P8's D transposed) | +| the norm | §3/E14 (row RMS over 128 columns, `+2^-13`, `rsqrt.approx`, gain) | +| the activations | §3/E15, §3/E17 (clamped cubic ramp, 8 groups per phase) | +| patch merge | §3/E46 (arena + shared staging), §3/E47 (`param+56`), §3/E48 (textures + surfaces) | +| per-launch plane-arena writes | §4 | diff --git a/kernels/rr/rrswin_enc4.hip b/kernels/rr/rrswin_enc4.hip new file mode 100644 index 0000000..e6c1955 --- /dev/null +++ b/kernels/rr/rrswin_enc4.hip @@ -0,0 +1,654 @@ +// Native replacement for the Ray Reconstruction denoiser's fifth Swin encoder, +// cuda_dldn_engine_swin_enc4_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the mirror cut is in place and builds and serves, and phases 1-11 are implemented: the +// ten-phase stem (two chains of five 96x32x32 GEMMs over the shared-staged block input, each +// phase's A operand read from the staging arena exactly where the spliced PTX read it) and the +// 64x96 position-only score GEMM with its 11792-byte f16 bias, followed by E11's cubic-exponent +// softmax. Every stem stage and the score stage are bit-exact against the debug oracle (see +// "Ground truth" below). Phases 12-62 -- the P*V GEMM and the 3x3-stencil merge, the sixteen +// 16x160 attention projections with their row-RMS norm, and the twenty banded MLP pairs -- are not +// implemented yet, so the two registers the cut reads back for phase 62 carry lane-distinct +// placeholders and the layer's surface output is still the translated kernel's. +// +// The kernel is one warp per 8x8 token patch with four waves per block (tid.z bounds to 0..3), and +// each wave reads its own 27648-byte slice of the weight image. The PTX this file replaces is +// kernels/extracted/rr/0017-PREPASS_ENTRYPOINT_NAME.ptx. +// +// kernels/rr/swin_enc4_recipe.py's recipe (D4R_RRSWIN_CUT=1) keeps NVIDIA's prologue (the input +// plane read, the e4m3 requantisation, the 30-fragment shared staging and the first weight loads, +// file lines 1-11882) and the surface epilogue (from line 52672) and replaces the 1386 mma of the +// 62 phases with the call below. Without that variable the same recipe builds the debug oracle. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's helpers and +// ZLUDA's own device functions are available. Compiled with -nogpuinc, so only plain clang +// builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the raw image is kept +// and read through a typed accessor. +struct DldnSwinEnc4Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinEnc4Params) == 144, "parameter block"); + +enum : int +{ + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 8, // plane arena (arg008), the 65,945,600-byte allocation the debug store writes past +}; + +#define DEVF __attribute__((device)) static inline +typedef float lds_f32 __attribute__((address_space(3))); +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through ZLUDA's exact +// e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (VERIFIED on all 1024 (n, k) pairs of a tile; the 64*(n&7) term is what keeps columns 16..31 +// from silently reading as zero.) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 columns (laneid ^ 1 and laneid ^ 2). +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +DEVF float bfly1(float v) +{ + return __builtin_bit_cast(float, bfly1_bits(__builtin_bit_cast(uint32_t, v))); +} + +DEVF float bfly2(float v) +{ + return __builtin_bit_cast(float, bfly2_bits(__builtin_bit_cast(uint32_t, v))); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +// add.f16x2 on a packed pair (the PTX's reduction and requantisation steps) +DEVF uint32_t pair_add(uint32_t a, uint32_t b) +{ + return __builtin_bit_cast(uint32_t, __builtin_bit_cast(hv2, a) + __builtin_bit_cast(hv2, b)); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// ZLUDA's relu_keep_nan_halves: a negative (or -0) half becomes +0, NaN is kept. +DEVF uint32_t relu_pair(uint32_t p) +{ + if ((p & 0x8000u) != 0 && (p & 0x7fffu) <= 0x7c00u) { + p &= 0xffff0000u; + } + if ((p & 0x80000000u) != 0 && ((p >> 16) & 0x7fffu) <= 0x7c00u) { + p &= 0x0000ffffu; + } + return p; +} + +// --------------------------------------------------------------------------- +// One GEMM: 96 rows (six m-tiles of 16) x 32 columns, K=32, f16 output. +// +// A lane's A registers hold, for each m-tile and each of its two rows, the eight e4m3 values of +// k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3) and of k + 8; the four lanes that differ in t +// hold the four disjoint eighths of the 32 k's, so two butterfly steps broadcast the other three +// eighths in. The B operand is read from the weight image (waddr) for the lane's own two columns of +// each n-tile. The dot product runs in f32 and is rounded to f16 once, which is what the +// translated mma does: e4m3 x e4m3 products are exact and 32 of them sum exactly in f32, so this +// reproduces the translated kernel bit for bit. +// +// Exactly one of the three C operands carries the seed: `wbias` (a byte pointer at the phase's bias +// offset, 16 bytes per n-tile), `seeds` (four already lane-indexed packed pairs, a zero C seed), or +// `cmat` (48 lane-indexed pairs of one chain, indexed [m-tile][row][n-tile] as +// (mi*2 + row)*4 + nt, the previous phase's D, whose seed differs per row and per n-tile). +// d is [m-tile][row half][n-tile], each entry the packed f16 pair for columns 2t, 2t+1. +DEVF void gemm(const uint32_t* as, const uint8_t* w, int base, const uint8_t* wbias, + const uint32_t* seeds, const uint32_t* cmat, int nmi, int t, + uint32_t d[6][2][4]) +{ + for (int nt = 0; nt < 4; ++nt) { + float bv[2][32]; + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(base, k, n)]); + } + } + for (int mi = 0; mi < nmi; ++mi) { + uint32_t afrag[4]; + for (int j = 0; j < 4; ++j) { + afrag[j] = as[4 * mi + j]; + } + uint32_t fixed = 0; + if (wbias != nullptr) { + fixed = *(const uint32_t*)(wbias + 16 * nt + 4 * t); + } else if (seeds != nullptr) { + fixed = seeds[nt]; + } + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int reg = 0; reg < 2; ++reg) { + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + uint32_t p[4]; + p[0] = afrag[2 * reg + row]; + p[1] = bfly1_bits(p[0]); + p[2] = bfly2_bits(p[0]); + p[3] = bfly1_bits(p[2]); + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const float av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + acc[row][0] += av * bv[0][k]; + acc[row][1] += av * bv[1][k]; + } + } + } + } + for (int row = 0; row < 2; ++row) { + // (mi*2 + row)*4 + nt packs a chain's 6 x 2 x 4 seeds into 48 words + const uint32_t bias_pair = (cmat != nullptr) ? cmat[(mi * 2 + row) * 4 + nt] : fixed; + d[mi][row][nt] = pair_of((half_t)(acc[row][0] + h2f(bias_pair)), + (half_t)(acc[row][1] + h2f(bias_pair >> 16))); + } + } + } +} + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_enc4_recipe.py: with +// D4R_RRSWIN_DEBUG=p1 (p2, p3, ... or a) the same splice keeps NVIDIA's whole body and stores that +// stage's registers into the plane arena at +46,000,000, which the kernel never otherwise writes, +// and the launch dump then holds the translated values for a block/lane. Built with +// -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this body stores the same +// registers of its own phase n in the same order, so the two dumps compare byte for byte. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +// The same geometry as the recipe's debug_block(): the slot index is +// `wgid.x + 32*wgid.y + 256*workitem_id_z`, capped at 64 slots, and a store only happens when every +// component is in range, so the mapping stays injective however the kernel is launched. enc4 runs +// four waves per block (tid.z bounds to 0..3) and each wave computes a different result -- its own +// 27648-byte weight slice, its own staging slots -- so the wave has to be part of the index. The +// slot is max(8192, 32*nregs*4) bytes, rounded up to a power of two. +// +// DEBUG_BASE is a build-time define so the native store and the oracle splice can be moved +// together; enc0's 46,000,000 is unusable here because enc4's arena is smaller and the launch +// dump only exposes arena offsets below 26,378,240 (see the recipe). The 64-slot cap bounds the +// widest stage (160 registers, a 32,768-byte slot) to 2 MiB. +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 20000000 +#endif +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + const uint32_t bx = __builtin_amdgcn_workgroup_id_x(); + const uint32_t by = __builtin_amdgcn_workgroup_id_y(); + const uint32_t bz = __builtin_amdgcn_workitem_id_z(); + const uint64_t block = bx + 32ull * by + 256ull * bz; + if (bx >= 32u || by >= 8u || bz >= 4u || block >= 64ull) { + return; + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + const uint64_t want = (uint64_t)n * 128ull > 8192ull ? (uint64_t)n * 128ull : 8192ull; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + (uint64_t)D4R_RRSWIN_DEBUG_BASE + block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// stage registers in the oracle's order: the phase's mma, m-tile major, n-tile minor, each as the +// (row g, row g+8) pair the mma writes. +DEVF void stage_regs(const uint32_t d[6][2][4], uint32_t regs[48]) +{ + int i = 0; + for (int mi = 0; mi < 6; ++mi) { + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// The stem, phases 1-10. Five shift groups of six staged A fragments, two chains of five +// accumulations: phase 2g+1 and 2g+2 both read shift group g, phase 2g+3 accumulates phase 2g+1's +// result and phase 2g+4 accumulates phase 2g+2's. Nothing is requantised between them -- the +// chain's C operand is the previous phase's f16 D pair -- so the stem is ten GEMMs over the same +// five input fragments with five different weight blocks. +// +// The staged fragments are read from the shared arena at `smem + 16*laneid + 512*k`, k = 0..29, +// with *no* tid.z term -- exactly the addresses the spliced PTX's 30 ld.shared.v4 used (the +// prologue's store side adds tid.z, so each fragment is written by the one wave that owns it and +// all four waves read all thirty; the body does not need to know that). +// +// The stem's weight block starts at byte 320 of the wave's slice, phase p's at +// 320 + 1024*((p-1)/2) + 5120*((p-1)%2) -- VERIFIED against the PTX's own add.s64 immediates +// (s7550, s7581, s7612, s7643, s7674, s7705, s7736, s7767, s7798, s7829). +// +// Phase 11 and later read the wave slice too (E10's 24 score-bias loads are at 10560 + 512*i of +// the same per-wave base); from E12 on the loads are off the image base directly. +DEVF void stem_group(const lds_u32* smem, int g, uint32_t lane, uint32_t as[24]) +{ + for (int mi = 0; mi < 6; ++mi) { + const lds_u32* src = smem + 128u * (uint32_t)(5 * mi + g) + 4u * lane; + for (int j = 0; j < 4; ++j) { + as[4 * mi + j] = src[j]; + } + } +} + +// The next group's C operand: the odd chain's seed is the odd phase's D, the even chain's the even +// phase's, each at the same (m-tile, row, n-tile) -- VERIFIED against the PTX, where phase p's mma +// i reads phase p-2's mma i as its C (s7616 reads %r5333/%r5334, phase 1's first D pair, and so on +// for every odd and even phase up to 10). +// The two chains' seeds live side by side in one 96-word array: the odd chain at 0..47, the even +// chain at 48..95, each packed [m-tile][row][n-tile] as (mi*2 + row)*4 + nt. +// +// The previous layout indexed (4*mi + row)*4 + nt, which strides four words per (m-tile, row) +// pair and so reaches 87 for mi = 5 -- past a 48-word array. m-tiles 0-2 stayed inside it (their +// seed is zero, so the stale contents were invisible) and m-tiles 3-5 read past the end, which is +// exactly the range that disagreed with the oracle. The even chain was also written at +24, +// overlapping the odd chain instead of following it. +DEVF void stem_seed(const uint32_t dodd[6][2][4], const uint32_t deven[6][2][4], + uint32_t cmat[96]) +{ + for (int mi = 0; mi < 6; ++mi) { + for (int row = 0; row < 2; ++row) { + for (int nt = 0; nt < 4; ++nt) { + cmat[(mi * 2 + row) * 4 + nt] = dodd[mi][row][nt]; + cmat[48 + (mi * 2 + row) * 4 + nt] = deven[mi][row][nt]; + } + } + } +} + +// --------------------------------------------------------------------------- +// Phase 11, the 64x96 score GEMM. Both operands come from phase 9's accumulators (position-only +// attention, S = bias + Q*Q^T): A is m-tile `a` of the 96-row block, B is the same 96 rows read as +// 12 eight-row groups, `nt = 2*mb + r` being m-tile mb's row half r (so the score's 96 columns are +// the 96 rows of the block, the 8x8 token patch plus its halo). +// +// E10 packs each operand's fragment exactly as the mma consumes it (VERIFIED against the PTX's own +// mov.b32 list, s7908-s8027): fragment `a`'s register 2*reg+row is +// e4m3x2(row_words(row 16a + g + 8*row)[reg]) +// and B fragment `nt`'s words 0 and 1 are the same two words of row 16*(nt/2) + 8*(nt%2) + g. Both +// sides therefore use one byte layout -- byte j of a word is column 2t + (j&1) + 16*((j>>1)&1) of +// word `reg`'s half -- so the dot product is the same 32-term pairing on both sides and two butterfly +// steps bring the other three eighths of the 32 k's in, exactly as enc0's phase 5 does. +// +// A lane only holds its own two rows of the group, and the mma's B fragment is indexed by +// groupID while the score's column is indexed by threadID_in_group, so every lane needs eight rows +// it does not hold. They go through the arena as e4m3 words: 12 groups x 8 rows x 4 k-eighths x +// two words = 3072 bytes, at arena offset 0 -- shift group 0's staging slots, which nothing reads +// after phase 10. + +// the f16 at (row, col) of a 96x32 block of packed pairs, col = 8*n-tile + 2t + c +DEVF half_t dcell(const uint32_t d[6][2][4], int row, int col) +{ + const uint32_t p = d[row >> 4][(row >> 3) & 1][col >> 3]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +// the lane's two e4m3-packed words for row r: word 0 packs columns (2t, 2t+1) and (16+2t, +// 16+2t+1), word 1 the columns 8 and 24 -- E10's pack, which is also the mma's own A fragment order +DEVF void row_words(const uint32_t d[6][2][4], int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// out[i][m]: word i as lane t^m holds it, which is what the dot product pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + +// the 32-term dot product of two packed operand word pairs, in the mma's own k order +DEVF float dot32(const uint32_t a[2][4], const uint32_t b[2][4]) +{ + float acc = 0.0f; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + acc += e4m3_to_f32((a[i][m] >> (8 * j)) & 0xffu) + * e4m3_to_f32((b[i][m] >> (8 * j)) & 0xffu); + } + } + } + return acc; +} + +// Phase 11's C seeds: the 11792-byte f16 table at wave byte 10560, read as 24 tiles of four words +// per lane at 10560 + 512*j. Each word is one (row, n-tile) f16 pair -- columns 2t and 2t+1 -- so a +// tile holds two n-tiles x two rows, and the mma's own C operands fix the order: for the tile +// a + 4*(nt>>1) the four words are (row g, nt), (row g+8, nt), (row g, nt+1), (row g+8, nt+1). The +// PTX confirms the tile stride: phase 11's first A-tile reads 10560 and 10568 for n-tiles 0 and 1 +// (s8028, s8029), 12608 and 12616 for n-tiles 2 and 3 (s8030, s8031), and the second A-tile starts +// at 11072 (s8040), i.e. 512 bytes per A-tile. +DEVF uint32_t score_seed(const uint8_t* wv, uint32_t lane, int a, int nt, int row) +{ + return *(const uint32_t*)(wv + 10560 + 512u * (uint32_t)(a + 4 * (nt >> 1)) + 16u * lane + + 4u * (uint32_t)(2 * (nt & 1) + row)); +} + +// The key rows go through the arena at word index 64*nt + 8*row + 2*t + i: twelve groups, eight +// rows, four k-eighths and two words, 768 words. The lane publishes the rows it holds, row g of +// every group, and then reads back the two rows (2t and 2t+1) its own two output columns need. +DEVF void score(lds_u32* smem, const uint32_t dodd[6][2][4], const uint8_t* wv, + uint32_t lane, int t, int g, uint32_t d11[4][2][12]) +{ +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + uint32_t w[2]; + row_words(dodd, 16 * (nt >> 1) + 8 * (nt & 1) + g, w); + smem[64 * nt + 8 * g + 2 * t] = w[0]; + smem[64 * nt + 8 * g + 2 * t + 1] = w[1]; + } + __builtin_amdgcn_wave_barrier(); + for (int a = 0; a < 4; ++a) { + uint32_t aw[2][2]; + row_words(dodd, 16 * a + g, aw[0]); + row_words(dodd, 16 * a + g + 8, aw[1]); + uint32_t av[2][2][4]; + bfly2x4(aw[0], av[0]); + bfly2x4(aw[1], av[1]); + for (int nt = 0; nt < 12; ++nt) { + float acc[2][2] = {{0.0f, 0.0f}, {0.0f, 0.0f}}; + for (int c = 0; c < 2; ++c) { + // the mma's B fragment is indexed by groupID, so the score's columns 2t and 2t+1 + // are the rows 2t and 2t+1 of the group -- held by four other lanes each + const int col = 2 * t + c; + uint32_t kb[2][4]; +#pragma unroll + for (int i = 0; i < 2; ++i) { +#pragma unroll + for (int m = 0; m < 4; ++m) { + kb[i][m] = smem[64 * nt + 8 * col + 2 * (t ^ m) + i]; + } + } + acc[0][c] = dot32(av[0], kb); + acc[1][c] = dot32(av[1], kb); + } + for (int row = 0; row < 2; ++row) { + // the seed is per row: the mma's C pair is (row g, row g+8), each a packed f16 pair + const float bias = h2f(score_seed(wv, lane, a, nt, row)); + d11[a][row][nt] = pair_of((half_t)(acc[row][0] + bias), + (half_t)(acc[row][1] + bias)); + } + } + } +} + +// --------------------------------------------------------------------------- +// E11, the score softmax. Byte-for-byte enc0's E5 with the same 64x96 shape (four m-tiles of +// sixteen rows, twelve n-tiles of eight columns): per element the scale, the clamp and the two +// clamped-cubic fma pairs that move the mantissa into the exponent field; then the in-lane sum tree, +// two butterfly steps that finish the row's 96 columns, the two halves' add, the reciprocal and +// the twelve products. There is no row maximum in this epilogue -- every max.f16x2 belongs to the +// clamp. +DEVF half_t hf16(uint16_t bits) +{ + return __builtin_bit_cast(half_t, bits); +} + +DEVF hv2 hv2_of(uint32_t p) +{ + return __builtin_bit_cast(hv2, p); +} + +DEVF uint32_t u32_of(hv2 v) +{ + return __builtin_bit_cast(uint32_t, v); +} + +// ZLUDA's own rcp.approx.ftz.f32 helper: calling it is what makes the reciprocal bit-exact. +extern "C" __attribute__((device)) float __zluda_ptx_impl_rcp_approx_f32(float); + +// one element: the scale, the clamp, the two clamped-cubic fma pairs and the trick that moves the +// mantissa into the exponent field ((u << 5) & 0x7FE07FE0 over the pair) +DEVF uint32_t expval_pair(uint32_t score) +{ + hv2 m = hv2_of(score) * __builtin_bit_cast(hv2, pair_of(hf16(0x2466), hf16(0x2466))); + m = __builtin_elementwise_max(m, __builtin_bit_cast(hv2, pair_of(hf16(0xb873), hf16(0xb873)))); + m = __builtin_elementwise_min(m, __builtin_bit_cast(hv2, pair_of(hf16(0x3873), hf16(0x3873)))); + const hv2 tt = __builtin_elementwise_fma(m, -m, + __builtin_bit_cast(hv2, pair_of(hf16(0x3b6b), hf16(0x3b6b)))); + const uint32_t u = u32_of(__builtin_elementwise_fma(m, tt, + __builtin_bit_cast(hv2, pair_of(hf16(0x3d80), hf16(0x3d80))))); + return (u << 5) & 0x7fe07fe0u; +} + +// one row: the twelve exponent pairs, the in-lane sum tree +// (((e0+e2)+(e4+e6))+(e8+e10)) + (((e1+e3)+(e5+e7))+(e9+e11)), the two butterfly steps that finish +// the row's 96 columns, the two halves' add, the reciprocal and the twelve products +DEVF void row_probs(const uint32_t d11[4][2][12], int mi, int rh, uint32_t prob[12]) +{ + hv2 ev[6], eo[6]; +#pragma unroll + for (int i = 0; i < 6; ++i) { + ev[i] = hv2_of(expval_pair(d11[mi][rh][2 * i])); + eo[i] = hv2_of(expval_pair(d11[mi][rh][2 * i + 1])); + } + const hv2 even = ((ev[0] + ev[1]) + (ev[2] + ev[3])) + (ev[4] + ev[5]); + const hv2 odd = ((eo[0] + eo[1]) + (eo[2] + eo[3])) + (eo[4] + eo[5]); + hv2 s = even + odd; + s = s + hv2_of(bfly1_bits(u32_of(s))); + s = s + hv2_of(bfly2_bits(u32_of(s))); + const uint32_t p = u32_of(s); + // the PTX broadcasts the f16 sum of the two halves (add.f16) and takes cvt.f32.f16 of it: + // the value, not its bits + const half_t r = (half_t)__zluda_ptx_impl_rcp_approx_f32((float)(half_lo(p) + half_hi(p))); + const uint32_t rcp = pair_of(r, r); +#pragma unroll + for (int i = 0; i < 6; ++i) { + prob[2 * i] = u32_of(ev[i] * hv2_of(rcp)); + prob[2 * i + 1] = u32_of(eo[i] * hv2_of(rcp)); + } +} + +// phase 11's 96 registers in the oracle's order: mma, m-tile major, n-tile minor, each as the +// (row g, row g+8) pair the mma writes +DEVF void score_regs(const uint32_t d11[4][2][12], uint32_t regs[96]) +{ + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int nt = 0; nt < 12; ++nt) { + regs[i++] = d11[mi][0][nt]; + regs[i++] = d11[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. The six 16-row fragments of shift group 0 arrive in the first mma's operand order +// (.f16.e4m3 fragments of four b32 each), then phase 1's C seed (%r11676, zero), the weight image, +// the parameter block and the address of the shared arena. +// +// The five registers the region's epilogue reads -- %r29719 (the x extent, param_0+0), %r31372 and +// %r31382 (phase 62's D pair), %r31608 (%tid.z) and %r31615 (the shared arena's address) -- cross +// the cut through the arena, not `call.uni`'s return parameters: ZLUDA lowers those to the +// function's LLVM return type (emit.rs's emit_call makes one value, or a +// get_or_create_struct_type struct for several, and distributes them with LLVMBuildExtractValue), +// so there is no .param-space object and no pointer is formed -- the callee reads 0x0 in all five +// slots. The body writes them at `scratch + 20*laneid + 4*i` as its last act and the splice reads +// them back immediately, before E62 issues a single shared store. +extern "C" __attribute__((device)) void d4r_swin_enc4( + uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6, + uint32_t a7, uint32_t a8, uint32_t a9, uint32_t a10, uint32_t a11, uint32_t a12, uint32_t a13, + uint32_t a14, uint32_t a15, uint32_t a16, uint32_t a17, uint32_t a18, uint32_t a19, uint32_t a20, + uint32_t a21, uint32_t a22, uint32_t a23, uint32_t c0, + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const uint32_t as1[24] = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, + a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23}; + // Address space 3 (the shared arena) explicitly: a generic access lowers to flat, which faults. + lds_u32* const smem = (lds_u32*)(uintptr_t)scratch; + const uint32_t lane = lane_id(); + const int t = (int)(lane & 3); // the lane's two columns of each n-tile + const int z = (int)__builtin_amdgcn_workitem_id_z(); + // the four waves each read their own 27648-byte slice of the weight image (s7507: tid.z*13824, + // then s7508 doubles it) + const uint8_t* const wv = w + 27648u * (uint32_t)z; + + uint32_t dodd[6][2][4]; // phases 1, 3, 5, 7, 9 + uint32_t deven[6][2][4]; // phases 2, 4, 6, 8, 10 + // Two chains' C seeds: odd at 0..47, even at 48..95. Phase 1/2's seed is %r11676, which is + // zero, so both start zeroed. + uint32_t cmat[96] = {0}; + uint32_t as[24]; +#if D4R_RRSWIN_DEBUG_STAGE == -1 + // Stage "a": the 24 A registers the cut hands over plus the C seed, in the oracle's order. + // This pins the prologue handoff independently of the body's arithmetic. 28 registers, not + // 25: the lane stride must be a multiple of 16 bytes so the oracle's st.global.v4.u32 stays + // aligned (see the recipe's _stage_table). The last four repeat the C seed, matching it. + { + uint32_t regs[28]; + for (int j = 0; j < 24; ++j) { + regs[j] = as1[j]; + } + for (int j = 24; j < 28; ++j) { + regs[j] = c0; + } + debug_store(prm, regs, 28); + } +#endif + + // ---- the stem: five shift groups, two chains of five accumulations ----- + for (int g = 0; g < 5; ++g) { + stem_group(smem, g, lane, as); + // Shift group 0 comes from the 24 registers the cut hands over: phase 1's 24 mma consume + // exactly the fragments at arena byte offsets 0, 2560, 5120, 7680, 10240, 12800, in that + // order (VERIFIED against the mma list at lines 11883-12044, which names %r11754, %r11774, + // %r11794, %r11814, %r11834 and %r11854 as its six A operands). Groups 1-4 are not + // live-out of the cut, so they are read from the arena, where the prologue staged them per + // wave (base `tid.z*2560`, s11638) -- see stem_group. + if (g == 0) { + for (int j = 0; j < 24; ++j) { + as[j] = as1[j]; + } + } + gemm(as, wv, 320 + 1024 * g, nullptr, nullptr, cmat, 6, t, dodd); +#if D4R_RRSWIN_DEBUG_STAGE + if (D4R_RRSWIN_DEBUG_STAGE == 2 * g + 1) { + uint32_t regs[48]; + stage_regs(dodd, regs); + debug_store(prm, regs, 48); + } +#endif + gemm(as, wv, 5440 + 1024 * g, nullptr, nullptr, cmat + 48, 6, t, deven); +#if D4R_RRSWIN_DEBUG_STAGE + if (D4R_RRSWIN_DEBUG_STAGE == 2 * g + 2) { + uint32_t regs[48]; + stage_regs(deven, regs); + debug_store(prm, regs, 48); + } +#endif + // the next group accumulates: its C operand is this pair's D, per (m-tile, row, n-tile) + stem_seed(dodd, deven, cmat); + } + + // ---- phase 11, the score, and E11's softmax ---------------------------- + uint32_t d11[4][2][12]; + score(smem, dodd, wv, lane, t, (int)(lane >> 2), d11); +#if D4R_RRSWIN_DEBUG_STAGE + if (D4R_RRSWIN_DEBUG_STAGE == 11) { + uint32_t regs[96]; + score_regs(d11, regs); + debug_store(prm, regs, 96); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE + if (D4R_RRSWIN_DEBUG_STAGE == 12) { + // E11's output: the softmax probabilities as phase 12 packs them into its A fragments + uint32_t regs[96]; + int i = 0; + for (int mi = 0; mi < 4; ++mi) { + for (int ks = 0; ks < 3; ++ks) { + for (int rh = 0; rh < 2; ++rh) { + uint32_t prob[12]; + row_probs(d11, mi, rh, prob); + regs[i++] = e4m3x2(prob[4 * ks]) | (e4m3x2(prob[4 * ks + 2]) << 16); + regs[i++] = e4m3x2(prob[4 * ks + 1]) | (e4m3x2(prob[4 * ks + 3]) << 16); + } + } + } + debug_store(prm, regs, 96); + } +#endif + + (void)c0; + // ---- handing the five accumulators back -------------------------------- + lds_u32* const out = smem + 5u * lane_id(); + out[0] = *(const uint32_t*)prm; // %r29719, param_0+0 + // %r31372 / %r31382 are phase 62's D pair; phases 11-62 are not implemented yet, so the two + // slots carry lane-distinct values that keep the read-back path observable without producing + // wild magnitudes. + out[1] = (uint32_t)lane_id() + 32u; + out[2] = (uint32_t)lane_id() + 64u; + out[3] = (uint32_t)z; // %r31608, %tid.z + out[4] = scratch; // %r31615, the shared arena's address +} \ No newline at end of file diff --git a/kernels/rr/rrswin_enc4_epilogues.md b/kernels/rr/rrswin_enc4_epilogues.md new file mode 100644 index 0000000..7b4e04a --- /dev/null +++ b/kernels/rr/rrswin_enc4_epilogues.md @@ -0,0 +1,799 @@ +# `cuda_dldn_engine_swin_enc4_kernel` — the epilogues of phases 1…62 + +Companion to `kernels/rr/rr_layer_spec.py enc4`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0017-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc4_kernel`. + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at its first line). **`LNNNNN` is + the physical line** of the same instruction in the corpus file, so every claim + can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and the + next phase's first `mma`. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_enc4_kernel_param_0+40]` (s9), globalised as + `cvta.to.global.u64 %rd3, %rd2` (s10). Every `ld.weak.global.ca.v4.u32` in an + epilogue reads `W + 16*laneid + imm`. (s20229 re-reads the same parameter; the + pointer is not cached.) +* `S` denotes the plane arena: `param_0+48`, reached as + `ld.param.u64 %rd808, [%rd1+-32]` with `%rd1 = param_0+80` (`add.s64 %rd1, + %rd9, 80`, s4) then `cvta.to.global.u64 %rd5, %rd808` (s19817–s19818). +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same cols)`, + `g = laneid>>2`, `t = laneid&3`. +* `rr_layer_spec.py`'s printed `M`/`N`/`K` come from `geom()` (distinct A/B + fragment counts and accumulator-chain length). The `Phase` object's own + `w_min..w_max`/`n_tiles`/`k_slots` fields use a different (512-byte-block) + convention and disagree with `geom()` on the stem phases; §2 uses `geom()` and + checks the arithmetic explicitly. +* Anything I could not pin down from the PTX is in §6 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, 533844 bytes) | `ld.param.u64 %rd2, [param_0+40]` | s9 (re-read s20229, s21313) | +| `S` (plane arena, `param+48`) | `ld.param.u64 %rd808, [%rd1+-32]` → `cvta.to.global.u64 %rd5, %rd808` | s19817–s19818 | +| output buffer (`param+56`) | `ld.param.u64 %rd849, [%rd945+-24]` with `%rd945 = param_0+80` | s21037–s21038 | +| input plane (`param+8`) | `ld.param.u64 %rd11, [%rd1+-72]` → `cvta.to.global.u64 %rd4, %rd11` | s22–s23 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r575, %r576}, [param_0+0]`; re-read as `ld.param.v2.u32 {%r29719, %r29720}, [%rd940+-80]` | s15; s20222 | +| block origin `(x0, y0)` | `%r570 = ctaid.x<<3`, `%r1 = %r570 - %rs124`; `%r574 = ctaid.y<<3`, `%r3 = %r574 - %rs125`; `%r2 = %r1 - 1`, `%r6 = %r3 - 1`; `%rs124/%rs125` from `ld.param.v2.u16 [param_0+80]` | s2, s3, s7, s12, s13, s14, s16, s5 | +| `%rd9` = `param_0` | `mov.b64 %rd9, cuda_dldn_engine_swin_enc4_kernel_param_0` | s1 | +| shared base `%r11752` | `mov.u32 %r11752, _ZZ33cuda_dldn_engine_swin_enc4_kernel33DldnEngineSwinEncParamsStructBaseE4smem` | s7511 | +| `%r31615` (second copy) | same `mov.u32` in E62 | s21312 | +| per-lane weight address | `mul.wide.u32 %rd, %laneid, 16` + `add.s64 %rd, %rd2, %rd` | e.g. s11983–s11984, s12267–s12268 | +| per-lane *table* address | `shl.b32 %r, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rd, %r, 12` → `add.s64 %rd, %rd74/…, %rd` = `W + ((laneid<<2)&12)` | e.g. s13552–s13555 | + +As in enc0/enc3, a `ld.global.v2.u16` or `ld.global.u32` with that addressing reads +the **same 16-byte record from the four lanes with equal `laneid&3`**, so those +tables are indexed by column, not by row. + +The `%tid.z` guard `setp.gt.u32 %p8, %r9, 3; @%p8 bra` at s20–s21 bounds `%tid.z` +to 0…3 for the whole mma region; the eight phases that stage through shared memory +(E12→P13…P20) add `(tid.z << 11)` (s11969) resp. `(tid.z << 9)` (s12028) to the +arena base. + +### 1.2 Constants that survive between epilogues + +| register | first definition | literal | meaning | +|---|---|---|---| +| `%f476` | s8077 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | f16 `0x2466` = 0.017181396484375 (softmax input scale) | +| `%fd383` | s8081 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | f16 clamp lower bound | +| `%fd385` | s8086 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | f16 clamp upper bound | +| `%f478` | s8092 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | cubic coefficient | +| `%f480` | s8097 `mov.f32 %f480, 0f3FB00000` | 1.375 | cubic constant term | +| `%fd1` | s5976 `mov.f64 %fd1, 0d3F20000000000000` | 2⁻¹³ | norm epsilon | +| `%f1117` | s13641 `mov.f32 %f1117, 0f3ED306EB` | 0.4121621549129486 | activation coefficient | +| `%f1118` | s13644 `mov.f32 %f1118, 0f3DA60DD6` | 0.0810810774564743 | activation coefficient | +| `%f1119` | s13647 `mov.f32 %f1119, 0f3F000000` | 0.5 | activation offset | +| `%f1120` | s13650 `mov.f32 %f1120, 0f40000000` | 2.0 | activation clamp | +| `%f1152` | s21429 `mov.f32 %f1152, 0f3F800000` | 1.0 | softmax dividend | +| `%f1148` | s21606 `mov.f32 %f1148, 0f3E800000` | 0.25 | final output scale | + +`%f1117…%f1120` are defined inside E21 (phase 21's epilogue) and re-materialised +inside every odd phase's epilogue (E23, E25, … E59, e.g. `s14094–s14100 +cvt.rn.f16.f32 low, %f1117 … %f1120`), exactly as in enc3. + +Live across the whole mma region (defined in the prologue, read by every warp +reduction): + +| register | statement | value | used as | +|---|---|---|---| +| `%r10789` | s7548 | 1 | `shfl.sync.bfly` `b` operand, bit 0 | +| `%r10798` | s7549 | 2 | `shfl.sync.bfly` `b` operand, bit 1 | +| `%r10800` | s10280 | −1 | `shfl.sync.bfly` membermask | + +The `c` (clamp/segment) operand of every butterfly is built as +`%r = (WARP_SZ << 8) - 8192` then `or.b32 %r, %r, 31` (e.g. s10279), i.e. 31 for a +32-lane warp. The `shfl.sync.down` cascade in E62 uses `%r31545 = 1` (s21424), +`%r31553 = 8` (s21417) and membermask `%r31555 = -1` (s21510). + +The long-lived **residual vector**: 48 `mov.b32 {%rsA, %rsB}, %r317xx` +statements (e.g. s5443, s5446 …) split registers produced by +`cvt.rn.f16x2.e4m3x2 %r31707, %rs128` (s5439) into f16 halves. `%rs128` comes from +a prologue `ld.global.v2.u16` off the input plane (`param_0+8`, s22–s23). These +halves are the second addend of the E12 column-table add (§3/E12). + +### 1.3 Quantisation helpers + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `cvt.rn.f16x2.e4m3x2` — its inverse, used only in the prologue (s5439 ff.). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (each step rounded through f16). + +### 1.4 The shared arena + +`_ZZ…E4smem` is declared **16384 bytes**. The mma A operands of phases 1…10 come +from 30 `ld.shared.v4.u32` at `%r11753 = %r11752 + 16*laneid` plus +`512*k`, `k = 0…29` (s7513–s7542, lines 11835–11864); phases 13…20 come from 8 +such loads at `%r11752 + (tid.z<<9) + 16*laneid + {0,2048,…,14336}` (s12033, +s12265, s12312, …, s12547); phase 61 comes from 80 `ld.shared.u32` +(s20242–s21030). The arena is written by the prologue (s7494–s7504), by E12 +(s11986–s12025) and by E60 (s20051–s20215). See §6/U3. + +## 2. Phase table summary + +Reproduced from `rr_layer_spec.py enc4` with `M`, `N`, `K` from `geom()` and +`check = (M/16)·(N/8)·(K/32)`: + +| # | stmt range | lines | M | N | K | nA | nB | chains | klens | mma | check | =? | weight bytes | C bias bytes | epi | +|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +| 1 | s7554–s7577 | L11883–12044 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 320..844 | – | 7 | +| 2 | s7585–s7608 | L12064–12225 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 5440..5964 | – | 7 | +| 3 | s7616–s7639 | L12245–12406 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 1344..1868 | – | 7 | +| 4 | s7647–s7670 | L12426–12587 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 6464..6988 | – | 7 | +| 5 | s7678–s7701 | L12607–12768 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 2368..2892 | – | 7 | +| 6 | s7709–s7732 | L12788–12949 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 7488..8012 | – | 7 | +| 7 | s7740–s7763 | L12969–13130 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 3392..3916 | – | 7 | +| 8 | s7771–s7794 | L13150–13311 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 8512..9036 | – | 7 | +| 9 | s7802–s7825 | L13331–13492 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 4416..4940 | – | 7 | +| 10 | s7833–s7856 | L13512–13673 | 96 | 32 | 32 | 6 | 4 | 24 | 1 | 24 | 24 | Y | 9536..10060 | – | 171 | +| 11 | s8028–s8075 | L14061–14390 | 64 | 96 | 32 | 4 | 12 | 48 | 1 | 48 | 48 | Y | – | 10560..22348 | 3844 | +| 12 | s11920–s11967 | L24541–24870 | 192 | 96 | 96 | 12 | 12 | 16 | 3 | 48 | 432 | **N** | – | – | 274 | +| 13 | s12242–s12261 | L25484–25617 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 22848..27468 | – | 27 | +| 14 | s12289–s12308 | L25675–25808 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 50496..55116 | – | 27 | +| 15 | s12336–s12355 | L25866–25999 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 78144..82764 | – | 27 | +| 16 | s12383–s12402 | L26057–26190 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 105792..110412 | – | 27 | +| 17 | s12430–s12449 | L26248–26381 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 133440..138060 | – | 27 | +| 18 | s12477–s12496 | L26439–26572 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 161088..165708 | – | 27 | +| 19 | s12524–s12543 | L26630–26763 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 188736..193356 | – | 27 | +| 20 | s12571–s12590 | L26821–26954 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 216384..221004 | – | 1029 | +| 21 | s13620–s13639 | L29419–29552 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 222144..226764 | 227264..227312 | 321 | +| 22 | s13961–s13980 | L30506–30639 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 227328..231948 | – | 92 | +| 23 | s14073–s14092 | L30842–30975 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 232768..237388 | 237888..237936 | 172 | +| 24 | s14265–s14284 | L31538–31671 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 237952..242572 | – | 92 | +| 25 | s14377–s14396 | L31874–32007 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 243072..247692 | 248192..248240 | 172 | +| 26 | s14569–s14588 | L32570–32703 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 248256..252876 | – | 92 | +| 27 | s14681–s14700 | L32906–33039 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 253376..257996 | 258496..258544 | 172 | +| 28 | s14873–s14892 | L33602–33735 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 258560..263180 | – | 92 | +| 29 | s14985–s15004 | L33938–34071 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 263680..268300 | 268800..268848 | 172 | +| 30 | s15177–s15196 | L34634–34767 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 268864..273484 | – | 92 | +| 31 | s15289–s15308 | L34970–35103 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 273984..278604 | 279104..279152 | 172 | +| 32 | s15481–s15500 | L35666–35799 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 279168..283788 | – | 92 | +| 33 | s15593–s15612 | L36002–36135 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 284288..288908 | 289408..289456 | 172 | +| 34 | s15785–s15804 | L36698–36831 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 289472..294092 | – | 92 | +| 35 | s15897–s15916 | L37034–37167 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 294592..299212 | 299712..299760 | 172 | +| 36 | s16089–s16108 | L37730–37863 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 299776..304396 | – | 92 | +| 37 | s16201–s16220 | L38066–38199 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 304896..309516 | 310016..310064 | 172 | +| 38 | s16393–s16412 | L38762–38895 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 310080..314700 | – | 92 | +| 39 | s16505–s16524 | L39098–39231 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 315200..319820 | 320320..320368 | 172 | +| 40 | s16697–s16716 | L39794–39927 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 320384..325004 | – | 92 | +| 41 | s16809–s16828 | L40130–40263 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 325504..330124 | 330624..330672 | 172 | +| 42 | s17001–s17020 | L40826–40959 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 330688..335308 | – | 92 | +| 43 | s17113–s17132 | L41162–41295 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 335808..340428 | 340928..340976 | 172 | +| 44 | s17305–s17324 | L41858–41991 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 340992..345612 | – | 92 | +| 45 | s17417–s17436 | L42194–42327 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 346112..350732 | 351232..351280 | 172 | +| 46 | s17609–s17628 | L42890–43023 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 351296..355916 | – | 92 | +| 47 | s17721–s17740 | L43226–43359 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 356416..361036 | 361536..361584 | 172 | +| 48 | s17913–s17932 | L43922–44055 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 361600..366220 | – | 92 | +| 49 | s18025–s18044 | L44258–44391 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 366720..371340 | 371840..371888 | 172 | +| 50 | s18217–s18236 | L44954–45087 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 371904..376524 | – | 92 | +| 51 | s18329–s18348 | L45290–45423 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 377024..381644 | 382144..382192 | 172 | +| 52 | s18521–s18540 | L45986–46119 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 382208..386828 | – | 92 | +| 53 | s18633–s18652 | L46322–46455 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 387328..391948 | 392448..392496 | 172 | +| 54 | s18825–s18844 | L47018–47151 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 392512..397132 | – | 92 | +| 55 | s18937–s18956 | L47354–47487 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 397632..402252 | 402752..402800 | 172 | +| 56 | s19129–s19148 | L48050–48183 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 402816..407436 | – | 92 | +| 57 | s19241–s19260 | L48386–48519 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 407936..412556 | 413056..413104 | 172 | +| 58 | s19433–s19452 | L49082–49215 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 413120..417740 | – | 92 | +| 59 | s19545–s19564 | L49418–49551 | 80 | 160 | 160 | 5 | 20 | 4 | 5 | 20 | 500 | **N** | 418240..422860 | 423360..423408 | 172 | +| 60 | s19737–s19756 | L50114–50247 | 16 | 160 | 32 | 1 | 20 | 20 | 1 | 20 | 20 | Y | 423424..428044 | – | 1381 | +| 61 | s21138–s21217 | L51887–52440 | 320 | 640 | 640 | 20 | 80 | 4 | 20 | 80 | 32000 | **N** | 428544..448524 | 530944..530992 | 117 | +| 62 | s21335–s21344 | L52605–52668 | 80 | 80 | 160 | 5 | 10 | 2 | 5 | 10 | 250 | **N** | 531264..533324 | 533824..533840 | 323 | + +**Arithmetic check.** Rows 1–11, 13–16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, +38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58 and 60 satisfy +`M/16 · N/8 · K/32 == mma`: every A×B tile of the grid is evaluated once and the +printed `M`/`N`/`K` is the true GEMM shape. + +Rows 12, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, +57, 59, 61 and 62 do **not** and are *banded*: only a diagonal band of the M×N +grid is evaluated, so the printed `M`/`N` are the extents spanned by the fragment +operands. The chain structure pins the real shape down: + +* **P12** (`48 mma`, 16 chains of 3): chain `c = 4·(c>>2) + (c&3)` is + `(A_{3·(c>>2)+k}, B_{2·(c&3)+k})`, `k = 0,1,2` — 4 row tiles × 4 column-pair + groups, 3 k-steps. Real shape **64×32×96**, all 16 output tiles evaluated. + (Same as enc0's P6 and enc3's P10.) +* **P21/23/…/59** (`20 mma`, 4 chains of 5): chain 0 is + `(A0,B0) (A1,B2) (A2,B4) (A3,B6) (A4,B8)`, chain 1 `(A_j, B_{2j+1})`, chains 2/3 + the same with `B10…B19`. Real shape **80×80×160** with only the 5×2 = 10 + diagonal output tiles of a 5×10 grid evaluated. +* **P61** (`80 mma`, 4 chains of 20): chain 0 is `(A_j, B_{2j})`, chain 1 + `(A_j, B_{2j+1})`, chains 2/3 with `B_{40+2j}`, `B_{40+2j+1}`, `j = 0…19`. + Real shape **320×320×640** over 4 output tiles. +* **P62** (`10 mma`, 2 chains of 5): `(A_j, B_{2j})` / `(A_j, B_{2j+1})`, + `j = 0…4`. Real shape **80×80×160** over 2 tiles. + +**Phases that read no weight-image B operand:** **P11** (`Bo = [None, None]` on all +48 mma; its `B` is a register pack of P9's D, §3/E10) and **P12** (its `B` is +packed from the `movmatrix` of P10's D, §3/E11). Every other phase loads its `B` +from `W`. + +**Weight-image extent.** The largest byte offset used anywhere is 533840 (P62's +second C seed, `ld.global.u32 [%rd900+533840]`); with the 4-byte read the image is +**533844 bytes**, 2522 distinct weight-image byte offsets (`weight_image_size`). The single largest +interior gap is `448524…530944` (the 82 KiB between P61's B block and P61's bias). + +## 3. The epilogues + +Phases 1…10 (the stem), 13…59 (the norm + 20 MLP branch pairs) and 60…62 (the +merge) are highly repetitive; each distinct body is written out once and the +repeats are tabulated. + +### E1…E9 — s7578–s7584, s7609–s7615, s7640–s7646, s7671–s7677, s7702–s7708, s7733–s7739, s7764–s7770, s7795–s7801, s7826–s7832: next-B loads + +Nine identical 7-statement epilogues. Each issues the two `v4.u32` fragments of +the *next* phase's B operand (`W + 16*laneid + {base, base+512}`): + +| epilogue | range | loads (statement / line) | offsets | next phase's W block | +|---|---|---|---|---| +| E1 | s7578–s7584 | s7582 / L12057, s7584 / L12061 | 5440, 5952 | P2 `5440..5964` | +| E2 | s7609–s7615 | s7613 / L12238, s7615 / L12242 | 1344, 1856 | P3 `1344..1868` | +| E3 | s7640–s7646 | s7644 / L12419, s7646 / L12423 | 6464, 6976 | P4 `6464..6988` | +| E4 | s7671–s7677 | s7675 / L12600, s7677 / L12604 | 2368, 2880 | P5 `2368..2892` | +| E5 | s7702–s7708 | s7706 / L12781, s7708 / L12785 | 7488, 8000 | P6 `7488..8012` | +| E6 | s7733–s7739 | s7737 / L12962, s7739 / L12966 | 3392, 3904 | P7 `3392..3916` | +| E7 | s7764–s7770 | s7768 / L13143, s7770 / L13147 | 8512, 9024 | P8 `8512..9036` | +| E8 | s7795–s7801 | s7799 / L13324, s7801 / L13328 | 4416, 4928 | P9 `4416..4940` | +| E9 | s7826–s7832 | s7830 / L13505, s7832 / L13509 | 9536, 10048 | P10 `9536..10060` | + +**Outputs:** the 8 registers of the next phase's B. Nothing else. + +### E10 — s7857–s8027: the score-phase bias tiles and the phase-11 operands + +171 statements: 24 `ld.weak.global.ca.v4.u32` (s7861/L13686 … s7907/L13778), 80 +`cvt.rn.satfinite.e4m3x2.f16x2` (s7908/L13781 … s8026/L14057), 40 `mov.b32` +(s7910/L13786 … s8027/L14059), 25 `add.s64`, plus the per-lane address pair. + +1. **Score-bias C seeds** (s7860–s7907): 24 `v4.u32` at + `W + 16*laneid + 10560 + 512*i`, `i = 0…23` → the 96 `C` operands of phase 11 + (byte block `[10560, 22348]`, 11792 bytes of f16). Phase 11's own mma confirm + the `4*(n>>1)+m` tile index: for the first A-tile the C offsets run + `10560, 10568` (s8028, s8029), `12608, 12616` (s8030, s8031), `14656, 14664`, + `16704, 16712`, `18752, 18760`, `20800, 20808` (s8038, s8039) — i.e. + `10560 + 2048*(n>>1) + 8*(n&1)` — and the second A-tile starts at `11072` + (`s8040`) = `10560 + 512`. Structurally identical to enc0's `[8384, 20672)` + and enc3's `[8448, 20236)`. +2. **B packs** (s7910–s7979, sources from s7908): the first 24 `mov.b32` + destinations = phase 11's twelve B fragments (24 b32), each a + `cvt.rn.satfinite.e4m3x2.f16x2` pair of two registers written by **phase 9's + mma** (e.g. `s7909: cvt %rs2341, %r7325`, `s7915: cvt %rs2345, %r7335`, + `s7910: mov.b32 %r8357, {%rs2341, %rs2345}` = B fragment 0). +3. **A packs** (s7982–s8027): the remaining 16 `mov.b32` destinations + (`%r8103…%r8106`, `%r8223…%r8226`, `%r8343…%r8346`, `%r8463…%r8466`) = phase + 11's four A fragments (16 b32), also from phase 9's D + (`s8017: cvt %rs2413, %r7445`, `s8021: mov.b32 %r8463, {%rs2413, %rs2414}`). + +As in enc3, **fragment 0 of phase 11's A and of its B are bit-identical** (both +packs read the same two source registers). + +**Inputs:** phase 9's 48 D registers. **Outputs:** phase 11's 16 A + 24 B +registers and its 96 C seeds. **Memory:** 24 weight loads only. + +### E11 — s8076–s11919: the 64×96 score softmax + +3844 statements, **zero memory access**; byte-for-byte the same code as enc3's E9 +(and enc0's E5) with shifted registers. Histogram: 1048 `mov.b32`, 672 +`cvt.rn.f16.f32`, 384 `cvt.rn.f16.f64`, 192 each `fma.rn.f16x2` / +`cvt.f32.f16` / `rcp.approx.ftz.f32` / `mul.f16`, 96 each `max.f16x2`/`min.f16x2`/ +`neg.f16x2`/`mul.f16x2`/`and.b32`, 48 `movmatrix`, 16 `shfl.sync.bfly`, 144 packs. + +| range | statements | what | +|---|---|---| +| s8076–s10193 | 2118 | 96 per-element exponent groups | +| s10194–s10273 | 80 | in-lane partial-sum trees (`add.f16x2`) | +| s10274–s10408 | 135 | 16 `shfl.sync.bfly.b32` (s10281/L21268 … s10402/L21572) → 8 row sums | +| s10411–s11172 | 769 | 192 `rcp.approx.ftz.f32` → 96 reciprocals | +| s11178–s11654 | 477 | 192 `mul.f16` → 96 probabilities | +| s11656–s11703 | 48 | `movmatrix.sync.trans.aligned.m8n8.b16` of **phase 10's** 48 D registers | +| s11704–s11918 | 216 | 144 packs | + +**(a) per-element exponent, s8076–s10193.** Per f16 half `x` of each of phase +11's 96 D f16x2 registers: + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +u = f16(1.375 + m*(0.92724609375 - m^2)) +E = (u_bits << 5) & 0x7FE07FE0 // first: s8102 shl.b32, s8103 and.b32 +``` + +identical to enc0's E5(a): **not** `exp`, and the two `fma.rn.f16x2` at +s8096/L14453 and s8097 are the cubic, `neg.f16x2` at s8091/L14439 the `−m`. + +**(b) row sums, s10194–s10408.** In-lane `add.f16x2` tree, then `shfl.sync.bfly` +over lane bits 0 and 1 (`%r10789 = 1`, `%r10798 = 2`, membermask `%r10800 = −1`), +then `add.f16x` of the halves and broadcast. + +**There is no row maximum in this epilogue.** Every `max.f16x2` (96, s8091 … +s10183) and `min.f16x2` belongs to the clamp of (a); the only shuffles are the 16 +butterflies above. + +**(c) reciprocity and probability, s10411–s11654.** 192 `rcp.approx.ftz.f32` +wrapped as `cvt.f32.f16 → rcp → cvt.rn.f16.f32`, then 192 `mul.f16`. + +**(d) V transpose, s11656–s11703.** Exactly 48 `movmatrix…m8n8.b16` on phase +**10**'s 48 D registers (`s11656 L23893` … `s11703 L24034`). + +**(e) packs, s11704–s11918.** 144 packs: the first 24 `mov.b32` → phase 12's 12 +B fragments (the transposed V), the rest → phase 12's 12 A fragments. + +**Inputs:** phase 11's 96 D, phase 10's 48 D, `%r10789/%r10798/%r10800`. +**Outputs:** phase 12's 48 A / 24 B registers plus the `%f476`, `%fd383`, +`%fd385`, `%f478`, `%f480` constants. **Memory:** none. + +### E12 — s11968–s12241: P·V epilogue — pack, shared staging, residual table, next B/C + +274 statements. Histogram: `mov.b32`×96, `add.f16`×80, +`cvt.rn.satfinite.e4m3x2.f16x2`×32, `ld.global.v2.u16`×20, `add.s64`×12, +`ld.weak.global.ca.v4.u32`×10, `shl.b32`×5, `add.s32`×4, `mov.u32`×4, +`st.shared.v4.u32`×4, `bar.sync`×2, `bra`×1, `ld.shared.v4.u32`×1, +`mul.wide.u32`×1, `cvt.u64.u32`×1, `and.b64`×1. + +**(a) require and shared staging, s11969–s12025.** + +``` +s11969 L24877: shl.b32 %r12002, %r9, 11 // tid.z << 11 +s11970 L24878: add.s32 %r12003, %r11752, %r12002 +s11973 L24883: add.s32 %r12005, %r12003, %r12004 // + 16*laneid +s11986 L24912: st.shared.v4.u32 [%r12005], {%r12009, %r12008, %r12007, %r12006} +``` + +32 packs of phase 12's D → 16 b32 (96 `mov.b32` in the whole epilogue; the other +80 pair the table adds) stored one `v4.u32` each at `+0`, `+512`, `+1024`, `+1536` +(s11986, s11999, s12012, s12025). + +**(b) `bar.sync 0` (s12026) and skip guard.** `s12027 L25001: @%p8 bra +$L__BB1_422` with `%p8 = (tid.z > 3)` (s20–s21) — phases 13…20 are only run for +`tid.z ≤ 3`. + +**(c) staging read-back, s12028–s12033.** `%r29518 = %r11752 + (tid.z<<9) + +(laneid<<4)` (s12028–s12032), `ld.shared.v4.u32 [%r29518]` → `%r29519 … %r29522` = +**phase 13's A operand** (one 16-byte fragment, `nA = 1`). + +**(d) next B, s12034–s12056.** 10 `v4.u32` at `W + 16*laneid + 22848 + 512*j`, +`j = 0..9` → phase 13's 20 B fragments (block `[22848, 27468)`). + +**(e) residual column table, s12062–s12081.** 20 `ld.global.v2.u16` at +`W + ((laneid<<2)&12) + {221504 + 16*i}`, `i = 0…19` → 40 f16 covering the 160 +columns of phase 13's output. + +**(f) residual add, s12082–s12241.** 80 `add.f16` — two per f16x2 — each +`table[column] + `: + +``` +s12084 L25089: add.f16 %rs3965,%rs6450,%rs3967 // %rs6450 = W+221504, %rs3967 = residual +s12083 L25085: add.f16 %rs3968,%rs6451,%rs3970 +s12085 L25092: mov.b32 %r12073, {%rs3965, %rs3968} +``` + +The 40 results `%r12073 …` are **phase 13's C operands**. The residual halves are +`%r31707`, `%r31706`, … split at s5443 ff. (§1.2). + +**Inputs:** phase 12's D, the shared staging, `W`. **Outputs:** phase 13's A +(4 regs), B (40 regs) and C (40 regs). + +### E13…E19 — s12262–s12288, s12309–s12335, s12356–s12382, s12403–s12429, s12450–s12476, s12497–s12523, s12544–s12570: next-A from shared, next-B from W + +Seven identical 27-statement epilogues (`add.s64`×11, 10 `v4.u32`, `mov.u32`×2, +`shl.b32`, `add.s32`, 1 `ld.shared.v4.u32`, `mul.wide.u32`): + +``` +s12264 L25627: add.s32 %r29525, %r29516, %r29524 // %r29516 = %r11752 + (tid.z<<9) +s12265 L25628: ld.shared.v4.u32 {…}, [%r29525+2048] +s12267 L25632: mul.wide.u32 %rd648, %r12266, 16 +s12268 L25633: add.s64 %rd649, %rd2, %rd648 +``` + +| epilogue | range | shared read offset | becomes | B offsets (10 loads) | next phase's W block | +|---|---|---|---|---|---| +| E13 | s12262–s12288 | s12265, `+2048` | P14 A | 50496 … 55104 | P14 `50496..55116` | +| E14 | s12309–s12335 | s12312, `+4096` | P15 A | 78144 … 82752 | P15 `78144..82764` | +| E15 | s12356–s12382 | s12359, `+6144` | P16 A | 105792 … 110400 | P16 `105792..110412` | +| E16 | s12403–s12429 | s12406, `+8192` | P17 A | 133440 … 138048 | P17 `133440..138060` | +| E17 | s12450–s12476 | s12453, `+10240` | P18 A | 161088 … 165696 | P18 `161088..165708` | +| E18 | s12497–s12523 | s12500, `+12288` | P19 A | 188736 … 193344 | P19 `188736..193356` | +| E19 | s12544–s12570 | s12547, `+14336` | P20 A | 216384 … 220992 | P20 `216384..221004` | + +### E20 — s12591–s13619: the RMS norm before the MLP + +1029 statements: 302 `mov.b32`, 240 `mul.f16`, 82 `add.f16`, 80 `cvt.f32.f16`, +80 `rsqrt.approx.ftz.f32`, 80 `cvt.rn.f16.f32`, 42 `add.f16x2`, 4 +`shfl.sync.bfly`, 40 packs, 20 `ld.global.v2.u16`, 10 weight `v4.u32`, 4 +`ld.global.u32`. + +| range | what | +|---|---| +| s12594–s12751 | 80 `mul.f16` — squares of phase 20's 40 D f16x2 | +| s12753–s12817 | 42 `add.f16x2` — in-lane reduction, with the 4 `shfl.sync.bfly` over lane bits 0,1 at s12795/L27521, s12801, s12810, s12816/L27575 | +| s12819–s12940 | 82 `add.f16` — `+ 2⁻¹³` (`%fd1`, s5976) broadcast into the f16x2 pairs | +| s12946–s13259 | 80 `rsqrt.approx.ftz.f32` (s12946/L27961 … s13259/L28469) | +| s13268–s13287 | 20 `ld.global.v2.u16` gain at `W + ((laneid<<2)&12) + {221824 + 16*i}` (`s13289 mul.f16 %rs4692,%rs4693,%rs6490` with `%rs6490 = W+221824`) | +| s13289–s13407 | 80 `mul.f16` — `inv · gain` | +| s13408–s13526 | 80 `mul.f16` — `x · (inv·gain)` (`s13408 mul.f16 %rs4935,%rs5217,%rs4695`) | +| s13532–s13550 | 10 weight `v4.u32` = phase 21's B (`222144 + 512*j`) | +| s13556–s13559 | 4 `ld.global.u32` at `W + ((laneid<<2)&12) + {227264,227280,227296,227312}` = phase 21's C bias | +| s13560–s13618 | 40 packs of the normalised values → phase 21's A | + +**What it computes.** The same per-**row** RMS reduction as enc3's E14, over the +**160** columns of a M=16/N=160 tile: the lane's 20 one-per-n-tile partials for +each of its two rows are tree-summed in-lane, the four `t = laneid&3` lanes are +folded with two butterfly steps, the f16x2 halves are added, then + +``` +inv = f16(rsqrt.approx(f32(f16(sumsq + 2^-13)))) +out[row,c] = x[row,c] · inv · gain[c] +``` + +There is no mean subtraction and no `1/N`. The 80 `rsqrt` results are the two row +sums re-emitted once per (row, n-tile) pair, not 80 distinct sums (the half-copies +that feed them are duplicates, e.g. `s12818`-range `add.f16 … , %rs…, %rs…` with +identical addends). `gain[c]` is per column. + +**Outputs:** phase 21's B (40 regs) and C (4 regs), 20 packed A registers, and the +normalised f16x2 registers that E21/E22 re-read. + +### E21 — s13640–s13960: clamped cubic activation + column bias + pack + +321 statements: `add.f16`×80, `mov.b32`×76, `cvt.rn.f16.f32`×32, `mul.f16x2`×24, +20 `ld.global.v2.u16`, 10 weight `v4.u32`, 8 each `neg/max/min/abs/sub/add.f16x2`, +8 packs, `mov.f32`×4. + +**(a) constants and activation, s13641–s13780.** Eight groups; each materialises +the activation constants (`s13641 L29561: mov.f32 %f1117, 0f3ED306EB`, `s13644 +%f1118, 0f3DA60DD6`, `s13647 %f1119, 0f3F000000`, `s13650 %f1120, 0f40000000`) +and then, on **phase 21's D**, + +``` +y = clamp(x, -2, +2) // s13653 neg, s13654 max, s13655 min +g = 0.5 + y*(0.412109375 - 0.0810546875*|y|) // abs, mul, sub, mul, add +out = x * g // s13661 mul.f16x2 +``` + +The same cubic ramp as enc0's E13 / enc3's E15 — **not** a sigmoid, GELU or SiLU. + +**(b) column bias, s13809–s13948.** 20 `ld.global.v2.u16` at +`W + ((laneid<<2)&12) + {232464 + 16*i}` then 80 `add.f16`, e.g. +`s13932 L30428: add.f16 %rs5416,%rs6524,%rs5418` — the second addend is a half of +phase **20**'s D (a residual). The 40 results `%r14926 … %r14956` are **phase +22's C operand**. + +**(c) pack, s13949–s13959.** 8 packs of the **activation outputs** +(`s13949 L30478: cvt.rn.satfinite.e4m3x2.f16x2 %rs5453, %r14617`) → phase 22's A +fragment. + +**(d) next B, s13785–s13803.** 10 `v4.u32` at `227328 + 512*j` → phase 22's B. + +**No stores and no `ld.global` beyond the two tables.** + +### E22 / E24 / … / E58 — s13981–s14072 and its 19 repeats: next B/C loads + pack + +92 statements, identical shape, for every even phase 22…58: + +``` +s13984 L30650: add.s64 %rd263, %rd676, 232768 +s13985 L30652: ld.weak.global.ca.v4.u32 { %r14958,…},[%rd263] // 232768 + 512*j, 10 loads +s14009 L30697: ld.global.u32 %r…, [%rd…+237888] // C bias, 4 words at +16*i +s14013 L30702: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r… // 40 packs +s14015 L30707: mov.b32 %r…, {%rs…, %rs…} // 20 b32 = 5 A fragments +``` + +The 40 pack sources (`%r28751 %r28752 %r28753 …`, `s14013 L30702: cvt %rs5461, +%r28752`) are the **normalised values** E20 produced with the second of its +multi-sets, i.e. phase 23's A operand is the *same* normed tile phase 21's A was +built from — phases 21 and 23 are two parallel GEMMs off one normed tile, each +with its own weight block and bias. The 4 C words are +`W + ((laneid<<2)&12) + {bias_base + 16*i}` (`s13556 L29274: +ld.global.u32 %r14283, [%rd669+227264]`, `s13557`/`s13558`/`s13559`) and each is +used in **both halves** of the *next odd* phase's mma C operand: for the P23 bias +loaded by E22, `s14073 C={%r15048,%r15048}` with `[%r15048=W+237888]`, +`s14074 C={%r15058,%r15058}` with `W+237904`. + +| epilogue | range | next-B block | next-C bytes | +|---|---|---|---| +| E22 | s13981–s14072 | 232768..237388 | 237888..237936 | +| E24 | s14285–s14376 | 243072..247692 | 248192..248240 | +| E26 | s14589–s14680 | 253376..257996 | 258496..258544 | +| E28 | s14893–s14984 | 263680..268300 | 268800..268848 | +| E30 | s15197–s15288 | 273984..278604 | 279104..279152 | +| E32 | s15501–s15592 | 284288..288908 | 289408..289456 | +| E34 | s15805–s15896 | 294592..299212 | 299712..299760 | +| E36 | s16109–s16200 | 304896..309516 | 310016..310064 | +| E38 | s16413–s16504 | 315200..319820 | 320320..320368 | +| E40 | s16717–s16808 | 325504..330124 | 330624..330672 | +| E42 | s17021–s17112 | 335808..340428 | 340928..340976 | +| E44 | s17325–s17416 | 346112..350732 | 351232..351280 | +| E46 | s17629–s17720 | 356416..361036 | 361536..361584 | +| E48 | s17933–s18024 | 366720..371340 | 371840..371888 | +| E50 | s18237–s18328 | 377024..381644 | 382144..382192 | +| E52 | s18541–s18632 | 387328..391948 | 392448..392496 | +| E54 | s18845–s18936 | 397632..402252 | 402752..402800 | +| E56 | s19149–s19240 | 407936..412556 | 413056..413104 | +| E58 | s19453–s19544 | 418240..422860 | 423360..423408 | + +### E23 / E25 / … / E59 — s14093–s14264 and its 18 repeats: clamped cubic activation + pack + +172 statements; identical op mix to E21 minus the table loads and the `mov.f32` +block (36 `mov.b32`, 32 `cvt.rn.f16.f32`, 24 `mul.f16x2`, 8 each +`neg/max/min/abs/sub/add.f16x2`, 10 weight `v4.u32`, 8 packs): + +``` +s14094 L30986: cvt.rn.f16.f32 low, %f1117 +s14102 L31009: neg.f16x2 %r15244,%r15243 +s14109 L31037: add.f16x2 %r15250,%r15243,%r15249 +s14234 L31471: ld.weak.global.ca.v4.u32 { …},[%rd…] // next B, 10 loads +s14253 L31510: cvt.rn.satfinite.e4m3x2.f16x2 … // 8 packs of activation outputs +``` + +Same function as E21(a) on the odd phase's D, 8 packs of the activation *outputs* +→ the next even phase's A, and 10 weight loads → its B. **No column bias, no +`ld.global`.** The 18 repeats are at s14093, s14377, s14681, s14985, s15289, +s15593, s15897, s16201, s16505, s16809, s17113, s17417, s17721, s18025, s18329, +s18637, s18937, s19241, s19545 (phases 23…59 odd). + +#### Shape of the attention + MLP region, E12–E60 + +``` +P11 A = pack(P9.D) B = pack(P9.D) C = bias@10560+512i → scores 64×96 + E11: cubic-exponent softmax (no row max), 48 movmatrix(P10.D) + packs +P12 A = pack(scores) B = pack(transpose(P10.D)) C = 0 → 64×32 + E12: pack → shared slot, read back as P13 A; table@221504 + residual → P13 C +P13 A = shared, B = W@22848, C = table+residual → D13 + E13: shared slot +2048 → P14 A; load P14 B +P14…P19 the same for the shared slots +4096 …, +14336 +P20 A = shared, B = W@216384, C = D19 → D20 (16×160) + E20: row-RMS norm over 160 columns (+2^-13, rsqrt, gain@221824), pack → P21 A +P21 A = normed tile, B = W@222144, C = bias@227264 → D21 (banded 80×80×160) + E21: cubic activation(D21); table@232464 + D20 → P22 C; pack → P22 A +P22 A = pack(activation), B = W@232768, C = D20+table → D22 + E22: pack of the *normed* tile → P23 A; load P23 B and C +P23 A = normed tile, B = W@237952, C = bias@237888 → D23 + … the P21/P22 pair then repeats 19 more times (P23/P24 … P59/P60). +P60 A = pack(activation P59), B = W@423424, C = D58 → D60 (16×160) + E60: arena scatter, shared staging, next B/C +P61 A = 20 shared slots, B = W@428544, C = bias@530944 → 4×20 k-steps + E61: pack + scatter to param+56, next B/C +P62 A = pack(E61), B = W@531264, C = bias@533824 → D62 + E62: the final epilogue +``` + +### E60 — s19757–s21137: pack → plane-arena scatter → shared staging → next B/C + +1381 statements. Histogram: `add.s32`×218, `or.b32`×129, `shl.b32`×99, +`and.b32`×80, `ld.shared.u32`×80, `mul.wide.u16`×69, `add.s64`×66, `shr.u32`×51, +`setp.lt.s32`×44, `bra`×41, `$label`×41, `cvt.rn.satfinite.e4m3x2.f16x2`×40, +`selp.b32`×40, `ld.weak.global.ca.v4.u32`×40, `mov.b32`×20, `st.shared.u32`×20, +`st.global.u32`×20, `bar.sync`×2, `ld.global.u32`×4. + +**(a) packs, s19757–s19816.** 40 `cvt.rn.satfinite.e4m3x2.f16x2` + 20 `mov.b32` +→ `%r371 … %r390` = phase 60's 16×160 output as 20 b32 = 40 e4m3 per lane. + +**(b) plane-arena scatter, s19817–s20029.** `%rd5 = cvta(ld.param.u64 [%rd1+-32])` +(s19817–s19818; `%rd1 = param_0+80` ⇒ **`param_0+48`**), lane decomposition +`s20035 shr %r424, laneid, 2` (`g`), `s20036 and %r425, laneid, 3` (`t`), and 20 +guarded `st.global.u32` (`s19843 L50422: st.global.u32 [%rd810], %r371` … +`s20029 L50646: … %r390`), each preceded by a +`setp.lt.s32 %p, idx, 0` + `bra` guard. The index is built from +`(%r1 + ((g+8j)&7))`, `((tid.z<<1) + ((g+8j)>>3))` and `(%r425 | 4)` in the same +way as enc3's E46(b) (§6/U4). + +**(c) shared staging, s20033–s20215.** `bar.sync 0`, then 20 `st.shared.u32` at +`%r29635 = %r11752 + (idx<<2)` with +`idx = t | ((laneid&28) | (y<<5))`, `y = (tid.z<<1) + (laneid>>5)` +(`s20051 L50672: st.shared.u32 [%r29635], %r371`), then the `+512*j` variants. + +**(d) staging read-back, s20222–s21030.** `bar.sync 0` (s20220), then 80 +`ld.shared.u32` at `%r11752 + (idx2<<2)` with +`idx2 = ((laneid<<1)&24) | ((laneid<<2)&0xFFFFFFC0) | (laneid&3)` +(`s20234–s20241`) plus byte offsets `{0, 1024, …, 7168}` and the `+16` variants +(`s20242 L50905: ld.shared.u32 …`). These 80 values are **phase 61's 20 A +fragments**. `ld.param.v2.u32 [%rd940+-80]` at s20222 re-reads `param_0+0`. + +**(e) next B/C, s21039–s21137.** Inside the loop `$L__BB1_406` (s21041), +`s21039 add.s64 %rd7, %rd947, 428544`, `s21042: mul.lo.s32 %r31250, %r31708, 640` +then 40 `v4.u32` at `W + 16*laneid + 428544 + 640*%r31708 + 512*j`, `j = 0…39` +(`s21048–s21126`) = phase 61's 80 B fragments, and 4 `ld.global.u32` at +`W + ((laneid<<2)&12) + {530944, 530960, 530976, 530992}` (s21134–s21137) = +phase 61's C bias. + +**Outputs:** `%r371…%r390` (read again by (c)), phase 61's A/B/C. +The shared arena is re-used four times in this epilogue — `%r11752` appears as the +base of the E60 stores and of the P61 read-back. + +### E61 — s21218–s21334: pack → surface scatter → next B/C + +117 statements: 8 packs + 2 `mov.b32` (s21218–s21227), 4 guarded stores to +**`param_0+56`** (s21257 `st.global.v2.u16`, s21267 `st.global.u32`, +s21298 `st.global.u32`, s21306 `st.global.v2.u16`), 5 `bra`, then 5 weight +`v4.u32` (s21319–s21327) and 2 `ld.global.u32` (s21333–s21334). + +``` +s21253 L52499: setp.lt.s32 %p381, %r545, 0 +s21254 L52500: @%p381 bra $L__BB1_408 +s21255 L52502: mul.wide.s32 %rd898, %r545, 4 +s21257 L52504: st.global.v2.u16 [%rd899], {%rs6698, %rs6699} +``` + +The destination is `param+56` (`%rd6 = cvta(%rd849)`, `%rd849 = ld.param.u64 +[%rd945+-24]`, s21037–s21038), **not** the plane arena; the extents are +`param_0+0`, halved (`s20223 shr %r451, %r29720, 1` = `ey>>1`, `s20224 shr %r452, +%r29719, 1` = `ex>>1`, `s20225 shl %r453, %r452, 3` = the row stride). The index +bases use `%r536 = %r1>>1` (s21036) and `%r535 = %r3>>1` (s21033). + +Then phase 62's B (5 `v4.u32` at `531264 + 512*j`) and C (2 `ld.global.u32` at +`533824`, `533840`). + +### E62 — s21345–s21667: the final epilogue + +323 statements: 4 `st.shared.u32` (s21357–s21374), 2 `bar.sync`, 5 `ld.shared.u32` +(s21414–s21422), `mul.ftz.f32`/`ex2.approx`/`add.ftz.f32`/`div.approx`×12, +12 `fma.rn.f16x2`, 4 `shfl.sync.down.b32`, 9 `tex.base.2d.v4.f16.s32` +(s21526–s21585), 3 `sust.b.2d.v4.b16.zero` (s21649, s21650, s21665). + +**(a) shared staging, s21345–s21374.** + +``` +s21348 L52679: and.b32 %r557, %r31392, 3 // t +s21350 L52681: shl.b32 %r558, %r31608, 4 // %r31608 = tid.z +s21351 L52682: add.s32 %r31395, %r556, %r558 // g + (tid.z<<4) +s21354 L52685: mad.lo.s32 %r31398, %r31397, 6, %r557 +s21357 L52688: st.shared.u32 [%r559], %r31372 +``` + +Phase 62's D (`%r31372/%r31382` and `%r31392`-group counterparts) is written to +`%r31615 + 4*(6*index + t)` with a `%r560 > 5` guard on the second word. + +**(b) row max and softmax, s21387–s21613.** After `bar.sync 0` (s21387), +`%r31565 = smem + 4*(6*%r562 + 48*%r563)` (s21410–s21413) and +`s21414–s21422` read a **6-element row** (`ld.shared.u32 [%r31565] … [+20]`); then + +``` +max.f16x2 / max.f16 over the row // row maximum +sub.f16x2 x - rowmax // e.g. s21502-region +mul.ftz.f32 by log2(e), ex2.approx.ftz.f32 // 2^((x-max)*log2e) +div.approx.ftz.f32 1.0(rowsum) with %f1152 = 0f3F800000 (s21429) +mul.f16x2 p = e / rowsum +``` + +**This epilogue has a real row maximum** (unlike E11), and a true `2^u` `ex2` +rather than the cubic mantissa trick. + +**(c) texture gather, s21421–s21590.** One texture (`load.param.u64 [%rd943+8]` at +s21524, copied into `%rd916 … %rd932`, s21525–s21572) with 9 +`tex.base.2d.v4.f16.s32` reads forming a 3×3 stencil; the 8 neighbour coordinates +are clamped by `selp` chains with `1` as the out-of-range sentinel (the same +pattern as enc3's E48(c)). Each texel is weighted by one of the five softmax +values with `fma.rn.f16x2` (`s21530 L52979`, `s21547 L53007`, …, +`s21580 L53074`) and one extra texel is folded in with `fma.rn.f16`. + +**(d) second sigmoid, difference, cross-lane sum, s21591–s21648.** Three +`mul.f16` + `sub.f16` products and differences, `%f1148 = 0.25` (s21606), then the +`shfl.sync.down` cascade: delta `1` (`%r31545`, s21424) and `8` (`%r31553`, +s21417), membermask `%r31555 = -1` (s21510), clamp operand `(WARP_SZ<<8)-8192 | 31` +(s21619, s21625, s21632, s21641), each followed by `add.f16x2` / `add.f16`. + +**(e) surface stores, s21646–s21667.** + +``` +s21646 L53255: ld.param.u64 %rd936, [%rd943+40] +s21647 L53256: ld.param.u64 %rd938, [%rd943+48] +s21649 L53259: sust.b.2d.v4.b16.zero [%rd934, {%r31559,%r565}], {%rs6803,%rs6806,%rs6809,%rs6840} +s21650 L53262: sust.b.2d.v4.b16.zero [%rd936, {%r31559,%r565}], {%rs6794,%rs6797,%rs6800,%rs6841} +s21665 L53280: sust.b.2d.v4.b16.zero [%rd938, {%r31587,%r31588}], {%rs6842,%rs6843,%rs6827,%rs6845} +``` + +Three 4-channel b16 surface writes. The handles are `param_0+32` (`%rd934`, read +at s21421), `+40` and `+48`; the texel source is the texture at `param_0+8` +(s21524). The third store is guarded (`s21655 … bra`) and stores `0` in its +fourth channel as in enc3. + +**Inputs:** phase 62's D, the shared staging of (a), `param+0/+8/+32/+40/+48`. +**Outputs:** none (the kernel `ret`s at s21667 / L53284). + +## 4. The plane-arena and surface writes + +`param_0+48` is reached once (`s19817 ld.param.u64 %rd808, [%rd1+-32]` with +`%rd1 = param_0+80` at s4) and is never the base of an `ld.*` in this entry. The +complete set of global writes in the 21667-statement entry: + +* **E60, 20 × `st.global.u32 [%rd5 + 4*idx], v`** — s19843, s19852, s19885, s19893, + s19902, s19910, s19919, s19927, s19936, s19944, s19953, s19961, s19970, s19978, + s19987, s19995, s20004, s20012, s20021, s20029 (§3/E60(b)). Value: phase 60's + requantised 16×160 output, 20 b32 per lane. +* **E61, 4 stores to `param_0+56`** — s21257 (`v2.u16`), s21267 (`u32`), + s21298 (`u32`), s21306 (`v2.u16`). +* **E62, 3 `sust.b.2d.v4.b16.zero`** — s21649, s21650, s21665. + +Nothing else writes to global memory. + +## 5. Uncharacterised + +**U1. The identity of the 11792-byte score bias (P11's C operand).** Phase 11 +adds the f16 table `[10560, 22348]` indexed as +`byte = 10560 + 512*(4*(n>>1) + m) + 16*laneid + 8*(n&1)`. Whether it is a +relative position bias, a learned score bias or a per-lane constant cannot be +decided from the PTX. *Missing:* the weight image's layout description (the +`_prep` permutation). + +**U2. The identity of the per-column tables.** `W+221504` (E12's C seed add), +`W+221824` (E20's norm gain), `W+232464` (E21's post-activation add) and +`W+227264`/`227264+65536`… (the odd phases' GEMM bias) all use the +`W + ((laneid<<2)&12) + off` pattern. Their role is computable (§3) but their +model names are not. + +**U3. The shared-arena layout.** The arena (16384 bytes) is written by the +prologue (s7494–s7504), E12 (s11986–s12025) and E60 (s20051–s20215), and read by +P1–P10 (s7513–s7542, at `%r11752 + 16*laneid + 512*k` with **no** `tid.z` term), +P13–P20 (s12033, s12265, …, s12547, at `%r11752 + (tid.z<<9) + 16*laneid + 2048*j`) +and P61 (s20242–s21030). The prologue's store side and the E60 store side add +`tid.z` terms that the P1–P10 read side does not, so the mapping cannot be +reconstructed from the PTX alone. *Missing:* the launch's `%tid.z`/`ctaid` +ranges, or a memory dump. + +**U4. E60's / E61's index algebra.** E60(b)'s arena stores, E60(c)'s shared +stores and E61's `param+56` stores each form index bases from +`(laneid&28) | (y<<5)` and `((g+8)<<2)&28 | (y2<<5)` plus `+512*j`, with +`y = (tid.z<<1) + (laneid>>5)` and `y2 = (tid.z<<1) + ((g+8)>>3)`, while E60(d)'s +read side uses `16*g + t` and `16*g + t + 128`. I could not prove the +store↔load permutation, nor whether the `%r31708` loop (s21041, `+128` at s21308) +runs once or twice per `tid.z` (the guard `%r31708 > 159` at s20227/s21046 is +checked before the first body, exactly as in enc3). *Missing:* a plane-arena dump. + +**U5. The MLP block's shape.** §3 establishes, from the pack sources and each +phase's C operand, that the MLP region is: one normed tile feeding every *odd* +phase (P21, P23, …, P59) as its `A`, each odd phase's activation feeding its +*paired* even phase as `A`, and the even phases' `C` chaining +(`D22 = … + D20 + table@232464`, `D24 = … + D22`, …, verified from each even +phase's C operands tracing to the previous even phase's mma). Only the **first** +even phase adds the column table `@232464` to the residual +(`s13932 add.f16 %rs5416,%rs6524,%rs5418`); every later even phase's `C` is the +previous even phase's `D` alone. Whether the 20 pairs are one wide MLP, a stack +of residual blocks, or something else is a model-level question the PTX cannot +answer. *Missing:* the model source. + +**U6. The stem's shift structure.** Phases 1…10 read the same 30 shared A +fragments in five shift groups (P1/P2 at `+0/512/…`, P3/P4 at `+512/…`, P5/P6 at +`+1024/…`, P7/P8 at `+1536/…`, P9/P10 at `+2048/…`, s7513–s7542) and accumulate +in two chains (`P1→P3→P5→P7→P9` and `P2→P4→P6→P8→P10`; each phase's C operands name +the previous one's D, e.g. `s7616 C={%r5574,%r5575}` = P1's D). Whether that is a +2×2 / 5-tap stencil is a property of the high-level model. *Missing:* the model +source. (enc3 has four shift groups and eight phases, so the tap count is a +per-stage constant.) + +**U7. The meaning of the prologue residual vector.** §1.2 tracks the f16 halves +`%rs…` back through `cvt.rn.f16x2.e4m3x2 %r31707, %rs128` (s5439) to the input +plane at `param_0+8` (s22–s23). What that plane holds is not determinable from +the PTX. + +**U8. The logical meaning of E62's final expression.** The tail computes +`out = (acc − sigmoid(acc)) * 0.25` on three channels gathered by texture from a +3×3 stencil. The arithmetic is exact in §3/E62(d); what model term it corresponds +to is not derivable. (Same gap as enc0 §6/U6.) + +**U9. The 82 KiB hole in the weight image.** Between P61's B block +(`428544..448524`) and P61's bias (`530944`) there are 82420 bytes that no phase +in this entry reads. Whether that region is padding, is unused by this stage, or +belongs to another kernel's parameters cannot be told from this entry. +*Missing:* the `_prep` code that builds the image. + +## 6. Quick acceptance index + +| requirement | where | +|---|---| +| every phase's M/N/K with the arithmetic checked | §2 (rows flagged **N** are banded; the real shapes are derived there) | +| weight image extent | §2 (533844 bytes, max offset 533840) | +| phases that read no weight operand | §2 (P11, P12) | +| score epilogue: row max? | **none** — §3/E11 (16 `shfl.sync.bfly`, no maximum) | +| score bias operand | §3/E10 (24 `v4.u32` at `W+10560+512*i`, indexed `4*(n>>1)+m`) | +| attention Q/K/V | §3/E10 (P11 A and B both from P9's D), §3/E11(d) (P10's D transposed) | +| the norm | §3/E20 (row RMS over 160 columns, `+2^-13`, `rsqrt.approx`, gain) | +| the activations | §3/E21, §3/E23 (clamped cubic ramp, 8 groups per phase) | +| patch merge | §3/E60 (arena + shared staging), §3/E61 (`param+56`), §3/E62 (textures + surfaces) | +| per-launch plane-arena writes | §4 | diff --git a/kernels/rr/rrswin_enc5.hip b/kernels/rr/rrswin_enc5.hip new file mode 100644 index 0000000..b06514a --- /dev/null +++ b/kernels/rr/rrswin_enc5.hip @@ -0,0 +1,860 @@ +// Native replacement for the Ray Reconstruction denoiser's last Swin encoder, +// cuda_dldn_engine_swin_enc5_kernel (nvngx_dlssd.dll 310.7). +// +// --------------------------------------------------------------------------- +// STATE: the mirror-cut frame is in place and builds/serves. Phases 1-12 are +// implemented -- the block's 96x64 input GEMM (two chains of five k-steps) and +// the self-attention (the 64x96 score and P*V) -- and each is bit-exact against +// the debug oracle; see "Ground truth" below. Phases 13-61 are not implemented +// yet: the eight 16x160 projections, the RMS norm, the twenty banded MLP GEMMs, +// their clamped-cubic activation and the plane-arena scatter, so the layer's +// result is not yet the reference's. +// +// The kernel is 8x8 token patches: grid (5,3,1) x block (32,1,8) -- one warp per +// %tid.z group, eight warps per block -- 15 blocks, parameter block 144 bytes. +// The PTX this file replaces is ~/.cache/d4r-rr-corpus/0018-PREPASS_ENTRYPOINT_NAME.ptx, +// entry lines 11883-50752 (kernels/rr/rrswin_enc5_epilogues.md). +// +// kernels/tex/make_ptx.py's recipe (kernels/rr/swin_enc5_recipe.py) keeps +// NVIDIA's input staging (lines 1-11882) and the whole surface epilogue (from +// line 50756) and replaces the 1306 mma of the 61 phases with the call below. +// +// Linked into ZLUDA's compile of that PTX (D4R_ZLUDA_EXTRA_BC), so tex_common.h's +// helpers and ZLUDA's own device functions are available. Compiled with -nogpuinc, +// so only plain clang builtins and attributes are used. +#include "../tex/tex_common.h" + +// --------------------------------------------------------------------------- +// Parameter block. Fields are addressed by their byte offset in the PTX, so the +// raw image is kept and read through a typed accessor. +struct DldnSwinEnc5Params +{ + uint8_t raw[144]; +}; +static_assert(sizeof(DldnSwinEnc5Params) == 144, "parameter block"); + +// the payload's offset into the plane arena, shared with the oracle's splice +// (kernels/rr/swin_enc5_recipe.py reads the same environment variable) +#ifndef D4R_RRSWIN_DEBUG_BASE +#define D4R_RRSWIN_DEBUG_BASE 4000000 +#endif + +enum : int +{ + kOutPlane = 48, // plane arena the encoder writes and the debug store uses (arg048) + kWeights = 40, // NVIDIA's prepared weight image (arg040), read-only + kPlaneArg = 48, // plane arena pointer, as the recipe's debug splice reads it + kDebugBase = D4R_RRSWIN_DEBUG_BASE, // bytes into the arena the kernel never writes + kDebugSlotFloor = 8192, // the per-block debug slot floor: 32 lanes x 64 registers x 4 bytes +}; + + +#define DEVF __attribute__((device)) static inline +typedef uint32_t lds_u32 __attribute__((address_space(3))); +typedef uint8_t lds_u8 __attribute__((address_space(3))); + +// --------------------------------------------------------------------------- +// The weight image (arg040, 431124 bytes) of phases 1-10 lives in four %tid.z +// slots of 27648 bytes each; every later phase reads the image from its base. +// Within a slot the block's input GEMM is two chains of five k-steps: +// +// chain A (columns 0..31) weight base 320 + 1024*k +// chain B (columns 32..63) weight base 5440 + 1024*k +// +// Each k-step is one m16n8k32 mma per (m-tile, n-tile), so a step reads two +// 512-byte tiles: 320 and 832 for chain A's k=0, 1344 and 1856 for its k=1, and +// so on. Chain A's k=0 is phase 1, its k=1 is phase 3 (which accumulates phase +// 1's result as its C operand), and chain B's k=0 is phase 2, its k=1 phase 4. + +#define WIN_BASE_A 320 +#define WIN_BASE_B 5440 +#define WIN_KSTEP 1024 // bytes between consecutive k-slices of one chain +#define WIN_SLOTS 27648 // bytes of weight image per %tid.z in phases 1-10 + +// phase 11's C operand, the 64x96 relative-position bias, at the slot base +#define WIN_BIAS_SCORE 10560 +// one k-step's 32 x 32 e4m3 V block, the shared window phase 12 needs per %tid.z +#define WIN_V_BYTES 1024 + +// e4m3 code -> f32, exact. The mma's e4m3 operands reach the FMA path through +// ZLUDA's exact e4m3 -> f16 widening, so this decode is the same value. +DEVF float e4m3_to_f32(uint32_t code) +{ + const uint32_t mag = code & 0x7fu; + const uint32_t bits = mag >= 8u + ? ((((mag >> 3) + 120u) << 23) | ((mag & 7u) << 20)) + : __builtin_bit_cast(uint32_t, (float)mag * 0x1p-9f); + return __builtin_bit_cast(float, bits | ((code & 0x80u) << 24)); +} + +// byte j of a lane's 16-byte weight tile holds (k, n) at +// addr(n, k) = base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) +// + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// (VERIFIED on enc0 against the debug oracle for all 1024 (n, k) pairs of a +// tile; the 64*(n&7) term is what keeps columns 16..31 from silently reading as +// zero, and the whole 32x32 tile is a bijection onto base + [0,1024).) +DEVF uint32_t waddr(int base, int k, int n) +{ + return (uint32_t)base + 512u * (uint32_t)(n >> 4) + 64u * (uint32_t)(n & 7) + + 16u * (uint32_t)((k >> 1) & 3) + 8u * (uint32_t)((n >> 3) & 1) + + 4u * (uint32_t)((k >> 3) & 1) + 2u * (uint32_t)((k >> 4) & 1) + + (uint32_t)(k & 1); +} + +// warp butterfly over the four lanes that hold a row's 32 k values (laneid ^ 1 +// and laneid ^ 2): the two shfl.sync.bfly steps the PTX's operand staging does. +DEVF uint32_t bfly1_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0xB1, 0xf, 0xf, false); +} + +DEVF uint32_t bfly2_bits(uint32_t v) +{ + return (uint32_t)__builtin_amdgcn_update_dpp(0, (int)v, 0x4E, 0xf, 0xf, false); +} + +// the low f16 of a packed pair (column 2t) +DEVF half_t half_lo(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)pair); +} + +// the high f16 of a packed pair (column 2t+1) +DEVF half_t half_hi(uint32_t pair) +{ + return __builtin_bit_cast(half_t, (uint16_t)(pair >> 16)); +} + +// f16 bits -> f32 +DEVF float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} + +DEVF uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) + | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// --------------------------------------------------------------------------- +// The block's input GEMM: 96 rows (six m-tiles of 16) x 32 columns, K = 160 as +// five k-steps of 32 that each round to f16 before the next one accumulates -- +// which is exactly what the mma chain does, since its C operand is the previous +// step's D pair. +// +// A lane's A registers hold, for each m-tile and each of its two rows, the eight +// e4m3 values of k = 2t + (j&1) + 16*((j>>1)&1) (byte j = 0..3) and of k + 8; the +// four lanes that differ in t hold the four disjoint eighths of the 32 k's, so two +// butterfly steps broadcast the other three eighths in. The B operand is read from +// the weight image (waddr) for the lane's own two columns of each n-tile. The dot +// product runs in f32 and is rounded to f16 once, which is what the translated mma +// does: e4m3 x e4m3 products are exact and 32 of them sum exactly in f32. +// +// The thirty A fragments are the ones NVIDIA's prologue staged in shared memory +// and the cut reads back into registers immediately before the first mma (PTX +// lines 11835-11864: `ld.shared.v4.u32 {…}, [%r11624 + 512*i]`, i = 0..29, with +// `%r11624 = smem + laneid*16`). Fragment 5*mi + k is m-tile mi's k-slice, so +// `as` is the lane's slot as u32 and fragment i starts 128 words in. +// +// d is [m-tile][row half][n-tile], each entry the packed f16 pair for columns 2t, 2t+1. +DEVF void win_zero(uint32_t d[6][2][4]) +{ +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { +#pragma unroll + for (int row = 0; row < 2; ++row) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + d[mi][row][nt] = 0; + } + } + } +} + +// one k-step: d <- round_f16(A[ks] * W[base + 1024*ks] + d) +DEVF void win_step(const uint8_t* w, int base, int ks, const lds_u32* as, int t, + uint32_t d[6][2][4], uint32_t* dbg) +{ + const int wb = base + WIN_KSTEP * ks; +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + float bv[2][32]; +#pragma unroll + for (int c = 0; c < 2; ++c) { + const int n = 8 * nt + 2 * t + c; +#pragma unroll + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(wb, k, n)]); + } + } +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { + const uint32_t* q = as + 128u * (uint32_t)(5 * mi + ks); +#pragma unroll + for (int reg = 0; reg < 2; ++reg) { +#pragma unroll + for (int row = 0; row < 2; ++row) { + // the register's value on this lane and on lanes t^1, t^2, t^3 + uint32_t p[4]; + p[0] = q[2 * reg + row]; + p[1] = bfly1_bits(p[0]); + p[2] = bfly2_bits(p[0]); + p[3] = bfly1_bits(p[2]); + // f64 accumulators: the mma's dot product is the correctly + // rounded sum of the 32 exact e4m3 products, and an f32 + // accumulator would round the partial sums in whatever + // order the compiler picks (measured: ~8% of the outputs + // one ulp off the reference). + double a0 = 0.0, a1 = 0.0; +#pragma unroll + for (int m = 0; m < 4; ++m) { + const int kk = 2 * (t ^ m); +#pragma unroll + for (int j = 0; j < 4; ++j) { + const int k = 8 * reg + kk + (j & 1) + 16 * ((j >> 1) & 1); + const double av = e4m3_to_f32((p[m] >> (8 * j)) & 0xffu); + a0 += av * (double)bv[0][k]; + a1 += av * (double)bv[1][k]; + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 16 + // this body's own arithmetic, for the oracle comparison + if (dbg != nullptr && ks == 0 && mi == 0) { + const int s16 = (row ? 4 : 0) + nt; + dbg[s16] = __builtin_bit_cast(uint32_t, (float)a0); + dbg[8 + s16] = (uint32_t)__builtin_bit_cast(uint16_t, (half_t)(float)a0); + } +#endif + // the mma's f32 accumulator plus the C operand, rounded once + // to f32 and then to f16 + const uint32_t prev = d[mi][row][nt]; + const float f0 = (float)(a0 + (double)h2f(prev)); + const float f1 = (float)(a1 + (double)h2f(prev >> 16)); + d[mi][row][nt] = pair_of((half_t)f0, (half_t)f1); + } + } + } + } +} + +// the whole chain: five k-steps into a zeroed accumulator +DEVF void win_chain(const uint8_t* w, int base, const lds_u32* as, int t, + uint32_t d[6][2][4]) +{ + win_zero(d); +#pragma unroll + for (int ks = 0; ks < 5; ++ks) { + win_step(w, base, ks, as, t, d, nullptr); + } +} + +// --------------------------------------------------------------------------- +// The attention. Phase 11 is the 64x96 score Q*K^T: its A operand is the query +// rows 0..63 of D9 and its B operand the key rows 0..95 of the *same* D9, so +// every lane owns both rows of each dot and no lane exchange is needed -- only +// the butterfly that brings the other three lanes' eighths of the 32 k's in. +// +// E10 packs both operands identically (PTX s7908-s8027): A quad mi = registers +// written {D9[m0,nt0,g], D9[m0,nt0,g+8]} {…nt2…} {…nt1…} {…nt3…} and B pair +// nt = the same four words of D9 rows 16*(nt>>1)+g and +8. Read back in the +// mma's own fragment order that is +// A reg o, byte j -> row 16*mi + g + 8*(o&1), k = 2t + (j&1) + 16*((j>>1)&1) + 8*(o>>1) +// B pair nt, reg b, byte j -> key row 16*(nt>>1) + g + 8*(nt&1), same k +// and the mma pairs A's register o with B's register o>>1, so the four n-tiles +// of an 8-column group share the two k-steps o>>1 = 0 and 1. `row_words` below +// builds one row's two words in exactly that order (word 0 = k-slice 0, word 1 +// = k-slice 1), so a row is four `cvt.rn.satfinite.e4m3x2.f16x2` and two packs. + +// the f16 the PTX's literals carry: 0f3C8CCB50, 0dBFE1CC0000000000, 0f3F6D6000, 0f3FB00000 +DEVF half_t hf16(uint16_t bits) +{ + return __builtin_bit_cast(half_t, bits); +} + +DEVF hv2 hv2_of(uint32_t p) +{ + return __builtin_bit_cast(hv2, p); +} + +DEVF uint32_t u32_of(hv2 v) +{ + return __builtin_bit_cast(uint32_t, v); +} + +// ZLUDA's own rcp.approx.ftz.f32 helper: calling it is what makes the reciprocal bit-exact. +extern "C" __attribute__((device)) float __zluda_ptx_impl_rcp_approx_f32(float); + +// the f16 at (row, col) of a 96x32 block of packed pairs, col = 8*n-tile + 2t + c +DEVF half_t dcell(const uint32_t d[6][2][4], int row, int col) +{ + const uint32_t p = d[row >> 4][(row >> 3) & 1][col >> 3]; + return (col & 1) ? half_hi(p) : half_lo(p); +} + +// the lane's two e4m3-packed words for row r: word 0 is k-slice 0 (columns +// 2t, 2t+1 and 16+2t, 17+2t), word 1 is k-slice 1 (columns 8+2t … and 24+2t …) +DEVF void row_words(const uint32_t d[6][2][4], int r, uint32_t w[2]) +{ + w[0] = e4m3x2(pair_of(dcell(d, r, 0), dcell(d, r, 1))) + | (e4m3x2(pair_of(dcell(d, r, 16), dcell(d, r, 17))) << 16); + w[1] = e4m3x2(pair_of(dcell(d, r, 8), dcell(d, r, 9))) + | (e4m3x2(pair_of(dcell(d, r, 24), dcell(d, r, 25))) << 16); +} + +// out[i][m]: word i as lane t^m holds it, which is what the mma pairs across the group +DEVF void bfly2x4(const uint32_t w[2], uint32_t out[2][4]) +{ +#pragma unroll + for (int i = 0; i < 2; ++i) { + out[i][0] = w[i]; + out[i][1] = bfly1_bits(w[i]); + out[i][2] = bfly2_bits(w[i]); + out[i][3] = bfly1_bits(out[i][2]); + } +} + +// E11(a), one element: the scale, the clamp, the two clamped-cubic fma pairs and the +// trick that moves the mantissa into the exponent field ((u << 5) & 0x7FE07FE0 over +// the pair). The constants are the same five the PTX materialises at s8077-s8097. +DEVF uint32_t expval_pair(uint32_t score) +{ + hv2 m = hv2_of(score) * __builtin_bit_cast(hv2, pair_of(hf16(0x2466), hf16(0x2466))); + m = __builtin_elementwise_max(m, __builtin_bit_cast(hv2, pair_of(hf16(0xb873), hf16(0xb873)))); + m = __builtin_elementwise_min(m, __builtin_bit_cast(hv2, pair_of(hf16(0x3873), hf16(0x3873)))); + const hv2 t = __builtin_elementwise_fma(m, -m, + __builtin_bit_cast(hv2, pair_of(hf16(0x3b6b), hf16(0x3b6b)))); + const uint32_t u = u32_of(__builtin_elementwise_fma(m, t, + __builtin_bit_cast(hv2, pair_of(hf16(0x3d80), hf16(0x3d80))))); + return (u << 5) & 0x7fe07fe0u; +} + +// E11(a)-(e), one row: the twelve exponent pairs, the in-lane sum tree +// ((e0+e1)+(e2+e3))+(e4+e5) over the even pairs and the same over the odd ones, +// the two butterfly steps that finish the row's 96 columns, the two halves' +// add, the reciprocal and the twelve products. d11 is [m-tile][row half][n-tile]. +DEVF void row_probs(const uint32_t d11[4][2][12], int mi, int rh, uint32_t prob[12]) +{ + hv2 ev[6], eo[6]; +#pragma unroll + for (int i = 0; i < 6; ++i) { + ev[i] = hv2_of(expval_pair(d11[mi][rh][2 * i])); + eo[i] = hv2_of(expval_pair(d11[mi][rh][2 * i + 1])); + } + const hv2 even = ((ev[0] + ev[1]) + (ev[2] + ev[3])) + (ev[4] + ev[5]); + const hv2 odd = ((eo[0] + eo[1]) + (eo[2] + eo[3])) + (eo[4] + eo[5]); + hv2 s = even + odd; + s = s + hv2_of(bfly1_bits(u32_of(s))); + s = s + hv2_of(bfly2_bits(u32_of(s))); + const uint32_t p = u32_of(s); + // the PTX broadcasts the f16 sum of the two halves (add.f16) and takes + // cvt.f32.f16 of it: the value, not its bits + const half_t r = (half_t)__zluda_ptx_impl_rcp_approx_f32((float)(half_lo(p) + half_hi(p))); + const uint32_t rcp = pair_of(r, r); +#pragma unroll + for (int i = 0; i < 6; ++i) { + prob[2 * i] = u32_of(ev[i] * hv2_of(rcp)); + prob[2 * i + 1] = u32_of(eo[i] * hv2_of(rcp)); + } +} + +// --------------------------------------------------------------------------- +// The eight 16x160x32 projections, phases 13-20. +// +// E12 (PTX s11968-s12241) requantises D12 to e4m3, packs each of its four +// 16x32 m-tiles into an A fragment and stores them at +// smem + %tid.z*2048 + 512*m-tile + laneid*16 +// so every %tid.z group keeps its own attention output. E13-E19 then read +// back, for phase 13+j, the fragment at `smem + laneid*16 + 2048*j + +// 512*%tid.z`: m-tile %tid.z of group j's D12 -- eight groups of four tiles, +// and only the %tid.z <= 3 groups carry on (the rest branch to the epilogue's +// exit at s12027, after the stores). The fragment is in the mma's own A +// layout: word o, byte j -> row g + 8*(o&1), k = 2t + (j&1) + 16*((j>>1)&1) +// + 8*(o>>1), the same one the prologue staged. + +// the lane's four A words of one staged fragment +DEVF const lds_u32* tile_frag(uint32_t scratch, int group, int tile) +{ + return (const lds_u32*)(uintptr_t)scratch + + 4u * lane_id() + 128u * (uint32_t)(4 * group + tile); +} + +// D12's m-tile mi as its A fragment's four words. Word o = 2*(o>>1) + (o&1) +// is row (o&1)'s k-slice (o>>1), so word 0 is (row g, k = 2t, 2t+1, 16+2t, +// 17+2t) out of n-tiles 0 and 2 and word 2 the same out of n-tiles 1 and 3. +DEVF void d12_frag(const uint32_t d12[4][2][4], int mi, uint32_t af[4]) +{ +#pragma unroll + for (int o = 0; o < 4; ++o) { + const uint32_t lo = e4m3x2(d12[mi][o & 1][2 * (o >> 1)]); + const uint32_t hi = e4m3x2(d12[mi][o & 1][2 * (o >> 1) + 1]); + af[o] = lo | (hi << 16); + } +} + +// one 16x160x32 mma phase: A is the staged fragment, B the image's ten +// 512-byte tiles (two n-tiles each) and C the per-column table plus the block's +// input tile x. The dot product runs in f32 and rounds to f16 once, exactly +// as the translated mma does. +DEVF void proj160(const uint8_t* w, int base, const uint32_t af[4], + const uint32_t cg[20], const uint32_t ch[20], int t, + uint32_t d[2][20]) +{ +#pragma unroll + for (int nt = 0; nt < 20; ++nt) { + const int wb = base + 512 * (nt >> 1); + const int n0 = 8 * (nt & 1) + 2 * t; + float bv[2][32]; +#pragma unroll + for (int c = 0; c < 2; ++c) { +#pragma unroll + for (int k = 0; k < 32; ++k) { + bv[c][k] = e4m3_to_f32(w[waddr(wb, k, n0 + c)]); + } + } + double a0 = 0.0, a1 = 0.0; +#pragma unroll + for (int o = 0; o < 4; ++o) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + const int k = 2 * t + (j & 1) + 16 * ((j >> 1) & 1) + 8 * (o >> 1); + const double av = e4m3_to_f32((af[o] >> (8 * j)) & 0xffu); + a0 += av * (double)bv[0][k]; + a1 += av * (double)bv[1][k]; + } + } + d[0][nt] = pair_of((half_t)(float)(a0 + (double)h2f(cg[nt])), + (half_t)(float)(a1 + (double)h2f(cg[nt] >> 16))); + d[1][nt] = pair_of((half_t)(float)(a0 + (double)h2f(ch[nt])), + (half_t)(float)(a1 + (double)h2f(ch[nt] >> 16))); + } +} + +// one byte of the prologue's staged A fragments: m-tile `mi`, column `col` +// (0..159, so k-slice col>>5), row half `rh`. x is a decode of e4m3 codes, so +// the staged byte is the very value the C-seed adds use. +DEVF uint16_t xcell(const lds_u32* as, int mi, int col, int rh) +{ + const int k = col & 31; + const uint32_t word = as[128u * (uint32_t)(5 * mi + (col >> 5)) + + 2u * (uint32_t)((k >> 3) & 1) + (uint32_t)rh]; + const uint32_t j = (uint32_t)(k & 1) | (((uint32_t)(k >> 4) & 1u) << 1); + return __builtin_bit_cast(uint16_t, (half_t)e4m3_to_f32((word >> (8 * j)) & 0xffu)); +} + +// the C seeds' x half, before the table: forty b32 per lane, n-tile major and +// the lane's two columns of each, row g in xg and row g+8 in xh +DEVF void proj_x(const lds_u32* as, int mi, int t, uint32_t xg[20], uint32_t xh[20]) +{ +#pragma unroll + for (int nt = 0; nt < 20; ++nt) { + uint32_t g = 0, h = 0; +#pragma unroll + for (int c = 0; c < 2; ++c) { + const int col = 8 * nt + 2 * t + c; + const uint32_t sh = 16u * (uint32_t)c; + g |= (uint32_t)xcell(as, mi, col, 0) << sh; + h |= (uint32_t)xcell(as, mi, col, 1) << sh; + } + xg[nt] = g; + xh[nt] = h; + } +} + +// E12's per-column table: twenty ld.global.v2.u16 at W+221520+16*i, the last +// one at W+221504, so n-tile nt reads chunk (nt+19) % 20 -- the lane's two +// halves are 2t and 2t+1 of it. +DEVF uint32_t tabpair(const uint8_t* w, int nt) +{ + const int t = (int)(lane_id() & 3); + const int chunk = (nt + 19) % 20; + return *(const uint32_t*)(w + 221504u + 16u * (uint32_t)chunk + 4u * (uint32_t)t); +} + +// the C seeds: table[column] + x[row][column], f16 add as the PTX does +DEVF void proj_c(const uint8_t* w, const uint32_t xg[20], const uint32_t xh[20], + uint32_t cg[20], uint32_t ch[20]) +{ +#pragma unroll + for (int nt = 0; nt < 20; ++nt) { + const uint32_t tab = tabpair(w, nt); + cg[nt] = pair_of((half_t)(h2f(tab) + h2f(xg[nt])), + (half_t)(h2f(tab >> 16) + h2f(xg[nt] >> 16))); + ch[nt] = pair_of((half_t)(h2f(tab) + h2f(xh[nt])), + (half_t)(h2f(tab >> 16) + h2f(xh[nt] >> 16))); + } +} + + +// --------------------------------------------------------------------------- +// Ground truth for a stage comes from kernels/rr/swin_enc5_recipe.py's debug +// recipe: with D4R_RRSWIN_DEBUG=w1 (w2 … w10) the splice keeps NVIDIA's whole +// body and stores that phase's forty-eight accumulator registers into the plane +// arena at +46,000,000, which the kernel never otherwise writes, and the launch +// dump then holds the translated values for a block/lane. Built with +// -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), this +// body stores the same registers of its own phase n in the same order, so the +// two dumps compare byte for byte. +#ifndef D4R_RRSWIN_DEBUG_STAGE +#define D4R_RRSWIN_DEBUG_STAGE 0 +#endif + +DEVF void debug_store(const uint8_t* prm, const uint32_t* regs, int n) +{ + // the oracle's splice is predicated on %tid.z == 0: the eight waves of a block + // share one per-block slot, so only one group may fill it + if (__builtin_amdgcn_workitem_id_z() != 0) { + return; + } + const uint32_t block = __builtin_amdgcn_workgroup_id_x() + + 5u * __builtin_amdgcn_workgroup_id_y(); + if (block >= 64u) { + return; // the oracle's per-block slots only cover the first 64 blocks + } + const uint64_t arena = *(const uint64_t*)(prm + kPlaneArg); + // the oracle's slot: 32 lanes x n x 4 bytes, at least kDebugSlotFloor, rounded + // up to a power of two (its splice forms block*slot with a shift) + const uint64_t want = (uint64_t)n * 128ull > (uint64_t)kDebugSlotFloor + ? (uint64_t)n * 128ull : (uint64_t)kDebugSlotFloor; + uint64_t slot = 1; + while (slot < want) { + slot <<= 1; + } + uint32_t* dst = (uint32_t*)(arena + (uint64_t)kDebugBase + (uint64_t)block * slot + + (uint64_t)lane_id() * (uint64_t)n * 4ull); + for (int i = 0; i < n; ++i) { + dst[i] = regs[i]; + } +} + +// the stage's registers in the oracle's order: the phase's twenty-four mma, +// m-tile major and n-tile minor, each as the (row g, row g+8) pair the mma writes +DEVF void stage_regs(const uint32_t d[6][2][4], uint32_t regs[48]) +{ + int i = 0; +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d[mi][0][nt]; + regs[i++] = d[mi][1][nt]; + } + } +} + +// --------------------------------------------------------------------------- +// Mirror cut. The callee is handed the weight image (arg040), the parameter +// block and the base of the entry's 16384-byte `smem` array; the thirty staged +// A fragments are still in that array when the cut is taken, so they are read +// from `scratch` rather than passed (kernels/rr/swin_enc5_recipe.py explains the +// six registers that come back the other way). +extern "C" __attribute__((device)) void d4r_swin_enc5( + const uint8_t* w, const uint8_t* prm, uint32_t scratch) +{ + const int t = (int)(lane_id() & 3); // the lane's two columns of each n-tile + const int g = (int)(lane_id() >> 2); // ... and of its sixteen rows + // the lane's 16-byte slot in the staging array; fragment i is 512 bytes in + const lds_u32* const as = (const lds_u32*)(uintptr_t)scratch + 4u * lane_id(); + // phases 1-10 read their weights from this %tid.z's 27648-byte slot + const uint8_t* const wt = w + (uintptr_t)WIN_SLOTS * __builtin_amdgcn_workitem_id_z(); + + // ---- phases 1-10: the block's 96x64 input GEMM ------------------------- + // chain A is phases 1,3,5,7,9 and ends in D9 (columns 0..31); chain B is + // phases 2,4,6,8,10 and ends in D10 (columns 32..63). All ten read the same + // staged A operand; only the weights and the C chain differ, and the C chain + // is what the five k-steps of win_step accumulate. Phase 2*n-1 is chain A's + // k-step n and phase 2*n is chain B's, so a stage store sits after each. + uint32_t d9[6][2][4]; + uint32_t d10[6][2][4]; + win_zero(d9); + win_zero(d10); +#if D4R_RRSWIN_DEBUG_STAGE == 15 + { // the six staged A fragments of k-step 0, as the mma sees them + uint32_t regs[24]; +#pragma unroll + for (int mi = 0; mi < 6; ++mi) { +#pragma unroll + for (int o = 0; o < 4; ++o) { + regs[4 * mi + o] = as[128u * (uint32_t)(5 * mi) + (uint32_t)o]; + } + } + debug_store(prm, regs, 24); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 16 + uint32_t dbg16[16] = {0}; +#endif +#pragma unroll + for (int ks = 0; ks < 5; ++ks) { + win_step(wt, WIN_BASE_A, ks, as, t, d9, +#if D4R_RRSWIN_DEBUG_STAGE == 16 + dbg16 +#else + nullptr +#endif + ); +#if D4R_RRSWIN_DEBUG_STAGE == 16 + if (ks == 0) { + uint32_t regs[24]; +#pragma unroll + for (int i = 0; i < 16; ++i) { + regs[i] = dbg16[i]; + } + int q = 16; +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + regs[q++] = d9[0][0][nt]; + regs[q++] = d9[0][1][nt]; + } + debug_store(prm, regs, 24); + } +#endif + win_step(wt, WIN_BASE_B, ks, as, t, d10, nullptr); +#if D4R_RRSWIN_DEBUG_STAGE == 1 || D4R_RRSWIN_DEBUG_STAGE == 3 \ + || D4R_RRSWIN_DEBUG_STAGE == 5 || D4R_RRSWIN_DEBUG_STAGE == 7 \ + || D4R_RRSWIN_DEBUG_STAGE == 9 + if (ks == (D4R_RRSWIN_DEBUG_STAGE - 1) / 2) { + uint32_t regs[48]; + stage_regs(d9, regs); + debug_store(prm, regs, 48); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 2 || D4R_RRSWIN_DEBUG_STAGE == 4 \ + || D4R_RRSWIN_DEBUG_STAGE == 6 || D4R_RRSWIN_DEBUG_STAGE == 8 \ + || D4R_RRSWIN_DEBUG_STAGE == 10 + if (ks == (D4R_RRSWIN_DEBUG_STAGE - 2) / 2) { + uint32_t regs[48]; + stage_regs(d10, regs); + debug_store(prm, regs, 48); + } +#endif + } + + // ---- phases 11 and 12: the block's self-attention ----------------------- + // Phase 11: D11[mi][rh][nt] = row 16*mi + g + 8*rh of D9 dotted with row + // 16*(nt>>1) + g + 8*(nt&1) of D9 over the sixteen k's the two registers + // o = 2*(nt&1) and o+1 select, plus the 64x96 relative-position bias. The + // bias is twenty-four 512-byte tiles at slot + WIN_BIAS_SCORE, tile + // 4*(nt>>1) + mi, sixteen bytes per lane holding the four f16 of the lane's + // (nt&1) pair (PTX co for mma j = 12*mi + 2*(nt>>1) + (nt&1)). + uint32_t d11[4][2][12]; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int rh = 0; rh < 2; ++rh) { + uint32_t aw[2], a[2][4]; + row_words(d9, 16 * mi + g + 8 * rh, aw); + bfly2x4(aw, a); +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + uint32_t kw[2], kb[2][4]; + row_words(d9, 16 * (nt >> 1) + 8 * (nt & 1) + g, kw); + bfly2x4(kw, kb); + // the mma pairs A's register o with B's register o>>1, so the + // n-tile's parity picks the k-step both sides use + const int b = nt & 1; + // the same exact accumulation as win_step: the correctly rounded + // sum of the sixteen exact products, rounded once more into the bias + double s = 0.0; +#pragma unroll + for (int m = 0; m < 4; ++m) { +#pragma unroll + for (int j = 0; j < 4; ++j) { + s += (double)e4m3_to_f32((a[b][m] >> (8 * j)) & 0xffu) + * (double)e4m3_to_f32((kb[b][m] >> (8 * j)) & 0xffu); + } + } + const uint32_t bias = *(const uint32_t*)(wt + WIN_BIAS_SCORE + + 512u * (uint32_t)(4 * (nt >> 1) + mi) + + 16u * lane_id() + 8u * (uint32_t)(nt & 1)); + d11[mi][rh][nt] = pair_of((half_t)(float)(s + (double)h2f(bias)), + (half_t)(float)(s + (double)h2f(bias >> 16))); + } + } + } +#if D4R_RRSWIN_DEBUG_STAGE == 11 + { + uint32_t regs[96]; + int i = 0; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int nt = 0; nt < 12; ++nt) { + regs[i++] = d11[mi][0][nt]; + regs[i++] = d11[mi][1][nt]; + } + } + debug_store(prm, regs, 96); + } +#endif + + // Phase 12: P*V, three k-steps of 32 over the 96 key columns, each rounded + // to f16 before the next adds to it (the chain's C operand). The V rows a + // lane needs live on the other 31 lanes, so each k-step's 32 x 32 e4m3 block + // goes through shared memory -- one kilobyte per %tid.z, because the eight + // waves of the block share the 16384-byte array and each computes its own + // attention from its own weight slot. + uint32_t d12[4][2][4]; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int rh = 0; rh < 2; ++rh) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + d12[mi][rh][nt] = 0; + } + } + } +#pragma unroll + for (int ks = 0; ks < 3; ++ks) { + lds_u8* const vs = (lds_u8*)(uintptr_t)scratch + + (uintptr_t)WIN_V_BYTES * __builtin_amdgcn_workitem_id_z(); + // only the k-step's own 32 key rows (m-tiles 2*ks and 2*ks+1) go into the + // kilobyte, indexed by the row's offset inside the k-step +#pragma unroll + for (int m4 = 2 * ks; m4 < 2 * ks + 2; ++m4) { +#pragma unroll + for (int rh4 = 0; rh4 < 2; ++rh4) { + const int row = 16 * m4 + 8 * rh4 + g; + const int r = row - 32 * ks; +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + for (int c = 0; c < 2; ++c) { + const half_t v = dcell(d10, row, 8 * nt + 2 * t + c); + vs[r * 32 + 8 * nt + 2 * t + c] = (uint8_t)e4m3x2(pair_of(v, v)); + } + } + } + } + __builtin_amdgcn_wave_barrier(); +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int rh = 0; rh < 2; ++rh) { + uint32_t prob[12]; + row_probs(d11, mi, rh, prob); + // the k-step's A fragment: word 0 packs prob[4ks] and prob[4ks+2], + // word 1 prob[4ks+1] and prob[4ks+3] + uint32_t aw[2]; + aw[0] = e4m3x2(prob[4 * ks]) | (e4m3x2(prob[4 * ks + 2]) << 16); + aw[1] = e4m3x2(prob[4 * ks + 1]) | (e4m3x2(prob[4 * ks + 3]) << 16); + uint32_t af[2][4]; + bfly2x4(aw, af); +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + double acc0 = 0.0, acc1 = 0.0; +#pragma unroll + for (int kk = 0; kk < 32; ++kk) { + // the P byte for key column kk is the one the lane with + // t = (kk&7)>>1 packs into word (kk>>3)&1, byte + // 2*(kk>>4) + (kk&1); the two butterfly steps bring the + // other three lanes' eighths in + const uint32_t pa = + (af[(kk >> 3) & 1][(kk >> 1) & 3] + >> (8 * (2 * (kk >> 4) + (kk & 1)))) & 0xffu; + const int r = kk * 32 + 8 * nt + 2 * t; + acc0 += (double)e4m3_to_f32(pa) * (double)e4m3_to_f32(vs[r]); + acc1 += (double)e4m3_to_f32(pa) * (double)e4m3_to_f32(vs[r + 1]); + } + // the mma rounds to f16 after every k-step + const uint32_t prev = d12[mi][rh][nt]; + d12[mi][rh][nt] = pair_of((half_t)(float)(acc0 + (double)h2f(prev)), + (half_t)(float)(acc1 + (double)h2f(prev >> 16))); + } + } + } + __builtin_amdgcn_wave_barrier(); + } +#if D4R_RRSWIN_DEBUG_STAGE == 12 + { + uint32_t regs[32]; + int i = 0; +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { +#pragma unroll + for (int nt = 0; nt < 4; ++nt) { + regs[i++] = d12[mi][0][nt]; + regs[i++] = d12[mi][1][nt]; + } + } + debug_store(prm, regs, 32); + } +#endif + + // ---- E12: the C seeds' x, then D12 staged as the projections' A --------- + // x is read first: the staging below overwrites the fragments it lives in. + const int z = (int)__builtin_amdgcn_workitem_id_z(); + uint32_t xg[20], xh[20]; + proj_x(as, z, t, xg, xh); + { + lds_u32* const dst = (lds_u32*)(uintptr_t)scratch + 4u * lane_id() + + 128u * (uint32_t)(4 * z); +#pragma unroll + for (int mi = 0; mi < 4; ++mi) { + uint32_t af[4]; + d12_frag(d12, mi, af); +#pragma unroll + for (int o = 0; o < 4; ++o) { + dst[128 * mi + o] = af[o]; + } + } + } + __builtin_amdgcn_s_barrier(); // E12's bar.sync 0 at s12026 + if (z >= 4) { + return; // s12027: the upper %tid.z groups leave before phase 13 + } + + // ---- phases 13-20: eight 16x160x32 projections ------------------------- + // Every phase reads the same A-fragment slot out of every group's staging + // (phase 13+j is group j's m-tile z) and the same C seeds; only the weights + // differ, at the tail of the eight 27648-byte weight slots. + uint32_t cg[20], ch[20]; + proj_c(w, xg, xh, cg, ch); +#pragma unroll + for (int j = 0; j < 8; ++j) { + const uint32_t* const af = tile_frag(scratch, j, z); + uint32_t d[2][20]; + proj160(w, 22848 + 27648 * j, af, cg, ch, t, d); +#if D4R_RRSWIN_DEBUG_STAGE == 13 + if (j == 0) { + uint32_t regs[40]; +#pragma unroll + for (int nt = 0; nt < 20; ++nt) { + regs[2 * nt] = cg[nt]; + regs[2 * nt + 1] = ch[nt]; + } + debug_store(prm, regs, 40); + } +#endif +#if D4R_RRSWIN_DEBUG_STAGE == 14 + if (j == 0) { + uint32_t regs[40]; +#pragma unroll + for (int nt = 0; nt < 20; ++nt) { + regs[2 * nt] = d[0][nt]; + regs[2 * nt + 1] = d[1][nt]; + } + debug_store(prm, regs, 40); + } +#endif + (void)d; + } + + // ---- handing the accumulators back ------------------------------------- + // Phase 61's four accumulators and the two values E61 reads that are computed + // inside the region (%r29781 = %tid.z, %r29782 = the shared base) cross the cut + // through the last 768 bytes of the shared array, 24 bytes apart per lane. + __attribute__((address_space(3))) uint32_t* const out = + (__attribute__((address_space(3))) uint32_t*)(uintptr_t)scratch + + (16384u - 24u * 32u) / 4u + 6u * lane_id(); + (void)d12; + + // Phases 13-61 are not implemented yet; until they are, the four accumulators + // are filled with lane-distinct values so the read-back path is observable + // without producing wild magnitudes. + for (int i = 0; i < 4; ++i) { + out[i] = (uint32_t)lane_id() + 32u * (uint32_t)i; + } + out[4] = __builtin_amdgcn_workitem_id_z(); + out[5] = scratch; +} diff --git a/kernels/rr/rrswin_enc5_epilogues.md b/kernels/rr/rrswin_enc5_epilogues.md new file mode 100644 index 0000000..b172b2d --- /dev/null +++ b/kernels/rr/rrswin_enc5_epilogues.md @@ -0,0 +1,927 @@ +# `cuda_dldn_engine_swin_enc5_kernel` — the epilogues of phases 1…61 + +Companion to `kernels/rr/rr_layer_spec.py enc5`. Everything below was read out of +`~/.cache/d4r-rr-corpus/0018-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_enc5_kernel` (file lines 1018–51175). + +## 0. Conventions + +* **`sNNNN` is a statement index** in the linearisation `rr_layer_spec.py` + documents (statements of the entry body; a wrapped `{ … }` block and a 4-line + `mma.sync` count as one statement, numbered at their first line). **`LNNNNN` + is the physical line** of the same instruction in the corpus file, so every + claim can be checked with `sed -n 'LNNNNN,LNNNNN p' …ptx`. +* An **epilogue** is the run of statements between one phase's last `mma` and + the next phase's first `mma`; `Exx` below means *the epilogue of phase xx*. + The phase table (`rr_layer_spec.py enc5`) gives the ranges. +* `W` denotes the prepared weight image: `ld.param.u64 %rd2, + [cuda_dldn_engine_swin_enc5_kernel_param_0+40]` (s9, L1037) and + `cvta.to.global.u64 %rd3, %rd2` (s10, L1038). Every `ld.weak.global.ca.v4.u32` + reads `W + 16*laneid + imm`; the table loads (see §1.1) read + `W + ((laneid<<2)&12) + imm`. Exception: the B loads of phases 2–10, the + phase-1 B load and the phase-11 C seeds carry an extra `%tid.z*27648` term + (see §1.1's last row and §2.3). +* `%rd1` = the parameter-block base at `+80`: `mov.b64 %rd6, param_0` (s1, L1018) + then `add.s64 %rd1, %rd6, 80` (s4, L1032). So `[%rd1+n]` is `param_0+80+n` + and `[%rd1-72]` is `param_0+8`. +* `smem` denotes the module's shared array + `_ZZ33cuda_dldn_engine_swin_enc5_kernel33DldnEngineSwinEncParamsStructBaseE4smem`, + declared 16384 bytes by the cut-ABI dump. +* The C/D register layout and the weight-addressing formula are fixed (see the + settled notes): `C/D reg0 = (row g, cols 2t,2t+1)`, `reg1 = (row g+8, same + cols)`, `g = laneid>>2`, `t = laneid&3`; the A fragment's four registers are + `reg0 = row g, k = 2t + (j&1) + 16*((j>>1)&1)`, `reg1 = row g+8, same k`, + `reg2 = row g, k+8`, `reg3 = row g+8, k+8`. +* Anything I could not pin down from the PTX is in §5 under **uncharacterised**. + +## 1. Shared vocabulary + +### 1.1 Addresses and parameters an epilogue touches + +| symbol | how it is obtained | statements | +|---|---|---| +| `W` (weight image, 431124 bytes) | `ld.param.u64 %rd2, [param_0+40]` / `cvta.to.global.u64 %rd3, %rd2` | s9 / s10 | +| `smem` | `mov.u32 %r11623, _ZZ…BaseE4smem` | s7511 (L11833), s7405 (L11639), s20122 (L50821) | +| `%rd1` = `param_0+80` | `mov.b64 %rd6, param_0` + `add.s64 %rd1, %rd6, 80` | s1 / s4 | +| extents `(ex, ey)` | `ld.param.v2.u32 {%r446, %r447}, [param_0]` | s15 (L1043) | +| block offsets `(%rs119, %rs120)` | `ld.param.v2.u16 {%rs119, %rs120}, [param_0+80]` | s5 (L1033) | +| input buffer | `ld.param.u64 %rd8, [%rd1+-72]` = `param_0+8`, then `cvta %rd4` | s22 / s23 | +| plane arena | `ld.param.u64 %rd805, [%rd1+-32]` = `param_0+48`, then `cvta %rd5` | s19817 / s19818 | +| output surface (`sust`) | `ld.param.u64 %rd874, [%rd881+32]` = `param_0+112` | s20134 (L50833) | +| texture handle | `ld.param.u64 %rd872, [%rd881+8]` = `param_0+88` | s20229 (L51030) | +| per-lane weight address | `mul.wide.u32 %rdX, %laneid, 16` + `add.s64 %rdX, %rd3, %rdX` | every load block | +| per-lane weight address, phases 1–11 | `add.s64 %rd138, %rd2, %rd136` with `%rd136 = mul.wide(%tid.z*13824, 2)` then `+ 16*laneid` | s7507–s7508, s7545–s7546 | +| per-lane *table* address | `shl.b32 %rX, %laneid, 2` → `cvt.u64.u32` → `and.b64 %rdX, %rX, 12` → `add.s64 %rdX, %rd3, %rdX` = `W + ((laneid*4) & 12)` | s15140–s15142 and 60 copies | + +The last line matters: every `ld.global.v2.u16` / `ld.global.u32` table load in +an epilogue reads `W + ((laneid<<2)&12) + off`, i.e. **the four lanes with equal +`laneid&3` read the same address, so one load instruction covers one 16-byte +word of the table and 32 lanes cover a 512-byte span**. A 20-load group with +`step 16` therefore covers 320 bytes = 160 f16 = the 160 columns of an +`N=160` GEMM's C operand (one f16 per column, replicated over the 16 rows of a +tile); a 4-load group covers 64 bytes = 32 f16 = the 32 columns of an `N=32` +GEMM's C operand. + +### 1.2 Constants and helpers + +| register | first definition | f32/f64 literal | f16 value used | +|---|---|---|---| +| `%f476` | s8077 L14399 `mov.f32 %f476, 0f3C8CCB50` | 0.017186790704727173 | `0x2466` = 0.017181396484375 | +| `%fd383` | s8081 L14410 `mov.f64 %fd383, 0dBFE1CC0000000000` | −0.55615234375 | `0xB873` | +| `%fd385` | s8086 L14424 `mov.f64 %fd385, 0d3FE1CC0000000000` | +0.55615234375 | `0x3873` | +| `%f478` | s8092 L14442 `mov.f32 %f478, 0f3F6D6000` | 0.92724609375 | `0x3B6B` | +| `%f480` | s8097 L14456 `mov.f32 %f480, 0f3FB00000` | 1.375 | `0x3D80` | +| `%f1117` | s13641 L29561 `mov.f32 %f1117, 0f3ED306EB` | 0.4121621549129486 | `0x3698` | +| `%f1118` | s13644 L29568 `mov.f32 %f1118, 0f3DA60DD6` | 0.0810810774564743 | `0x2D30` | +| `%f1119` | s13647 L29575 `mov.f32 %f1119, 0f3F000000` | 0.5 | `0x3800` | +| `%f1120` | s13650 L29582 `mov.f32 %f1120, 0f40000000` | 2.0 | `0x4000` | +| `%fd770` | L8337 (prologue) `mov.f64 %fd770, 0d3F20000000000000` | 2⁻¹³ | `0x0800` = 0.0001220703125 | + +`%f1117…%f1120` are materialised **inside E21** (s13641–s13652) and re-used by +E23 … E59, which contain no `mov.f32`/`mov.f64` of their own. + +* `cvt.rn.satfinite.e4m3x2.f16x2` — the requantisation used everywhere + (`f16x2_to_e4m3x2_satfinite_bits` in `ptx/lib/zluda_ptx_impl.cpp`). +* `rcp.approx.ftz.f32`, `rsqrt.approx.ftz.f32`, `ex2.approx.ftz.f32`, + `div.approx.ftz.f32` — always wrapped as + `cvt.f32.f16 → op → cvt.rn.f16.f32` (each step rounded through f16). +* `mov.u32 %r11547, 0` (s7547, L11871) is the constant-zero C operand used by + every mma whose `C` field is `{%r11547, %r11547}`. + +## 2. Phase table, geometry and weight image + +### 2.1 The phase table + +`rr_layer_spec.py enc5` prints 61 phases. The columns are reproduced here with +the M/N/K arithmetic of §2.2: + +| # | stmt range | tool M | tool N | tool K | mma | grid | weight bytes | bias bytes | epi | +|---|---|---|---|---|---|---|---|---|---| +| 1 | s7554–s7577 | 96 | 32 | 32 | 24 | full | 320..844 | – | 7 | +| 2 | s7585–s7608 | 96 | 32 | 32 | 24 | full | 5440..5964 | – | 7 | +| 3 | s7616–s7639 | 96 | 32 | 32 | 24 | full | 1344..1868 | – | 7 | +| 4 | s7647–s7670 | 96 | 32 | 32 | 24 | full | 6464..6988 | – | 7 | +| 5 | s7678–s7701 | 96 | 32 | 32 | 24 | full | 2368..2892 | – | 7 | +| 6 | s7709–s7732 | 96 | 32 | 32 | 24 | full | 7488..8012 | – | 7 | +| 7 | s7740–s7763 | 96 | 32 | 32 | 24 | full | 3392..3916 | – | 7 | +| 8 | s7771–s7794 | 96 | 32 | 32 | 24 | full | 8512..9036 | – | 7 | +| 9 | s7802–s7825 | 96 | 32 | 32 | 24 | full | 4416..4940 | – | 7 | +| 10 | s7833–s7856 | 96 | 32 | 32 | 24 | full | 9536..10060 | – | 171 | +| 11 | s8028–s8075 | 64 | 96 | 32 | 48 | full | *(none)* | 10560..22348 | 3844 | +| 12 | s11920–s11967 | 192 | 96 | 96 | 48 | band | *(none)* | – | 274 | +| 13 | s12242–s12261 | 16 | 160 | 32 | 20 | full | 22848..27468 | – | 27 | +| 14 | s12289–s12308 | 16 | 160 | 32 | 20 | full | 50496..55116 | – | 27 | +| 15 | s12336–s12355 | 16 | 160 | 32 | 20 | full | 78144..82764 | – | 27 | +| 16 | s12383–s12402 | 16 | 160 | 32 | 20 | full | 105792..110412 | – | 27 | +| 17 | s12430–s12449 | 16 | 160 | 32 | 20 | full | 133440..138060 | – | 27 | +| 18 | s12477–s12496 | 16 | 160 | 32 | 20 | full | 161088..165708 | – | 27 | +| 19 | s12524–s12543 | 16 | 160 | 32 | 20 | full | 188736..193356 | – | 27 | +| 20 | s12571–s12590 | 16 | 160 | 32 | 20 | full | 216384..221004 | – | 1029 | +| 21 | s13620–s13639 | 80 | 160 | 160 | 20 | band | 222144..226764 | 227264..227312 | 321 | +| 22 | s13961–s13980 | 16 | 160 | 32 | 20 | full | 227328..231948 | – | 92 | +| 23 | s14073–s14092 | 80 | 160 | 160 | 20 | band | 232768..237388 | 237888..237936 | 172 | +| 24 | s14265–s14284 | 16 | 160 | 32 | 20 | full | 237952..242572 | – | 92 | +| 25 | s14377–s14396 | 80 | 160 | 160 | 20 | band | 243072..247692 | 248192..248240 | 172 | +| … | *(the 23/24 pair repeats with a fixed stride)* | | | | | | | | | +| 59 | s19545–s19564 | 80 | 160 | 160 | 20 | band | 418240..422860 | 423360..423408 | 172 | +| 60 | s19737–s19756 | 16 | 160 | 32 | 20 | full | 423424..428044 | – | 299 | +| 61 | s20056–s20065 | 80 | 80 | 160 | 10 | band | 428544..430604 | 431104..431120 | 234 | + +The odd phases 25…59 follow the exact pattern of 23 (weight +`= 243072 + 10240*((n-23)/2)`, bias `= 248192 + 10240*((n-23)/2)`, 172 +statements), and the even phases 26…60 follow 24 (weight +`= 237952 + 10240*((n-24)/2)`, 92 statements). + +### 2.2 The M/N/K arithmetic (`M/16 · N/8 · K/32 == mma`) + +Ranks hold for **53 of the 61 phases**. The eight failures are the banded +phases; in every one of them the tool's `M` (and, for P12, its `K`) is an +overcount because *18 of the 32 A/B register sets are k-slices, not distinct +row/column tiles*. The chain analysis that fixes them: + +| # | mma | tool M×N×K | product | fails? | correct reading | evidence | +|---|---|---|---|---|---|---| +| 1–10 | 24 | 96×32×32 | 24 | – | 96×32×32, dense | s7554: 6 A quads × 4 B pairs × 1 k-step | +| 11 | 48 | 64×96×32 | 48 | – | 64×96×32, dense | s8028: 4 A × 12 B × 1 | +| **12** | 48 | 192×96×96 | 432 | **no** | **64×32×96** = 4 m-tiles × 4 n-tiles × 3 k-steps | 16 chains of length 3, `chains_of` at s11920–s11967 | +| 13–20 | 20 | 16×160×32 | 20 | – | 16×160×32, dense | s12242: 1 A quad × 20 B pairs | +| **21,23,…,59** | 20 | 80×160×160 | 500 | **no** | **16×32×160** = 1 m-tile × 4 n-tiles × 5 k-steps | 4 chains of length 5 (s13620–s13639): A advances one k-slice per step; B advances 512 B per step, 2 n-tiles inside each 512-byte tile | +| 22,24,…,60 | 20 | 16×160×32 | 20 | – | 16×160×32, dense | s13961: 1 A quad × 20 B pairs | +| **61** | 10 | 80×80×160 | 250 | **no** | **16×16×160** = 1 × 2 × 5 | 2 chains of length 5, s20056–s20065 | + +For P12 the mma chain is +`s11920 A=%r11180 B=%r11474 → s11922 A=%r11200 B=%r11494 → s11924 A=%r11220 +B=%r11514`: three *different* A quads and three *different* B pairs accumulate +into one D, so the three are k-slices (k = 0/32/64) of one 16-row tile. Chains +0…3 share the A triple and take four different B triples; chains 4…7 use a +second A triple, and so on. The grid is therefore 4 A-tiles × 4 B-tiles × 3 +k-steps = 48, i.e. `(64×96)·(96×32)`, with `M=64, N=32, K=96`. + +For phase 21 the chain is +`s13620 A=%r14257 B=%r14064@222144 → s13622 A=%r14277 B=%r14068@222656 → +s13624 A=%r14297 B=%r14072@223168 → s13626 A=%r14317 B=%r14076@223680 → +s13628 A=%r14337 B=%r14080@224192`. The A quads are the five k-slices of one +16-row tile (K = 5·32 = 160) and the B pairs step 512 bytes, i.e. one k-slice +each; chain 1 uses the same five A quads with the B pairs at `+8` (the second +n-tile of the same 512-byte tile), which is why a 512-byte weight tile is +shared by two chains. Four chains → N = 32. + +The tool's own note on phase 12/21/61 (`grid: band`) is thus correct as a +*selection* remark but its `M`, `N`, `K` columns overcount by the k-slice +factor; the corrected shapes above are what a native replacement has to +produce. + +### 2.3 Weight image extent + +The prepared weight image is **431124 bytes**. The largest byte actually +loaded is `W+431120` (`ld.global.u32` at s20055, L50687), and 431120+4 = 431124; +no load reads past it. The corpus' largest `ld.weak.global.ca.v4.u32` offset is +`W+430592` (s20064, L50745) plus 12 bytes of the `v4` = 430604, inside the same +extent. + +One caveat, established in §3/E1–E9: the B loads of phase 1, phases 2–10 and +the C seeds of phase 11 are issued from `W + %tid.z*27648 + 16*laneid + off` +(`%rd138 = %rd2 + mul.wide(%tid.z*13824, 2)`, s7507–s7580), so those +phase-table offsets name four interleaved `%tid.z` blocks rather than a single +contiguous run. The image is laid out as 27648-byte slots: slot `k` holds the +`%tid.z = k` group's phases-1…11 weights in its first 22848 bytes and one later +phase's weights in its tail (`%tid.z = 0` slot tail = phase 13 at 22848, `k = 1` +tail = phase 14 at 50496, `k = 2` tail = phase 15 at 78144, …). Phases 12 and +later read from the plain `W + 16*laneid + off` base (e.g. s12036 L25015 +`add.s64 %rd641, %rd2, %rd640`). + +### 2.4 Phases that read no weight operand + +Every `B` operand of every phase resolves to the weight image **except two**: + +* **phase 11** — its B registers `%r11474…%r11584` are written by `mov.b32` at + s11705… (inside E11) and carry the transposed V (see §3/E11); the phase-table + B column is `?`. +* **phase 12** — its B registers are the same `movmatrix`/pack output written in + E11; the phase-table B column is `?`. + +Phase 11's *C* operand is a weight read (the 12288-byte score bias at +`W+10560…W+22348`, loaded in E10), and phase 12's C operand is the constant +`%r11547 = 0` (s7547), so neither phase reads a `B` from `W`. + +## 3. The epilogues + +| epilogue | range | stmts | named operation | +|---|---|---|---| +| E1–E9 | s7578–s7832 (nine 7-statement runs) | 7 each | next-B weight loads | +| E10 | s7857–s8027 | 171 | 24 B-fragment loads (phase 11's C bias) + pack phase 10's D | +| E11 | s8076–s11919 | 3844 | softmax of the 64×96 score block, V-transpose, pack | +| E12 | s11968–s12241 | 274 | pack phase 12's D → shared, 160-column table add, next B | +| E13–E19 | s12262–s12570 (seven 27-statement runs) | 27 each | shared A fetch + next-B loads | +| E20 | s12591–s13619 | 1029 | RMS norm (², sum, rsqrt, gain) + packs + next B/C | +| E21 | s13640–s13960 | 321 | clamped cubic activation + 160-column C build + pack | +| E23, E25, …, E59 | 172 statements each | 172 | clamped cubic activation + pack + next B | +| E22, E24, …, E58 | 92 statements each | 92 | pack the phase-20 output × gain → next odd phase's A + next B/C | +| E60 | s19757–s20055 | 299 | pack → plane-arena scatter → next B/C | +| E61 | s20066–s20299 | 234 | shared fade-in, softmax, texture gather, surface write | + +--- + +### E1–E9 — s7578–s7832: next-B weight loads + +Nine byte-identical 7-statement runs, each two `ld.weak.global.ca.v4.u32` at +`W + 16*laneid + {off, off+512}` = the *next* phase's B operand. The first +run: + +``` +s7578 L12051: mov.u32 %r5444, %laneid +s7579 L12053: mul.wide.u32 %rd140, %r5444, 16 +s7580 L12054: add.s64 %rd141, %rd138, %rd140 +s7581 L12055: add.s64 %rd94, %rd141, 5440 +s7582 L12057: ld.weak.global.ca.v4.u32 { %r5445,%r5446,%r5447,%r5448},[%rd94] +s7583 L12059: add.s64 %rd95, %rd141, 5952 +s7584 L12061: ld.weak.global.ca.v4.u32 { %r5449,%r5450,%r5451,%r5452},[%rd95] +``` + +The offsets, and the phase whose B they are, are: + +| run | statement range | offsets | next phase (weight bytes) | +|---|---|---|---| +| E1 | s7578–s7584 | +5440, +5952 | P2 (5440..5964) | +| E2 | s7609–s7615 | +1344, +1856 | P3 (1344..1868) | +| E3 | s7640–s7646 | +6464, +6976 | P4 (6464..6988) | +| E4 | s7671–s7677 | +2368, +2880 | P5 (2368..2892) | +| E5 | s7702–s7708 | +7488, +8000 | P6 (7488..8012) | +| E6 | s7733–s7739 | +3392, +3904 | P7 (3392..3916) | +| E7 | s7764–s7770 | +8512, +9024 | P8 (8512..9036) | +| E8 | s7795–s7801 | +4416, +4928 | P9 (4416..4940) | +| E9 | s7826–s7832 | +9536, +10048 | P10 (9536..10060) | + +The run base is `%rd138 = %rd2 + %rd136` (s7580), where +`%rd136 = mul.wide.u32(%r11621, 2)` and `%r11621 = %r9*13824` with +`%r9 = %tid.z` (s19 L1047, s7507 L11827, s7508 L11828). So the address these +nine runs and the prologue's phase-1 B load use is + +``` +W + %tid.z*27648 + 16*laneid + +``` + +**not** `W + 16*laneid + `: `%rd138` already carries a `%tid.z*27648` +term. (`rr_layer_spec.py`'s `track_weights` drops that term because it is the +result of a `mul.wide`, so the phase table's byte offsets for phase 1's B, +phases 2–10's B and phase 11's C bias are relative to +`W + %tid.z*27648`, whereas every other offset in the table is relative to +`W`. See §5 U7.) + +--- + +### E10 — s7857–s8027: phase 11's C-seed loads + pack of phase 10's D + +171 statements, 24 weight loads + 80 packs (histogram: `80 cvt.rn.satfinite`, +`40 mov.b32`, `25 add.s64`, `24 ld.weak.global.ca.v4.u32`). + +``` +s7861 L13686: ld.weak.global.ca.v4.u32 { %r7686,%r7687,%r7688,%r7689},[%rd112] // +10560 + … +s7907 L13778: ld.weak.global.ca.v4.u32 { %r7778,%r7779,%r7780,%r7781},[%rd135] // +22336 +s7908 L13781: cvt.rn.satfinite.e4m3x2.f16x2 %rs, %r… // first pack +``` + +* **24 loads** at `W + 16*laneid + 10560 + 512*i`, `i = 0…23` — the phase-11 + score-bias C seeds, byte block `[10560, 22348)` = 12288 bytes = 6144 f16. + Same layout as enc0's E9: the four C registers of one mma are the four u32 of + one 16-byte lane slot, tile index `4*(n>>1) + m`, stride 512 bytes. +* **80 packs / 40 b32** at s7908–s8027, whose sources are registers written by + **phase 9 and phase 10's mma** (traced through the `mov.b32` packs: 38 packs + come from a register whose newest definition is an `mma` of P9, 2 from P10, + 40 from sources the walk cannot resolve in one hop). These 40 b32 are + phase 11's A and B operands. + +**Outputs:** phase 11's 4+24 operand registers plus the 24 C-seed registers +(`%r7686…%r7781`). **Memory:** 24 weight loads, nothing else. + +--- + +### E11 — s8076–s11919: softmax of the 64×96 score block + +**Phase 11** = 48 `mma` (s8028–s8075), D registers 96 f16x2 (64 rows × 96 +columns, 8 rows × 8 cols per lane). The epilogue is byte-for-byte the same +algorithm as enc0's E5, with its own constants (they are *not* shared with any +other enc5 epilogue). Sub-sections, by first occurrence of each op class: + +| range | stmts | what | +|---|---|---| +| s8076–s10193 | 2118 | 96 per-element groups: scale, clamp, cubic, exponent extract | +| s10194–s10277 | 84 | in-lane partial row-sum trees (`add.f16x2` ×104 back to s10194) | +| s10278–s10311 | 34 | 16 `shfl.sync.bfly` → 8 row sums (`s10281 L21268` … `s10402 L21572`) | +| s10409–s11174 | 766 | 192 `rcp.approx.ftz.f32` → 96 reciprocals (`s10411 L21594`) | +| s11178–s11654 | 477 | 192 `mul.f16` → 96 probabilities (`s11178 L22839`) | +| s11656–s11703 | 48 | `movmatrix.sync.trans.aligned.m8n8.b16` (V-transpose) `s11656 L23893` | +| s11704–s11918 | 215 | 144 packs (`s11704 L24037`) | + +#### (a) per-element exponent, s8076–s10193 + +``` +s8077 L14399: mov.f32 %f476, 0f3C8CCB50 +s8080 L14407: mul.f16x2 %r8344,%r7862,%r8343 +s8085 L14421: max.f16x2 %r8347,%r8344,%r8349 +s8090 L14435: min.f16x2 %r8350,%r8347,%r8352 +s8096 L14453: fma.rn.f16x2 %r8355,%r8350,%r8353,%r8358 +s8101 L14467: fma.rn.f16x2 %r8359,%r8350,%r8355,%r8362 +s8102 L14470: shl.b32 %r11745, %r8359, 5 +s8103 L14471: and.b32 %r10264, %r11745, 2145419232 // 0x7FE07FE0 +``` + +Per f16 half `x` of each of the 96 D registers: + +``` +m = clamp(f16(x * 0.017181396484375), -0.55615234375, +0.55615234375) +t = f16(m*(-m) + 0.92724609375) +u = f16(m*t + 1.375) +E = bits(u)[9:5] // floor(32*frac(u)) — the top five mantissa bits +F = bits(u)[4:0] // the low five mantissa bits +expval = f16 from bits (E << 10) | (F << 5) // = 2^(E-15) * (1 + F/32) +``` + +i.e. `((u_bits << 5) & 0x7FE07FE0)` keeps `u`'s mantissa and drops its sign and +exponent, so the mantissa lands in the exponent field. This is not `exp` and +not `exp2(x*log2e)`: the exponent is the *cubic* +`32*(0.375 + 0.92724609375*m − m³)` quantised to a 6-bit significand. The +clamp bounds are the guard: `d/dm [0.92724609375m − m³]` vanishes at +`m = √(0.92724609375/3) = 0.55615…`. + +#### (b) in-lane partial sums, s10194–s10277 + +96 `expval` registers summed in groups with `add.f16x2` (104), giving 4 f16x2 +(= 8 f16) per group, i.e. **each lane reduces its 96 values to 24 partial sums +in 12 f16x2 registers**. + +#### (c) cross-lane row sums, s10278–s10311 + +``` +s10281 L21268: shfl.sync.bfly.b32 %r…, %r…, 1, %r…, -1 +s10290 L21292: add.f16 %rs2318,%rs2319,%rs2320 +``` + +Eight times (one per row `g, g+8` of the four m-tiles): add the two f16x2 +partials, butterfly over lane bits 0 and 1 (operands 1 and 2), add the two +halves with `add.f16`, then broadcast into both halves. Result: **8 row sums**, +covering all 96 columns because the four lanes with equal `laneid&7` hold +different column pairs. + +**There is no row maximum anywhere in this epilogue.** `max.f16x2` (96×) and +`min.f16x2` (96×) are the clamp of (a); the only warp shuffles are the 16 +`shfl.sync.bfly` above. + +#### (d) reciprocal, s10409–s11174 + +192 `rcp.approx.ftz.f32` = 96 f16x2 reciprocals, each +`cvt.f32.f16 → rcp.approx.ftz.f32 → cvt.rn.f16.f32` on a row-sum register +(duplicated, so each row sum is inverted once per n-tile of that row): + +``` +s10408 L21591: mov.b32 {hl, hu}, %r10719 +s10411 L21594: rcp.approx.ftz.f32 fl, fl +s10413 L21596: cvt.rn.f16.f32 hl, fl +``` + +#### (e) probabilities, s11178–s11654 + +192 `mul.f16` → 96 f16x2 results `p = expval * (1/rowsum)`; the column sums +computed in (b)/(c) cancel the constant `2⁻⁴⁷` of (a), so `p_ij ∝ 2^(32·u_ij)` +and `Σ_j p_ij = 1` up to the `rcp.approx` error. + +#### (f) V-transpose, s11656–s11703 + +**48** `movmatrix.sync.trans.aligned.m8n8.b16` on 48 distinct phase-10 D +registers (`%r7445`, `%r7446`, `%r7455`, … each exactly once). Each +transposes one 8×8 b16 tile built from the 32 threads' `%r`, i.e. 48 × 64 = +3072 values = the whole 96×32 D tile. + +#### (g) packs, s11704–s11918 + +144 packs in three groups: + +1. s11704–s11775 — from the **movmatrix** results → **phase 12's B** + fragments (`%r11474 … %r11584`, traced: `%r11474` is written by + `mov.b32 @s11705`, `%r11584` by `@s11768`). +2. s11776–s11893 — from the **probabilities** → phase 12's A fragments. +3. s11894–s11918 — more probability packs whose destinations are not read + after s11919 (compiler spill). + +**Inputs:** phase 11's 96 D f16x2, phase 10's 48 D f16x2, the three `shfl` +operands. **Outputs:** phase 12's 12 A quads / 12 B pairs and the five +constants of §1.2 (read again by E21–E59). **Memory:** none. + +--- + +### E12 — s11968–s12241: pack phase 12's D → shared, 160-column table, next B + +274 statements. Sub-sections: + +``` +s11968 L24876: bar.sync 0 +s11974 L24885: cvt.rn.satfinite.e4m3x2.f16x2 %rs3929, %r11208 +s11986 L24912: st.shared.v4.u32 [%r11876], {%r11880, %r11879, %r11878, %r11877} +s11999 L24941: st.shared.v4.u32 [%r11876+512], {…} +s12012: st.shared.v4.u32 [%r11876+1024], {…} +s12025: st.shared.v4.u32 [%r11876+1536], {…} +s12026 L25000: bar.sync 0 +s12033 L25010: ld.shared.v4.u32 {%r29390, %r29391, %r29392, %r29393}, [%r29389] +s12038 L25018: ld.weak.global.ca.v4.u32 { %r11895,…},[%rd160] // +22848 + … ten loads at +22848 + 512*i (i = 0…9), last s12056 L25054 (+27456) +s12062 L25063: ld.global.v2.u16 {%rs6407, %rs6408}, [%rd644+221520] + … twenty loads at +221520 + 16*i, last s12081 L25082 (+221808) +s12083 L25085: add.f16 %rs…, %rs6445, %rs… // first of 80 +``` + +1. **32 packs** of phase 12's D (s11974–s12025) → 16 b32, stored by **4 + `st.shared.v4.u32`** at `smem + %r9*512 + laneid*16` offsets + `0, 512, 1024, 1536` (`%r11876 = %r11623 + %r9<<11 + laneid*16`, s11969– + s11973). This is the A operand that E13–E19 fetch back. +2. **`bar.sync 0`**, then **one `ld.shared.v4.u32`** at `[%r29389]` + (`%r29387 = %r11623 + %r9<<9`, s12029) — a 512-byte reload of the same + staging, used as the source of the table add below. +3. **Ten weight loads** at `W + 16*laneid + 22848 + 512*i` → phase 13's 20 B + fragments. +4. **Twenty table loads** at `W + ((laneid<<2)&12) + 221520 + 16*i` (320 bytes, + 160 f16 = one f16 per column) → the 160-column vector. +5. **80 `add.f16`** (s12083–s12240) `= table[column] + shared_operand` → + 40 b32 = **phase 13's C seeds** (the epilogue's 96 `mov.b32` are the + pack/repack plumbing). + +**Outputs:** phase 13's 20 B fragments, 40 C seeds, and the shared staging. +**Memory:** 4 shared stores, 1 shared load, 10 + 20 weight loads. + +--- + +### E13–E19 — s12262–s12570: shared A fetch + next-B loads + +Seven identical 27-statement runs. Each begins with one `ld.shared.v4.u32` +that fetches the *next* phase's single A quad from the E12 staging, at a +2048-byte stride: + +| run | range | shared load | next-phase A base | B loads (phase, bytes) | +|---|---|---|---|---| +| E13 | s12262–s12288 | s12265 L25628 `[%r29396+2048]` | +2048 | P14, +50496 … | +| E14 | s12309–s12335 | s12312 `[%r29402+4096]` | +4096 | P15, +78144 … | +| E15 | s12356–s12382 | s12359 `[%r29408+6144]` | +6144 | P16, +105792 … | +| E16 | s12403–s12429 | s12406 `[%r29414+8192]` | +8192 | P17, +133440 … | +| E17 | s12450–s12476 | s12453 `[%r29420+10240]` | +10240 | P18, +161088 … | +| E18 | s12497–s12523 | s12500 `[%r29426+12288]` | +12288 | P19, +188736 … | +| E19 | s12544–s12570 | s12547 `[%r29432+14336]` | +14336 | P20, +216384 … | + +Each run also contains **ten `ld.weak.global.ca.v4.u32`** at +`W + 16*laneid + base + 512*i`, `i = 0…9` — the next phase's 20 B fragments +(`s12270 L25636` is the first of E13's). The A quad itself is loaded by the +preceding phase's epilogue at `+0, +2048, …`, so the shared array holds eight +2048-byte A tiles. Nothing else happens. + +--- + +### E20 — s12591–s13619: RMS norm before the MLP, and the odd phases' operand + +1029 statements, no stores, 20 table loads, 10 weight loads, 4 bias loads, +40 packs. Op boundaries: + +| range | op | +|---|---| +| s12591–s12596 | first of 240 `mul.f16` — 96 f16x2 squares of phase 20's D | +| s12753–s12817 | 42 `add.f16x2` + 4 `shfl.sync.bfly.b32` (`s12795 L27521`) → 8 row sums | +| s12804–s12940 | 82 `add.f16` | +| s12820–s12821 | `mov.f64 %fd386, 0d3F20000000000000` (L27587) + `cvt.rn.f16.f64 %rs4446, %fd386` — the `2⁻¹³` epsilon | +| s12944–s13261 | 80 `cvt.f32.f16` + 80 `rsqrt.approx.ftz.f32` (`s12946 L27961`) + 80 `cvt.rn.f16.f32` | +| s13268–s13287 | 20 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + 221840 + 16*i` — the norm gain | +| s13300–s13528 | `mul.f16` ×(gain) | +| s13532–s13550 | 10 `ld.weak.global.ca.v4.u32` at `W + 16*laneid + 222144 + 512*i` → phase 21's B | +| s13556–s13559 | 4 `ld.global.u32` at `W + ((laneid<<2)&12) + 227264 + 16*i` → phase 21's C seed | +| s13560–s13618 | 40 packs | + +**What it computes.** For each of the 8 rows a lane holds: + +``` +sumsq[row] = Σ_c x[row,c]² (f16, 4-lane butterfly) +inv = rsqrt.approx.ftz.f32(f32(f16(sumsq + 2⁻¹³))) // rounded to f16 +out[row,c] = x[row,c] * inv * gain[c] +``` + +with **no mean subtraction and no `1/N`** (the quantity is the raw sum of +squares plus `2⁻¹³`), and `gain[c]` read per column from the 320-byte table at +`W+221840…W+222128`. The norm's bias is not added here; it arrives as a C +operand later. + +The 40 packs are the crucial part: tracing each pack's source shows that +**19 packs read a register whose newest definition is a phase-20 `mma`, 1 reads +phase 20's last `mma`, and 20 read one of the 20 gain loads at +`W+221840…W+222128`**. So E20 produces **the odd phases' A operand**: the +normalised tile scaled by the gain table, packed to e4m3. This same pack +content is reproduced in E22, E24, …, E58 (§3). + +**Outputs:** phase 21's B (`%r14064…`) and C (`%r14154, %r14164, %r14254, +%r14264`), phase 21's A (in E21), and the shared staging. **Memory:** 20 table +loads, 1 shared load, 10 + 4 weight loads. + +--- + +### E21 — s13640–s13960: clamped cubic activation + 160-column C build + +321 statements. This is the only epilogue that materialises the four activation +constants (s13641–s13652). + +``` +s13641 L29561: mov.f32 %f1117, 0f3ED306EB +s13648 L29578: cvt.rn.f16.f32 low, %f1119 // 0.5 +s13650 L29582: mov.f32 %f1120, 0f40000000 // 2.0 +s13653 L29590: neg.f16x2 %r14350,%r14349 +s13654 L29594: max.f16x2 %r14352,%r14225,%r14350 +s13655 L29598: min.f16x2 %r14355,%r14352,%r14349 +s13656 L29602: abs.f16x2 %r14358,%r14355 +s13657 L29606: mul.f16x2 %r14360,%r14347,%r14358 +s13658 L29610: sub.f16x2 %r14363,%r14346,%r14360 +s13659 L29614: mul.f16x2 %r14366,%r14355,%r14363 +s13660 L29618: add.f16x2 %r14369,%r14348,%r14366 +s13661 L29622: mul.f16x2 %r14372,%r14225,%r14369 +``` + +Per element, over each of the 8 f16x2 D registers of phase 21 (its four chains, +two registers each): + +``` +y = clamp(x, -2, +2) +g = 0.5 + y * (0.412109375 - 0.0810546875 * |y|) // f16 throughout +out = x * g +``` + +`g` is a *cubic ramp*, not a sigmoid: `g(+2) = 1` ⇒ `out = x` for `x ≥ 2`; +`g(-2) = 0` ⇒ `out = 0` for `x ≤ -2`. **Reproduce the formula, not SiLU/GELU.** + +Then, in this order: + +| range | op | +|---|---| +| s13640–s13781 | 8 activation groups (each 4 `cvt` + 4 `mov.f32` + 10 f16x2 ops) | +| s13785–s13803 | 10 `ld.weak.global.ca.v4.u32` at `W + 16*laneid + 227328 + 512*i` → phase 22's B | +| s13809–s13828 | 20 `ld.global.v2.u16` at `W + ((laneid<<2)&12) + 232448 + 16*i` (320 bytes) | +| s13829–s13947 | 80 `add.f16` `= table[column] + residual` → 40 b32 | +| s13949–s13960 | 8 packs **of the activation outputs** → phase 22's A | + +Evidence for the split: + +``` +s13829 L30118: add.f16 %rs5210,%rs6526,%rs5212 // table + residual +s13831 L30125: mov.b32 %r14636, {%rs5207, %rs5210} // → phase 22's C +s13949 L30478: cvt.rn.satfinite.e4m3x2.f16x2 %rs5448, %r14488 // activation output +s13960 L30504: mov.b32 %r14823, {%rs5453, %rs5454} // → phase 22's A +s13961 L30506: mma … {%r14820, %r14821, %r14822, %r14823}, {%r14579, %r14580}, {%r14636, %r14637} +``` + +**Outputs:** phase 22's A (8 b32), phase 22's C (40 b32), phase 22's B +(`%r14579…`), and the four constants (consumed again by E23 … E59). + +--- + +### E23, E25, …, E59 — 172 statements each: activation + pack + next B + +Twenty runs, one after each odd banded phase, byte-identical in shape +(histogram: 32 `cvt.rn.f16.f32`, 36 `mov.b32`, 8 each `neg/max/min/abs.f16x2`, +24 `mul.f16x2`, 8 `sub.f16x2`, 8 `add.f16x2`, 10 `ld.weak.global.ca.v4.u32`, +8 packs). Same clamped cubic as E21 but **no table add and no `ld.global`**: + +``` +s14094 L30986: cvt.rn.f16.f32 low, %f1117 // constant from E21 +s14102 L31009: neg.f16x2 %r…,%r… +s14103 L31013: max.f16x2 %r…,%r…,%r… // phase 23's D +s14234 L31471: ld.weak.global.ca.v4.u32 {…},[%rd270] // +232768 … (phase 24's B) +s14253 L31510: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r… +``` + +The 10 weight loads are at `W + 16*laneid + base + 512*i` for the next even +phase (232768 for E23, 243072 for E25, …); the 8 packs are the activation +outputs and become the next even phase's A. No `mov.f32`, no `ld.global`, +no shared access. + +--- + +### E22, E24, …, E58 — 92 statements each: the shared odd-phase operand + +Twenty runs (histogram: 40 `cvt.rn.satfinite`, 20 `mov.b32`, 12 `add.s64`, +10 `ld.weak.global.ca.v4.u32`, 4 `ld.global.u32`). Example: + +``` +s13985 L30652: ld.weak.global.ca.v4.u32 { %r14579,…},[%rd260] // +227328 … (phase 23's B) +s14009 L30697: ld.global.u32 %r14919, [%rd676+237888] // phase 23's C, 4 words + … +s14013 L30702: cvt.rn.satfinite.e4m3x2.f16x2 %rs…, %r… +``` + +Tracing the pack sources of every one of these runs gives the *same* answer as +E20's pack group: **19 packs read a phase-20 `mma` register, 1 reads phase 20's +last `mma`, and 20 read one of the gain loads at `W+221840…W+222128`**. So +E22 … E58 do **not** consume their own phase's D: they re-emit the shared +odd-phase A operand (phase 20's normalised-and-gained output) for the next odd +phase, plus that odd phase's B and C. This is why every odd phase 21…59 uses +the same A operand (cf. the `a_source` column of `rr_layer_spec.py`). + +The four `ld.global.u32` are at `W + ((laneid<<2)&12) + {227264, 237888, +248192, …} + {0,16,32,48}` — a 64-byte, 32-column C seed for the next odd phase. + +--- + +### E60 — s19757–s20055: pack → plane-arena scatter → next B/C + +299 statements. Three sub-sections. + +#### (a) requantise, s19757–s19816 + +40 `cvt.rn.satfinite.e4m3x2.f16x2` + 20 `mov.b32` → `%r370 … %r389` (phase 60's +64×32 output as 20 b32 = 40 e4m3 values per lane). + +#### (b) plane-arena scatter, s19817–s20031 + +``` +s19817 L50393: ld.param.u64 %rd805, [%rd1+-32] // param_0+48 +s19818 L50394: cvta.to.global.u64 %rd5, %rd805 +s19820 L50398: shr.u32 %r390, %r29384, 2 // g = laneid>>2 +s19821 L50399: and.b32 %r391, %r29384, 3 // t = laneid&3 +s19822 L50400: shr.u32 %r29468, %r29384, 5 // laneid>>5 +s19823 L50401: and.b32 %r29469, %r390, 7 +s19824 L50402: add.s32 %r29470, %r369, %r29468 // y = %r369 + (laneid>>5) +s19830 L50408: add.s32 %r29471, %r1, %r29469 // x = %r1 + (g&7) +s19836 L50414: mad.lo.s32 %r392, %r7, %r29470, r29472 // %r7 = 8*ex +s19841 L50420: mul.wide.s32 %rd806, %r393, 4 +s19843 L50422: st.global.u32 [%rd807], %r370 +``` + +**Twenty guarded stores** `st.global.u32 [%rd5 + 4*idx]`, in statement order +`idx = + d` with `d = %r391 = t = laneid&3` for the first of a pair and +`d = %r394 = t|4` for the second: + +| # | statement | value | base | +|---|---|---|---| +| 1 | s19843 L50422 | `%r370` | `%r392` | +| 2 | s19852 L50433 | `%r371` | `%r392` | +| 3 | s19885 L50468 | `%r372` | `%r396` | +| 4 | s19893 L50478 | `%r373` | `%r396` | +| 5 | s19902 L50489 | `%r374` | `%r399 = %r392 + %r8` | +| 6 | s19910 L50499 | `%r375` | `%r399` | +| 7 | s19919 L50510 | `%r376` | `%r402 = %r396 + %r8` | +| 8 | s19927 L50520 | `%r377` | `%r402` | +| 9 | s19936 L50531 | `%r378` | `%r405 = %r399 + %r8` | +| 10 | s19944 L50541 | `%r379` | `%r405` | +| 11 | s19953 L50552 | `%r380` | `%r408 = %r402 + %r8` | +| 12 | s19961 L50562 | `%r381` | `%r408` | +| 13 | s19970 L50573 | `%r382` | `%r411 = %r405 + %r8` | +| 14 | s19978 L50583 | `%r383` | `%r411` | +| 15 | s19987 L50594 | `%r384` | `%r414 = %r408 + %r8` | +| 16 | s19995 L50604 | `%r385` | `%r414` | +| 17 | s20004 L50615 | `%r386` | `%r417 = %r411 + %r8` | +| 18 | s20012 L50625 | `%r387` | `%r417` | +| 19 | s20021 L50636 | `%r388` | `%r420 = %r414 + %r8` | +| 20 | s20029 L50646 | `%r389` | `%r420` | + +The two principal bases are built once: + +``` +s19823 L50401: and.b32 %r29469, %r390, 7 // g&7 +s19824 L50402: add.s32 %r29470, %r369, %r29468 // y = %r369 + (laneid>>5) +s19830 L50408: add.s32 %r29471, %r1, %r29469 // x = %r1 + (g&7) +s19835 L50413: shl.b32 %r29472, %r29471, 3 // 8*x +s19836 L50414: mad.lo.s32 %r392, %r7, %r29470, %r29472 // = 8*ex*y + 8*x +s19862 L50444: shl.b32 %r29772, %r446, 3 // 8*ex +s19864 L50446: shr.u32 %r29476, %r29475, 3 // (g+8)>>3 +s19865 L50447: and.b32 %r29477, %r29475, 7 // (g+8)&7 +s19866 L50448: add.s32 %r29478, %r29774, %r29476 +s19878 L50460: mad.lo.s32 %r396, %r29772, %r29478, %r29480 +``` + +with `g = laneid>>2`, `t = laneid&3`, `%r7 = %r446<<3 = 8*ex` (s17 L1045), +`%r8 = %r447 * %r7 = ey*8*ex` (s18 L1046, the **plane stride**), +`%r369 = %r3 + (tid.z<<1)` (s12592 L26961), `%r1`/`%r3` the block origins +(s7 L1035, s14 L1042), and every store guarded by +`p1/p2 = (y<0) | (y≥ey) | (laneid>15) | (x<0) | (x≥ex)` (s19825–s19834, +s19867–s19877): a guard failure stores `-1` as the index and the following +`setp.lt.s32 …, -1` + `bra` skips the store. Consecutive pairs therefore walk +**one plane per two stores**, i.e. the arena is a stack of `8*ex*ey`-u32 +planes. + +#### (c) next B/C, s20032–s20055 + +``` +s20032 L50650: ld.param.u64 %rd878, [param_0+40] +s20033 L50651: ld.param.u64 %rd877, [param_0+40] +s20040 L50661: ld.weak.global.ca.v4.u32 { %r29500,…},[%rd846] // +428544, phase 61's B + … five loads at +428544 + 512*i (last s20048 L50677, +430592) +s20054 L50686: ld.global.u32 %r29530, [%rd855+431104] // phase 61's C seed +s20055 L50687: ld.global.u32 %r29540, [%rd855+431120] +``` + +**Outputs:** phase 61's B (10 fragments) and C (`%r29530, %r29540`). +**Memory:** 20 plane-arena stores, 5 + 2 weight loads. + +--- + +### E61 — s20066–s20299: the final epilogue + +234 statements. It consumes the cut's four returned accumulators +(`%r29601, %r29611, %r29781, %r29782`). + +#### (a) shared fade-in, s20066–s20135 + +``` +s20066 L50758: bar.sync 0 +s20078 L50772: st.shared.u32 [%r430], %r29601 +s20082 L50777: st.shared.u32 [%r430+16], %r29611 +s20093 L50789: st.shared.u32 [%r432], %r29602 +s20095 L50792: st.shared.u32 [%r432+16], %r29612 +s20100 L50798: bar.sync 0 +s20129 L50828: ld.shared.u32 %r29649, [%r29759] +s20131 L50830: ld.shared.u32 %r29650, [%r29759+4] +s20132 L50831: ld.shared.u32 %r29653, [%r29759+8] +s20133 L50832: ld.shared.u32 %r29656, [%r29759+12] +s20135 L50834: ld.shared.u32 %r29670, [%r29759+16] +``` + +Four `st.shared.u32` write the returned accumulators (16 bytes apart) and five +`ld.shared.u32` read back a 20-byte window at +`%r29759 = smem + ((x*6 + y*48) << 2)` (s20125–s20128) — the two row groups' +values side by side. + +#### (b) bounds check, s20101–s20121 + +`s20111–s20112` form `x = %r1 + %r433`, `y = %r3 + %r434`; `s20116` reads +`param_0+0` (`%r29646, %r29647` = `(ex, ey)`); `s20113–s20120` build +`p350 = (laneid>>5 > 1) | (x|y < 0) | (x ≥ ex) | (y ≥ ey)` and `s20121 +bra $L__BB1_370` skips the rest. + +#### (c) softmax over 5 shared values, s20136–s20212 + +``` +s20138 L50838: max.f16x2 %r29648,%r29649,%r29650 +s20140 L50846: max.f16x2 %r29654,%r29651,%r29656 +s20142 L50851: max.f16 %rs…,%rs…,%rs… +s20145 L50860: sub.f16x2 %r29669,%r29670,%r29671 +s20148 L50868: mul.ftz.f32 %f…, %f…, 0f3FB8AA3B // *log2(e) +s20149 L50869: ex2.approx.ftz.f32 %f…, %f… +s20153 L50876: add.ftz.f32 %f…, %f…, %f… // row sum +s20205 L50988: div.approx.ftz.f32 %f1141, %f1142, %f1160 // 1/rowsum +s20208 L50995: mul.f16x2 %r29672,%r29673,%r29686 + … five f16x2 multiplies (s20208–s20212) +``` + +A real row max (`max.f16x2` ×3, `max.f16` ×2), `x − max`, `2^((x−max)·log2e)` +through `cvt.f32.f16 → mul → ex2.approx`, an f32 row sum, `div.approx.ftz.f32` +with `1.0`, and five `mul.f16x2` — a textbook f32 softmax, unlike E11's. + +#### (d) texture gather, s20213–s20296 + +`ld.param.u64 %rd872, [%rd881+8]` = `param_0+88` (s20229 L51030) is the texture +handle; nine `tex.base.2d.v4.f16.s32` (s20231 L51033 … s20290 L51153) sample it +at integer coordinates clamped into `[1, ex−2] × [1, ey−2]` (s20213–s20228, +s20240–s20248), and each result is folded in with `fma.rn.f16x2` against the +softmax weights (s20235 L51041, …, 12 total f16x2 fma) starting from +`%r29702 = 0` (s20130 L50829). + +#### (e) surface write, s20297 + +``` +s20297 L51171: sust.b.2d.v4.b16.zero [%rd874, {%r29753,%r436}], {%rs6599,%rs6603,%rs6607,%rs6614} +``` + +`%rd874` = `param_0+112` (s20134 L50833). One 4-channel b16 surface write per +lane; the fourth channel is the constant `0` (`s20296 L51169: mov.u16 %rs6614, +0`). `ret` at s20299 L51175. + +**Inputs:** the four returned accumulators, `param+0/+48/+88/+112`, the smem +window, `0f3FB8AA3B`, `0f3F800000`. +**Outputs:** none (the kernel returns). + +## 4. Memory traffic of the whole entry + +### 4.1 Global + +* **Weight-image B fragments** — `ld.weak.global.ca.v4.u32` in the E1–E9 runs, + E12–E19 runs, E20–E60 runs, always `W + 16*laneid + imm`, `imm` a phase-table + byte offset. The largest is `W+430592` (E60, s20048). +* **Per-column tables** — `ld.global.v2.u16` / `ld.global.u32` at + `W + ((laneid<<2)&12) + imm`. The complete list: + +| statements | offsets | loads | block | consumer | +|---|---|---|---|---| +| s6864–s6883 (prologue) | `W+0 … W+304`, step 16 | 20 × v2.u16 | 320 B | prologue normalise | +| s7861–s7907 (E10) | `W+10560 … W+22336`, step 512 | 24 × v4.u32 | 12288 B | phase 11's C (score bias) | +| s12062–s12081 (E12) | `W+221520 … W+221808`, step 16 | 20 × v2.u16 | 320 B | phase 13's C | +| s13268–s13287 (E20) | `W+221840 … W+222128`, step 16 | 20 × v2.u16 | 320 B | norm gain **and** odd-phase A | +| s13556–s13559 (E20) | `W+227264 … W+227312` | 4 × u32 | 64 B | phase 21's C | +| s13809–s13828 (E21) | `W+232448 … W+232752`, step 16 | 20 × v2.u16 | 320 B | phase 22's C | +| s14009–s14012 (E22) | `W+237888 … W+237936` | 4 × u32 | 64 B | phase 23's C | +| *(E24, E26, …, E58)* | `W + 237888 + 10240*k` | 4 × u32 | 64 B each | odd phases 25…61 at `W+431104` | +| s20054–s20055 (E60) | `W+431104, W+431120` | 2 × u32 | 8 B | phase 61's C | + +* **Plane arena (param_0+48)** — read once, at s19817 L50393 (E60), and written + by E60's twenty `st.global.u32` (§3/E60). Nothing reads it back inside this + launch. +* **Input buffer (param_0+8)** — read once, at s22 L1051 (`%rd8`), converted to + `%rd4` (s23 L1052); the prologue's `ld.global.v2.u16` reads (s178 L1218 and 39 + siblings, all `[%rd4 + mul.wide(%r29786, 4)]`) sample it at e4m3 pairs. +* **Texture handle (param_0+88)** — read once, at s20229 L51030 (E61). +* **Output surface (param_0+112)** — read once, at s20134 L50833 (E61), used as + the `sust.b.2d.v4.b16.zero` descriptor at s20297 L51171. +* **Extents (param_0+0)** — s15 L1043 (prologue) and s20116 L50814 (E61). +* **E61 does not read `param_0+24`, `+32`, `+48`, `+96` or `+104`.** + +### 4.2 Shared + +* **Prologue staging** — ten `st.shared.v4.u32` per `%tid.z` group, fed by 80 + e4m3 packs of the input buffer (s7364–s7403): + * five at `%r5148 + {0,512,1024,1536,2048}` where + `%r5148 = smem + %tid.z*2560 + laneid*16` (s7404…s7422, L11638…L11674, + last s7474 L11790); + * five at `%r5173 + {10240,10752,11264,11776,12288}` where + `%r5173 = %r5146 + laneid*16 = smem + %tid.z*2560 + laneid*16` + (s7499 region, s7484 L11803 … s7504 L11823). + + followed by a `bar.sync 0` (s7506 L11826). The staged A operands are read + back at s7513–s7542: thirty `ld.shared.v4.u32 [%r11624 + 512*i]`, + `i = 0…29`, with `%r11624 = smem + laneid*16` (s7510–s7512) — the read base + carries **no** `%tid.z` term, while the store base does; the correspondence + between the two is in §5 U8. +* **E12 staging** — 4 `st.shared.v4.u32` at + `smem + %tid.z*512 + laneid*16` offsets `0,512,1024,1536` (s11986 L24912 … + s12025), read back by the `ld.shared.v4.u32` of E12 (s12033) and E13–E19 + (offsets 2048 … 14336). +* **E61 staging** — 4 `st.shared.u32` + 5 `ld.shared.u32` (§3/E61(a)). + +Nothing else in the entry touches shared memory. + +## 5. Uncharacterised + +**U1. `param_0+24`, `+32`, `+96`, `+104`, `+120`, `+128` are never read.** A +grep of every `ld.param` in the entry (50 instructions, listed in §1.1) shows +exactly `param_0+0`, `+8`, `+40`, `+48`, `+80`, `+88`, `+112`; there is no read +at `+24`, `+32`, `+96`, `+104`, `+120` or `+128`. *Missing:* the parameter +struct's field names. + +**U2. The identity of the tables.** The 320-byte blocks at +`W+221504`/`W+221840`/`W+232448` (and the prologue's `W+0…W+304`) are per-column +f16 vectors read with the `W + ((laneid<<2)&12)` pattern. Their role is +*computable* (§3/E12, E20, E21) but their names are not. *Missing:* the weight +image's `_prep` permutation or the model's parameter names. + +**U3. Phase 11's and 12's B operands.** Both are register-resident (E11's +`movmatrix`/pack output, §3/E11), so the phase table's `?` weight/`band` columns +are correct; what the two operands *are* in model terms (V vs Vᵀ vs a +concatenation) is not determinable from the PTX alone. *Missing:* the +high-level attention formulation. + +**U4. The exact residual subtracted in E21's C build.** The 80 `add.f16` at +s13829–s13947 add a per-column table to a register pair whose provenance the +one-hop walk does not resolve (`%rs5212` etc.). The *arithmetic* is +`C = table[column] + residual` (s13829 L30118, s13831 L30125), but which +register holds the residual is not established. *Missing:* a full def-use chain +through the phase-20 norm. + +**U5. E22…E58's pack source.** The walk shows 20 of each run's 40 packs read +the gain loads at `W+221840…W+222128` and 20 read phase-20 `mma` registers, i.e. +the same content as E20's pack group. Whether that is a deliberate re-emission +of the shared A operand or an artefact of how the compiler scheduled one +operand across twenty uses cannot be decided from the PTX. *Missing:* the +source-level loop structure. + +**U6. The plane-arena geometry in E60.** The index is +`idx = (8*ex)*y + 8*x + d` with `d ∈ [0,8)`, so one row-stride unit is +`8*ex` u32 = `32*ex` bytes, but whether the arena is the same object as +`param_0+8` (the input read in the prologue) is not established — the two +pointers are distinct fields of the parameter block. *Missing:* the harness. + +**U7. The `%tid.z` weight-base term.** The B loads of phase 1, phases 2–10 and +the C seeds of phase 11 are issued from `W + %tid.z*27648 + 16*laneid + off` +(§2.3, §3/E1–E9), while every later phase uses `W + 16*laneid + off`. The +phase-table byte offsets for those eleven phases are therefore *not* absolute +image offsets. Whether the four `%tid.z` groups compute four different output +tiles of a 4×-wide GEMM, or four replicas of the same tile with different +weights, cannot be decided from the PTX: the A operands they read are +`%tid.z`-independent (shared reads at `smem + laneid*16`, §4.2), and their D +registers are physically the same registers. *Missing:* the block's launch +geometry (`%ntid.z`) and the high-level loop structure. + +**U8. The prologue's staging regions.** The ten staging stores per `%tid.z` +group write `[%tid.z*2560, %tid.z*2560+2560)` and +`[%tid.z*2560+10240, %tid.z*2560+12800)`; for `%tid.z = 3` the second block +ends at 20480, which exceeds the 16384-byte declaration of the shared array +(`.shared .align 4 .b8 _ZZ…smem[16384]`, L1027). The read side uses a +`%tid.z`-independent base (`smem + laneid*16`) and spans `[0, 15360)`, so the +store and load regions do not obviously line up for every `%tid.z`. *Missing:* +the launch's `%ntid.z` and the source-level staging loop; I could not decide +whether some `%tid.z` values never reach the stores (`setp.gt.u32 %p3, %r9, 3` +at s20 L1048 only excludes `%tid.z > 3`) or whether the array is over-allocated +by the ABI. + +## 6. Quick acceptance index + +| requirement | where | +|---|---| +| phase table with M/N/K checked | §2.1, §2.2 | +| weight image extent | §2.3 (431124 bytes) | +| phases that read no weight operand | §2.4 (11 and 12) | +| norm (RMS, no mean, `2⁻¹³`, per-column gain) | §3/E20, s12591–s13619 | +| attention (score, softmax, V-transpose, P·V) | §3/E10, E11, E12 | +| activations (clamped cubic, not GELU) | §3/E21, E23…E59 | +| merge / patch expand | no 8-lane merge (that device appears only in enc0's E20(c)); this layer's per-pixel gather is E61's 5 shared loads + 9 texture reads (§3/E61) | +| per-launch table in the plane arena | §4.1 and §3/E60(b) | +| plane-arena writes, exact value and index | §3/E60(b) | +| final epilogue | §3/E61 | diff --git a/kernels/rr/rrswin_engine.h b/kernels/rr/rrswin_engine.h new file mode 100644 index 0000000..6a7c7d7 --- /dev/null +++ b/kernels/rr/rrswin_engine.h @@ -0,0 +1,245 @@ +// The Swin-layer engine: descriptor-driven e4m3 GEMM phases for the eleven +// cuda_dldn_engine_swin_* denoiser layers. +// +// Why: the translated kernels are ~83,373 instructions for 536 FP8 WMMAs, dominated by +// operand reassembly (9,124 selects, 7,976 LDS permutes, ~23,000 shifts/ands/perms). An +// engine that keeps its activations as an e4m3 image and reads operands directly from it +// pays none of that. +// +// STATUS: every function here is validated by kernels/tools/rrswin_engine_k16_test.cpp, which +// runs on the GPU with checked HIP calls and compares against host models written independently: +// step 1 one k32 step, step 2 a 64-wide k chain as two k32 steps with f16 rounding between them, +// step 3 staging an accumulator as the next phase's operands (staged image dumped and compared +// byte for byte), step 4a/4b the weight preparation (slots checked directly, then through a GEMM +// against the documented image layout), step 4c a 32-row phase with two m-tiles, which is the +// case swin_gemm_tile's slot_step exists for, step 5/5a the phase loop itself, two phases chained +// through a staged image (the staged image is checked against the model as well), and step 6 +// swin_act_pair, the clamped cubic activation, against a scalar model of the specification's +// formula at a one-ulp bar (the device uses packed f16x2 ops, as the PTX does; the bit-exact +// check for it is the oracle comparison). The layout was measured, not assumed: +// kernels/tools/rrswin_operand_fit.cpp reports D's row index as VGPR i + 8*(lane>>4), its +// column index as lane & 15, and both operands' byte order as the identity. +// Step 3 of that test stages an accumulator and consumes it as the next phase's operands, and +// also dumps the staged image: every staged byte equalled the model's own e4m3 requantisation +// of D[k][col], so the accumulator-to-operand mapping ("D VGPR i is row i + 8h" is the next +// GEMM's k) is measured, not assumed. Its earlier mismatches were all bugs in the test: a +// k32 step mislabelled k16, a weight array too small for a second GEMM's slots, and a second +// k16 chunk left holding the first GEMM's operands. +// +// Layout facts this file uses, and where each comes from: +// 1. A k16 WMMA operand is 8 e4m3 bytes = this lane's half of a 16-byte row. "half h the K +// values 8h .. 8h+7 in order" -- kernels/common/wmma_layout.h +// 2. The lane/half selection is `8 * hf` with hf = lane >> 4, and the caller reads the row's +// 16 bytes from shared memory itself +// -- kernels/tex/enc0_tail.hip (working native) +// 3. A weight slot is the same 16 bytes per lane, `kslot_from16` is the identity under +// D4R_TEX_FP8 on gfx12, and `kop_image(img, idx)` picks this half +// -- kernels/tex/tex_common.h +// 4. `k32_e4m3(c, a0, b0, a1, b1)` is one m16n8k32 e4m3 step as two native gfx12 FP8 +// WMMAs and is bit-identical to ZLUDA's gfx12 lowering of NVIDIA's mma +// -- kernels/tex/tex_common.h (with tex_common's own +// comment, and enc0_tail/dec0_head using it in +// shipped, verified kernels) +#pragma once +#include +#include "../tex/tex_common.h" + +namespace rrswin +{ + +// This lane's operand for k16 chunk `chunk` of image row `row_base + (lane & 15)`; rows are +// `stride` bytes apart. The row comes from the lane, as in enc0_tail (`m = l & 15`), so a +// caller cannot pass a row that does not match its lane. A row holds consecutive k, 16 +// bytes per k16 chunk, so a k32 image needs stride >= 32; a smaller stride silently reads +// the next row. +__attribute__((device)) static inline kop swin_operand(const uint8_t* img, int stride, int row_base, int chunk) +{ + const uint32_t l = lane_id(); + const uint32_t half_bytes = (l >= 16) ? 8u : 0u; + const uint32_t row = (uint32_t)row_base + (l & 15u); + const uint2_t* p = (const uint2_t*)(img + (size_t)row * (size_t)stride + 16u * (uint32_t)chunk + half_bytes); + return kop_from8(*p); +} + +// One m16n16 output tile of one k32 step. The operand roles follow the working kernels +// (enc0_tail): the prepared weight slot is the A operand and the staged activation is the B +// operand, so the WMMA computes D^T relative to the token-major view. Both operands are +// lane-indexed: A's row and B's column are both `lane & 15` (wmma_layout.h: "A operand lane +// l = row r of A, B operand lane l = column r of B", r = l & 15), which is why the weight +// slot is `slot_base + (lane & 15)` and the two k16 halves of that slot are 16 slots apart +// -- exactly enc0_tail's `kop_image(w, slot)` / `kop_image(w, slot + 16)` with +// `slot = base + m`. +// `slot_step` is the distance between a row's two k16 slots. It is a parameter, not a +// constant, because a phase with more than one m-tile puts the next tile's rows in between: +// with slot_step fixed at 16 a 32-row phase would read tile 1's rows as tile 0's second k16. +// `k32_index` selects which 32-wide slice of the activations this step reads: a phase with more +// than one k32 step must advance the image's chunks too, or every step re-reads k 0..31. +__attribute__((device)) static inline f8v swin_gemm_tile(f8v c, const kslot* w, int slot_base, + int slot_step, const uint8_t* img, int stride, + int row_base, int k32_index = 0) +{ + const int slot = slot_base + (int)(lane_id() & 15u); + const kop a0 = kop_image(w, slot); + const kop b0 = swin_operand(img, stride, row_base, 2 * k32_index); + const kop a1 = kop_image(w, slot + slot_step); + const kop b1 = swin_operand(img, stride, row_base, 2 * k32_index + 1); + return k32_e4m3(c, a0, b0, a1, b1); +} + +// Stage an accumulator as the operand image of the next phase. On gfx12 the accumulator's +// layout *is* the operand layout (wmma_layout.h: "D VGPR i is row i + 8h, which is the gfx12 +// B-operand layout of the next GEMM (no exchange)"): this lane's VGPR i holds the value that +// belongs at k = i + 8*(lane >> 4) of column (lane & 15), so each lane requantises its own +// eight values to e4m3 and writes them at its own row's k-half -- no cross-lane movement. +// `row_base` is the first token column this tile covers and `chunk` the k16 chunk the tile's +// rows land in (a 16-row m-tile is one k16 chunk), so a phase with several tiles stages each +// into its own place. +__attribute__((device)) static inline void swin_stage_operand(uint8_t* img, int stride, int row_base, + int chunk, const f8v acc) +{ + const uint32_t l = lane_id(); + const uint32_t h = l >> 4, col = (uint32_t)row_base + (l & 15u); + uint8_t* p = img + (size_t)col * (size_t)stride + 16u * (uint32_t)chunk + 8u * h; +#pragma unroll + for (int i = 0; i < 8; i += 2) + { + const hv2 pair = {(half_t)acc[i], (half_t)acc[i + 1]}; + const uint32_t code = e4m3x2(__builtin_bit_cast(uint32_t, pair)); + p[i] = (uint8_t)(code & 0xffu); + p[i + 1] = (uint8_t)(code >> 8); + } +} + +// ---------------------------------------------------------------- weight preparation +// One phase's weights as WMMA slots, so the phase loop can read them with kop_image and never +// touch the image layout. Slot `base + 2*n_rows*s + n_rows*h + n` holds the k32 step s, k16 +// half h and output row n, i.e. 16 consecutive e4m3 bytes of k 32s + 16h .. +15; the caller +// passes that same `n_rows` as swin_gemm_tile's slot_step. The 2*n_rows per step is what keeps +// a step's two k16 halves adjacent for any row count. +// +// `waddr(k, n)` returns the byte offset of the weight image's element (k, n). Layer bodies +// document their own; enc0's is +// base + 512*(n>>4) + 64*(n&7) + 16*((k>>1)&3) + 8*((n>>3)&1) + 4*((k>>3)&1) + 2*((k>>4)&1) + (k&1) +// and a layer whose image differs passes its own lookup. Run it once per launch (a `_prep` +// kernel, as kernels/tex/enc0_tail.hip does for its weights). +template +__attribute__((device)) static inline void swin_prep_phase(uint8_t* slots, int base, int n_rows, + int k_steps, const uint8_t* image, + Lookup waddr) +{ + for (int n = 0; n < n_rows; ++n) + for (int s = 0; s < k_steps; ++s) + for (int h = 0; h < 2; ++h) + for (int j = 0; j < 16; ++j) + slots[(size_t)(16 * (base + 2 * n_rows * s + n_rows * h + n) + j)] = + image[waddr(32 * s + 16 * h + j, n)]; +} + +// ---------------------------------------------------------------- f16 pair helpers +// The packed-f16 plumbing kernels/rr/rrswin_enc0.hip defines for its epilogues. +__attribute__((device)) static inline half_t hf16(uint16_t bits) { return __builtin_bit_cast(half_t, bits); } +__attribute__((device)) static inline float h2f(uint32_t bits) +{ + return (float)__builtin_bit_cast(half_t, (uint16_t)bits); +} +__attribute__((device)) static inline hv2 hv2_of(uint32_t p) { return __builtin_bit_cast(hv2, p); } +__attribute__((device)) static inline uint32_t u32_of(hv2 v) { return __builtin_bit_cast(uint32_t, v); } +__attribute__((device)) static inline uint32_t pair_of(half_t a, half_t b) +{ + return (uint32_t)__builtin_bit_cast(uint16_t, a) | ((uint32_t)__builtin_bit_cast(uint16_t, b) << 16); +} + +// ---------------------------------------------------------------- epilogues +// The clamped cubic activation every layer's MLP applies before requantising: +// y = clamp(x, -2, +2); out = x * (0.5 + y * (0.412109375 - 0.0810546875 * |y|)) +// in f16 throughout, on the two halves of a packed pair. (Not SiLU/GELU: g(+2) = 1 and +// g(-2) = 0.) The constants are the f16 values of the PTX's 0f3ED306EB/0f3DA60DD6/0f3F000000/ +// 0f40000000 as kernels/rr/rrswin_enc0.hip documents them. +__attribute__((device)) static inline uint32_t swin_act_pair(uint32_t x) +{ + const hv2 two = hv2_of(pair_of(hf16(0x4000), hf16(0x4000))); + const hv2 slope = hv2_of(pair_of(hf16(0x2d30), hf16(0x2d30))); + const hv2 mid = hv2_of(pair_of(hf16(0x3698), hf16(0x3698))); + const hv2 half0 = hv2_of(pair_of(hf16(0x3800), hf16(0x3800))); + hv2 y = __builtin_elementwise_max(hv2_of(x), -two); + y = __builtin_elementwise_min(y, two); + y = __builtin_elementwise_max(y, -y); + const hv2 g = half0 + y * (mid - slope * y); + return u32_of(hv2_of(x) * g); +} + +// Stage NVIDIA's m16n8k32 A fragments as an image. The fragment layout is the one +// kernels/rr/rrswin_enc0.hip documents and verified against the oracle: +// reg 0 byte j -> row g, k = 2t + (j&1) + 16*((j>>1)&1) +// reg 1 byte j -> row g+8, same k +// reg 2 byte j -> row g, k = 8 + 2t + (j&1) + 16*((j>>1)&1) +// reg 3 byte j -> row g+8, same k +// with g = lane>>2 and t = lane&3. One m-tile's fragment is four registers per lane, so a +// phase's 4*m_tiles registers cover 16*m_tiles rows. Each lane scatters its own 16 bytes, which +// is a shared-memory store per byte -- the whole point of the engine is that this happens once +// per phase instead of once per mma. +__attribute__((device)) static inline void swin_stage_fragment(uint8_t* img, int stride, + const uint32_t* frag, int m_tiles) +{ + const uint32_t l = lane_id(); + const uint32_t g = l >> 2, t = l & 3u; + for (int mi = 0; mi < m_tiles; ++mi) + { + const uint32_t* f = frag + 4 * mi; + uint8_t* r0 = img + (size_t)(16 * mi + g) * (size_t)stride; + uint8_t* r1 = img + (size_t)(16 * mi + g + 8) * (size_t)stride; +#pragma unroll + for (int j = 0; j < 4; ++j) + { + const uint32_t k0 = 2 * t + (j & 1) + 16u * ((j >> 1) & 1); + const uint32_t k2 = 8u + k0; + r0[k0] = (uint8_t)(f[0] >> (8 * j)); + r1[k0] = (uint8_t)(f[1] >> (8 * j)); + r0[k2] = (uint8_t)(f[2] >> (8 * j)); + r1[k2] = (uint8_t)(f[3] >> (8 * j)); + } + } +} + +// ---------------------------------------------------------------- the phase loop +// One phase: m_tiles x n_tiles tiles of a k32-steps GEMM, each tile a 16x16 m16n16 WMMA block, +// with the epilogue staging each tile's accumulator as the next phase's activations. +struct Phase +{ + int m_tiles; // 16-row tiles of the weight image + int n_tiles; // 16-token tiles + int k32_steps; // k = 32 * k32_steps + int slot_base; // first weight slot of this phase (see swin_prep_phase) + int epilogue; // 0 stage the accumulator, 1 keep it in acc + int dst_image; // image the epilogue stages into (epilogue 0) +}; + +// Run one phase from `src`, staging requantized accumulators into `dst` or retaining them. +// `weight_rows` is the output row count used to prepare each pair of k16 weight slot banks. +// When retaining results, `acc` must hold m_tiles * n_tiles entries in row-major tile order. +__attribute__((device)) static inline void swin_phase(const Phase& ph, const kslot* w, int weight_rows, + const uint8_t* src, int src_stride, + uint8_t* dst, int dst_stride, f8v* acc) +{ + for (int mt = 0; mt < ph.m_tiles; ++mt) + for (int nt = 0; nt < ph.n_tiles; ++nt) + { + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + for (int step = 0; step < ph.k32_steps; ++step) + c = swin_gemm_tile(c, w, ph.slot_base + 16 * mt + 2 * weight_rows * step, weight_rows, + src, src_stride, 16 * nt, step); + if (ph.epilogue == 0) + swin_stage_operand(dst, dst_stride, 16 * nt, mt, c); + else if (acc != nullptr) + acc[mt * ph.n_tiles + nt] = c; + } +} + +// enc0's weight image layout, as its body documents it. +__attribute__((device)) static inline int swin_waddr_enc0(int k, int n) +{ + return 512 * (n >> 4) + 64 * (n & 7) + 16 * ((k >> 1) & 3) + 8 * ((n >> 3) & 1) + + 4 * ((k >> 3) & 1) + 2 * ((k >> 4) & 1) + (k & 1); +} + +} // namespace rrswin diff --git a/kernels/rr/swin_dec0_debug_stages.py b/kernels/rr/swin_dec0_debug_stages.py new file mode 100644 index 0000000..542a61c --- /dev/null +++ b/kernels/rr/swin_dec0_debug_stages.py @@ -0,0 +1,126 @@ +#!/usr/bin/env python3 +"""Oracle debug stages for cuda_dldn_engine_swin_dec0_kernel's 19 phases. + +Each stage is a (file line after which the store block goes, registers in order) tuple for +kernels/tex/make_ptx.py's SWIN_DEBUG_STAGES, so D4R_RRSWIN_DEBUG=p1 (p2, p3, ...) builds +NVIDIA's own body with that stage's registers stored into the buffer at arg048 + 46,000,000, +which kernels/rr/rrswin_dec0.hip's D4R_RRSWIN_DEBUG_STAGE reproduces from its own registers. + +The registers are read out of ~/.cache/d4r-rr-corpus/0023-PREPASS_ENTRYPOINT_NAME.ptx with +kernels/rr/rr_layer_spec.py's own parser: a phase is a maximal run of adjacent mma, and a +stage keeps the mma whose D pair no other mma of the same phase reads as its C (the last +k-step of an accumulating chain) and lists those tiles in mma statement order, each as the +(row g, row g+8) pair the mma writes. Phase 1 is 48x128 with K=64, so its 96 mma are 48 +chains of two steps and it contributes 48 pairs; phase 5 and phase 10 are 64x32 with +K=96, 48 mma in 16 chains of three steps, and contribute 16 pairs each. The splice line is +the `;` that ends the phase's last mma (its first line plus three). +""" + + +def swin_quads(bases): + """One A fragment per base: four b32.""" + return sum(([f"%r{b + o}" for o in range(4)] for b in bases), []) + + +def swin_seq(regs): + """A plain register list.""" + return list(regs) + + +def swin_pairs(bases): + """One register pair per base: a tile's (row g, row g+8) D registers.""" + return sum(([f"%r{b + rh}" for rh in (0, 1)] for b in bases), []) + + +def stages(): + """The stage table: name -> (splice line, registers).""" + return { + # phase 1: 48 tiles, splice after file line 2061 + "p1": (2061, + swin_pairs([484, 494, 524, 534, 564, 574, 604, 614, 644, 654, 684, 694, 724, 734, 764, + 774, 804, 814, 844, 854, 884, 894, 924, 934, 964, 974, 1004, 1014, 1044, 1054, 1084, + 1094, 1124, 1134, 1164, 1174, 1204, 1214, 1244, 1254, 1284, 1294, 1324, 1334, 1364, + 1374, 1404, 1414])), + # phase 2: 24 tiles, splice after file line 10622 + "p2": (10622, + swin_pairs([4655, 4665, 4675, 4685, 4695, 4705, 4715, 4725, 4735, 4745, 4755, 4765, + 4775, 4785, 4795, 4805, 4815, 4825, 4835, 4845, 4855, 4865, 4875, 4885])), + # phase 3: 24 tiles, splice after file line 10803 + "p3": (10803, + swin_pairs([4904, 4914, 4924, 4934, 4944, 4954, 4964, 4974, 4984, 4994, 5004, 5014, + 5024, 5034, 5044, 5054, 5064, 5074, 5084, 5094, 5104, 5114, 5124, 5134])), + # phase 4: 48 tiles, splice after file line 11520 + "p4": (11520, + swin_pairs([5321, 5331, 5341, 5351, 5361, 5371, 5381, 5391, 5401, 5411, 5421, 5431, + 5441, 5451, 5461, 5471, 5481, 5491, 5501, 5511, 5521, 5531, 5541, 5551, 5561, 5571, + 5581, 5591, 5601, 5611, 5621, 5631, 5641, 5651, 5661, 5671, 5681, 5691, 5701, 5711, + 5721, 5731, 5741, 5751, 5761, 5771, 5781, 5791])), + # phase 5: 16 tiles, splice after file line 21999 + "p5": (21999, + swin_pairs([8607, 8617, 8667, 8677, 8727, 8737, 8787, 8797, 8847, 8857, 8907, 8917, + 8967, 8977, 9027, 9037])), + # phase 6: 16 tiles, splice after file line 22535 + "p6": (22535, + swin_pairs([9089, 9099, 9109, 9119, 9129, 9139, 9149, 9159, 9169, 9179, 9189, 9199, + 9209, 9219, 9229, 9239])), + # phase 7: 24 tiles, splice after file line 22716 + "p7": (22716, + swin_pairs([9258, 9268, 9278, 9288, 9298, 9308, 9318, 9328, 9338, 9348, 9358, 9368, + 9378, 9388, 9398, 9408, 9418, 9428, 9438, 9448, 9458, 9468, 9478, 9488])), + # phase 8: 24 tiles, splice after file line 22897 + "p8": (22897, + swin_pairs([9507, 9517, 9527, 9537, 9547, 9557, 9567, 9577, 9587, 9597, 9607, 9617, + 9627, 9637, 9647, 9657, 9667, 9677, 9687, 9697, 9707, 9717, 9727, 9737])), + # phase 9: 48 tiles, splice after file line 23614 + "p9": (23614, + swin_pairs([9924, 9934, 9944, 9954, 9964, 9974, 9984, 9994, 10004, 10014, 10024, 10034, + 10044, 10054, 10064, 10074, 10084, 10094, 10104, 10114, 10124, 10134, 10144, 10154, + 10164, 10174, 10184, 10194, 10204, 10214, 10224, 10234, 10244, 10254, 10264, 10274, + 10284, 10294, 10304, 10314, 10324, 10334, 10344, 10354, 10364, 10374, 10384, 10394])), + # phase 10: 16 tiles, splice after file line 34088 + "p10": (34088, + swin_pairs([13210, 13220, 13270, 13280, 13330, 13340, 13390, 13400, 13450, 13460, 13510, + 13520, 13570, 13580, 13630, 13640])), + # phase 11: 16 tiles, splice after file line 34325 + "p11": (34325, + swin_pairs([13691, 13701, 13711, 13721, 13731, 13741, 13751, 13761, 13771, 13781, 13791, + 13801, 13811, 13821, 13831, 13841])), + # phase 12: 16 tiles, splice after file line 36579 + "p12": (36579, + swin_pairs([14179, 14189, 14199, 14209, 14219, 14229, 14239, 14249, 14259, 14269, 14279, + 14289, 14299, 14309, 14319, 14329])), + # phase 13: 16 tiles, splice after file line 39042 + "p13": (39042, + swin_pairs([15310, 15320, 15330, 15340, 15350, 15360, 15370, 15380, 15390, 15400, 15410, + 15420, 15430, 15440, 15450, 15460])), + # phase 14: 16 tiles, splice after file line 39290 + "p14": (39290, + swin_pairs([15512, 15522, 15532, 15542, 15552, 15562, 15572, 15582, 15592, 15602, 15612, + 15622, 15632, 15642, 15652, 15662])), + # phase 15: 16 tiles, splice after file line 41450 + "p15": (41450, + swin_pairs([16642, 16652, 16662, 16672, 16682, 16692, 16702, 16712, 16722, 16732, 16742, + 16752, 16762, 16772, 16782, 16792])), + # phase 16: 16 tiles, splice after file line 41698 + "p16": (41698, + swin_pairs([16844, 16854, 16864, 16874, 16884, 16894, 16904, 16914, 16924, 16934, 16944, + 16954, 16964, 16974, 16984, 16994])), + # phase 17: 16 tiles, splice after file line 43858 + "p17": (43858, + swin_pairs([17974, 17984, 17994, 18004, 18014, 18024, 18034, 18044, 18054, 18064, 18074, + 18084, 18094, 18104, 18114, 18124])), + # phase 18: 16 tiles, splice after file line 44106 + "p18": (44106, + swin_pairs([18176, 18186, 18196, 18206, 18216, 18226, 18236, 18246, 18256, 18266, 18276, + 18286, 18296, 18306, 18316, 18326])), + # phase 19: 16 tiles, splice after file line 46266 + "p19": (46266, + swin_pairs([19306, 19316, 19326, 19336, 19346, 19356, 19366, 19376, 19386, 19396, 19406, + 19416, 19426, 19436, 19446, 19456])), + # E1: the dequantised skip input (24 v2.u16 loads at param_0+24, 48 e4m3x2 registers) + "sk": (6695, swin_seq(list(range(4074, 4122)))), + # E1: the dequantised patch read back from the shared window (the 24 ld.shared.v2.u16) + "rp": (6840, swin_seq(list(range(4122, 4170)))), + # E1: the 24 packed A registers phases 2 and 3 read, fragment by fragment + "a2": (10442, swin_quads([9539, 9579, 9619, 9659, 9699, 9739])), + } diff --git a/kernels/rr/swin_dec0_recipe.py b/kernels/rr/swin_dec0_recipe.py new file mode 100644 index 0000000..49f7c64 --- /dev/null +++ b/kernels/rr/swin_dec0_recipe.py @@ -0,0 +1,231 @@ +"""Splice recipe for `cuda_dldn_engine_swin_dec0_kernel`. + +Self-contained: `kernels/tex/make_ptx.py` imports this module by path and returns +`recipe()` for the kernel name, so nothing here may import make_ptx. Everything +below is derived from the corpus PTX with `kernels/rr/rr_layer_spec.py`'s own +parser (the sibling module, imported for its lineariser and mma collector): the +mma region is `s326-s18231` (file lines 1393-46263), 544 mma in 19 phases, the +weight image is 47376 bytes at arg040, the parameter block is 152 bytes, and the +launch is grid 161x93 with block 32x1x1 (one wave). + +**Shape of the splice.** NVIDIA's plane/texture prologue (lines 1-1392) and its +surface epilogue (46264-end) are kept verbatim, and so is every epilogue between +the phases: E1's shared-window staging, the RMS norms, both attention softmaxes +and the clamped-cubic activations all stay NVIDIA's PTX, so the body only has to +reproduce the arithmetic the mma statements perform. Each phase's contiguous mma +run is replaced by one `call.uni` into `d4r_swin_dec0` with that phase's operands. + +**Why the calls need spill slots.** `call.uni` has no ABI: every register the +surrounding PTX still needs across the call is destroyed. So each block + + 1. stores the registers that are live across this call (defined before the + phase's first mma, read after its last) into `d4r_spill`, + 2. copies the phase's A/B/C operand registers into the parameter bank, + 3. calls, + 4. reads the phase's D registers back out of `d4r_spill` into the exact + register names the mma would have written, and + 5. reloads the spilled registers. + +The largest live-across set is 508 bytes per lane (phase 3), so the spill area +is `SPILL_SLOT` bytes per lane, and the largest D return is phase 1's 192 b32, +so the return area is `RET_SLOT` bytes per lane. Both are indexed off +`laneid * LANE_STRIDE` inside a single module-scope `.shared` array; the array is +declared in the `extern` string, which `make_ptx.py` emits at module scope (a +`.shared` declaration is not legal inside a block). + +**Operand encoding.** The callee receives, in this order, the phase number, the +A fragments (four b32 each, in first-use order), the B fragments (two b32 each, +in first-use order), the C words (two b32 per distinct C operand, in first-use +order), the weight image, the parameter block and its shared row base. B +fragments and C operands that `rr_layer_spec` resolves into the weight image are +*not* passed: the callee reads them from arg040 at the offsets the mma resolved. +Chain C operands (a previous k step's D) and the constant `%r13609` are not +passed either: the callee computes them. +""" + +import importlib.util +import os +import sys +from pathlib import Path + +_HERE = Path(__file__).resolve().parent +if str(_HERE) not in sys.path: + sys.path.insert(0, str(_HERE)) +import rr_layer_spec as SPEC # noqa: E402 (path is fixed up above) + +MODULE = "0023-PREPASS_ENTRYPOINT_NAME.ptx" +ENTRY = "cuda_dldn_engine_swin_dec0_kernel" +PARAM = ENTRY + "_param_0" + +# the cut: phase 1's first mma (line 1393) through phase 19's last (line 46266); +# make_ptx.py replaces lines[before-1:after-1] +CUT = (1393, 46267) + +# shared-memory geometry, bytes per lane +LANE_STRIDE = 1280 +RET_SLOT = 768 # 192 b32, phase 1's D +SPILL_SLOT = 512 # the widest live-across set is 508 +SPILL = RET_SLOT # spill area starts after the return area +SPILL_BYTES = LANE_STRIDE * 32 + +# the callee's parameter bank: MAXP b32 then b64, b64, b32. Phase 4 passes the +# most (137); rrswin_dec0.hip's d4r_swin_dec0 must declare the same count. +MAXP = 144 + +SPILL_SYMBOL = "d4r_spill" + + +def _ptx_dir(): + return Path(os.environ.get("D4R_DLSS_PTX_DIR", + _HERE.parent / "extracted" / "ptx")) + + +def _key(reg): + return (reg[:3], int(reg[3:]) if reg[3:] else 0) + + +def _analyse(): + """Every number the splice needs, read out of the corpus PTX.""" + lines = (_ptx_dir() / MODULE).read_text().split("\n") + body = next(((a, b) for n, a, b in SPEC.find_entries(lines) if n == ENTRY)) + if body is None: + raise SystemExit(f"{MODULE}: no entry {ENTRY}") + stmts, _ = SPEC.linearise(lines, *body) + defs = SPEC.track_weights(stmts, ENTRY) + mmas = SPEC.collect_mma(stmts, defs) + phases = SPEC.build_phases(stmts, mmas) + + last_w, last_r = {}, {} + for s in stmts: + for r in SPEC.dest_regs(s.text): + last_w[r] = s.idx + for r in SPEC.read_regs(s.text): + last_r[r] = max(last_r.get(r, 0), s.idx) + for group in SPEC.RE_OPERAND.findall(s.text): + for r in SPEC.REG_SRC.findall(group): + last_r[r] = max(last_r.get(r, 0), s.idx) + + out = [] + for p in phases: + lo, hi = p.mma[0].idx, p.mma[-1].idx + a_frag, b_frag, c_frag = [], [], [] + c_index, d_regs = [], [] + for m in p.mma: + a = tuple(m.regs("A")) + b = tuple(m.regs("B")) + if a not in a_frag: + a_frag.append(a) + if b not in b_frag: + b_frag.append(b) + d_regs.extend(m.regs("D")) + cregs = tuple(m.regs("C")) + if all(r in d_regs or r == "%r13609" for r in cregs): + c_index.append(-1) # chain or the zero constant + elif all(o is None for o in m.co): + c_index.append(-1) # resolved into the weight image + else: + if cregs not in c_frag: + c_frag.append(cregs) + c_index.append(c_frag.index(cregs)) + out.append(dict( + idx=p.idx, lo=lo, hi=hi, + line0=p.mma[0].line, line1=p.mma[-1].line + 3, + a=[r for f in a_frag for r in f], + b=[r for f in b_frag for r in f if defs.from_weight(r, lo) is None], + c=[r for f in c_frag for r in f], + c_index=c_index, d=d_regs, + spill=sorted((r for r in last_w if last_w[r] < lo and last_r.get(r, 0) > hi), + key=_key), + )) + return lines, out + + +def _extern(): + """The callee's declaration and the shared spill array, at module scope.""" + params = ", ".join(f".param .b32 d4r_p{i}" for i in range(MAXP)) + return (f".shared .align 4 .b8 {SPILL_SYMBOL}[{SPILL_BYTES}];\n" + f".extern .func d4r_swin_dec0\n(\n\t{params},\n" + "\t.param .b64 d4r_w, .param .b64 d4r_v, .param .b32 d4r_s\n)\n;\n") + + +def _spill_ops(ph): + """The st.shared / ld.shared pair that carries one live-across register.""" + lines = [] + for j, reg in enumerate(ph["spill"]): + off = SPILL + 4 * j + if reg.startswith("%rd"): + lines.append(f"\tmov.b64 {{%rtlo,%rthi}}, {reg};") + lines.append(f"\tst.shared.v2.b32 [%rk+{off}], {{%rtlo,%rthi}};") + elif reg.startswith("%p"): + lines.append(f"\tselp.b32 %rtlo, 1, 0, {reg};") + lines.append(f"\tst.shared.u32 [%rk+{off}], %rtlo;") + else: + lines.append(f"\tst.shared.u32 [%rk+{off}], {reg};") + return lines + + +def _reload_ops(ph): + lines = [] + for j, reg in enumerate(ph["spill"]): + off = SPILL + 4 * j + if reg.startswith("%rd"): + lines.append(f"\tld.shared.v2.b32 {{%rtlo,%rthi}}, [%rk+{off}];") + lines.append(f"\tmov.b64 {reg}, {{%rtlo,%rthi}};") + elif reg.startswith("%p"): + lines.append(f"\tld.shared.u32 %rtlo, [%rk+{off}];") + lines.append(f"\tsetp.ne.u32 {reg}, %rtlo, 0;") + else: + lines.append(f"\tld.shared.u32 {reg}, [%rk+{off}];") + return lines + + +def _block(ph): + """The `{ ... }` that replaces one phase's mma run.""" + k = ph["idx"] + n = 1 + len(ph["a"]) + len(ph["b"]) + len(ph["c"]) + if n > MAXP: + raise SystemExit(f"phase {k} needs {n} parameters, MAXP is {MAXP}") + decl = "\n".join(f"\t.param .b32 q{k}_{i};" for i in range(n)) + decl += f"\n\t.param .b64 qw{k};\n\t.param .b64 qv{k};\n\t.param .b32 qs{k};" + zero = "\n".join(f"\tst.param.b32 [q{k}_{i}+0], 0;" for i in range(n)) + operands = [f"\tst.param.b32 [q{k}_{i + 1}+0], {r};" + for i, r in enumerate(ph["a"] + ph["b"] + ph["c"])] + args = ", ".join([f"q{k}_{i}" for i in range(n)] + [f"qw{k}", f"qv{k}", f"qs{k}"]) + body = [ + f"mov.u32 %rk, {SPILL_SYMBOL};", + f"mad.lo.s32 %rk, %laneid, {LANE_STRIDE}, %rk;", + ] + body += _spill_ops(ph) + body += [decl, zero, "\n".join(operands)] + body += [ + f"ld.param.u64 %rv, [{PARAM}+40];", + f"st.param.b64 [qw{k}+0], %rv;", + f"mov.b64 %rv, {PARAM};", + f"st.param.b64 [qv{k}+0], %rv;", + f"st.param.b32 [qs{k}+0], %rk;", + f"call.uni d4r_swin_dec0, ({args});", + ] + body += [f"\tld.shared.u32 {ph['d'][i]}, [%rk+{4 * i}];" for i in range(len(ph["d"]))] + body += _reload_ops(ph) + return "\n".join(["{", + ".reg .b32 %rk, %rv, %rtlo, %rthi;", + "\n".join(body), + "}"]) + + +def _call(): + lines, phases = _analyse() + out = [] + cursor = CUT[0] + for ph in phases: + if not ph["spill"] and not ph["c"] and len(ph["a"]) + len(ph["b"]) > 0: + pass + out += lines[cursor - 1:ph["line0"] - 1] + out.append(_block(ph)) + cursor = ph["line1"] + 1 + out += lines[cursor - 1:CUT[1] - 1] + return "\n".join(out) + + +def recipe(): + return dict(file=MODULE, cut_call=CUT, extern=_extern(), call=_call()) \ No newline at end of file diff --git a/kernels/rr/swin_dec1_recipe.py b/kernels/rr/swin_dec1_recipe.py new file mode 100644 index 0000000..e78c256 --- /dev/null +++ b/kernels/rr/swin_dec1_recipe.py @@ -0,0 +1,386 @@ +#!/usr/bin/env python3 +"""Splice recipe for cuda_dldn_engine_swin_dec1_kernel (nvngx_dlssd.dll 310.7). + +kernels/tex/make_ptx.py's per-layer hook imports this module by path and returns +`recipe()`. Everything here is self-contained: nothing is imported from +make_ptx.py or rr_layer_spec.py. + +The cut replaces the whole 26-phase mma region of the entry -- physical lines +1486-38472 of ~/.cache/d4r-rr-corpus/0022-PREPASS_ENTRYPOINT_NAME.ptx, statement +range s403-s15988 -- with one `call.uni d4r_swin_dec1`. NVIDIA's texture +prologue (lines 1-1485, which stage phase 1's A fragments and its sixteen bias +seeds) and its surface epilogue (line 38473 to the end, which stages phase 26's +accumulators through shared memory, softmaxes over them, gathers three textures +and writes param_0+112) stay in PTX. + +The callee is handed, in this order: + + * the 36 A registers of phase 1 (nine .f16.e4m3 fragments of four b32, the + first mma's operand order), + * the sixteen C bias seeds phase 1 reads from the weight image at +24576..24816 + (every other mma's C operand is another mma's D register, which the body + computes itself, so no other C register is passed), + * the weight image pointer (%rd3, the `cvta.to.global` of param_0+40), + * the parameter block pointer (%rd8, param_0 itself), + * the address of the entry's 6400-byte .shared scratch. + +`call.uni` return values cannot come back to PTX (ZLUDA lowers them to an LLVM +return type with no .param-space object), so the ten values the epilogue reads +out of the deleted region cross the cut through the shared scratch, 40 bytes per +lane: phase 26's eight accumulator registers %r18794 %r18795 %r18804 %r18805 +%r18834 %r18835 %r18844 %r18845 (E26 stages them at s16000..s16019 and reads them +back at s16085..s16100), plus %r18991 (= 32*tid.z, computed inside the cut at +line 38396) and %r18993 (the shared base, line 38394). rr_layer_spec.py's +`live_across` reports only six of these because dest_regs() reads the first +register of an mma's D list only; the four second halves are read by E26 too. + +D4R_RRSWIN_DEBUG= builds NVIDIA's own body with that stage's registers +stored into the plane arena at +DEBUG_BASE, which kernels/rr/rrswin_dec1.hip +reproduces with -DD4R_RRSWIN_DEBUG_STAGE=. +""" + +import os + +MODULE = "0022-PREPASS_ENTRYPOINT_NAME.ptx" +CALLEE = "d4r_swin_dec1" + +# the mma region: the first mma's first physical line, and the line after the last +# mma's last physical line +CUT_CALL = (1486, 38473) + +# phase 1's A fragments, in the first mma's operand order (s403 reads %r1084..) +A_REGS = [ + "%r1084", "%r1085", "%r1086", "%r1087", + "%r1104", "%r1105", "%r1106", "%r1107", + "%r1124", "%r1125", "%r1126", "%r1127", + "%r1564", "%r1565", "%r1566", "%r1567", + "%r1584", "%r1585", "%r1586", "%r1587", + "%r1604", "%r1605", "%r1606", "%r1607", + "%r2044", "%r2045", "%r2046", "%r2047", + "%r2064", "%r2065", "%r2066", "%r2067", + "%r2084", "%r2085", "%r2086", "%r2087", +] + +# phase 1's sixteen bias seeds, in weight-image offset order (+24576, +24592, ...) +C_REGS = [ + "%r1621", "%r1631", "%r1681", "%r1691", + "%r1741", "%r1751", "%r1801", "%r1811", + "%r1861", "%r1871", "%r1921", "%r1931", + "%r1981", "%r1991", "%r2041", "%r2051", +] + +# what the epilogue reads back out of the deleted region +RET_REGS = ["%r18794", "%r18795", "%r18804", "%r18805", + "%r18834", "%r18835", "%r18844", "%r18845", + "%r18991", "%r18993"] +RET_STRIDE = 4 * len(RET_REGS) + +SCRATCH = "_ZZ33cuda_dldn_engine_swin_dec1_kernel33DldnEngineSwinEncParamsStructBaseE4smem" + +# registers the splice reads: %rd3 is the globalised weight image (s9), %rd8 is +# param_0 itself (s1) +W_REG = "%rd3" +V_REG = "%rd8" + +# --- oracle debug stages -------------------------------------------------- +# The payload goes into the param_0+8 feature-plane buffer, and at offset 0 from +# that pointer. enc0's stages use param_0+48 + 46,000,000 because enc0's plane +# arena is 45,219,840 bytes; dec1's param_0+48 is a different, much smaller +# allocation (E25 only ever writes 8*ex*ey*4 = 7,536,640 bytes of it at +# 640x368), and 46,000,000 past either param_0+8 or param_0+48 faults with +# "page not present". Offset 0 is safe because the entry reads param_0+8 only +# in the prologue -- s67-s324, before the cut at line 1486 -- so a store at any +# stage line is past this kernel's own last read of it, and the bridge dumps +# every argument right after the launch that produced it, so the payload is +# captured before anything else can overwrite it. +DEBUG_BASE = 0 +DEBUG_GRID_X = 81 # ctaid.y * 81 + ctaid.x, one slot per block +DEBUG_MAX_BLOCK = 64 +DEBUG_SLOT_FLOOR = 8192 # 32 lanes x 64 registers x 4 bytes + + +def debug_slot(nregs): + """Bytes per block: 32 lanes x nregs x 4, at least the floor, a power of two + so the splice's shift can form block * slot.""" + want = max(DEBUG_SLOT_FLOOR, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +def debug_block(regs): + """PTX storing REGS (one u32 each) to plane arena + DEBUG_BASE + + block*slot + lane*len(regs)*4. make_ptx.py's debug branch inserts it into + NVIDIA's own body; rrswin_dec1.hip's debug_store() writes the same bytes.""" + slot = debug_slot(len(regs)) + stores = "\n".join( + "@%%pdbg1 st.global.v4.u32 [%%rddbg3+%d], {%s};" + % (i * 16, ", ".join(regs[i * 4:i * 4 + 4])) + for i in range((len(regs) + 3) // 4)) + return f"""// d4r debug stage +{{ +.reg .pred %pdbg<2>; +.reg .b32 %rdbg<8>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [cuda_dldn_engine_swin_dec1_kernel_param_0+8]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mad.lo.s32 %rdbg3, %rdbg2, {DEBUG_GRID_X}, %rdbg1; +setp.lt.u32 %pdbg1, %rdbg3, {DEBUG_MAX_BLOCK}; +shl.b32 %rdbg4, %rdbg3, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg7, %rdbg6, {DEBUG_BASE}; +cvt.u64.u32 %rddbg2, %rdbg7; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +# a1: phase 1's staged input -- the 36 A registers and the sixteen bias seeds, at +# the cut line itself, before the region has run. +A1_REGS = A_REGS + C_REGS + +# p1: phase 1's 144 mma D pairs in mma order (statements s403..s546); the last mma's +# fourth line is 2490. +P1_REGS = [ + "%r652", "%r653", "%r662", "%r663", + "%r672", "%r673", "%r682", "%r683", + "%r692", "%r693", "%r702", "%r703", + "%r712", "%r713", "%r722", "%r723", + "%r732", "%r733", "%r742", "%r743", + "%r752", "%r753", "%r762", "%r763", + "%r772", "%r773", "%r782", "%r783", + "%r792", "%r793", "%r802", "%r803", + "%r812", "%r813", "%r822", "%r823", + "%r832", "%r833", "%r842", "%r843", + "%r852", "%r853", "%r862", "%r863", + "%r872", "%r873", "%r882", "%r883", + "%r892", "%r893", "%r902", "%r903", + "%r912", "%r913", "%r922", "%r923", + "%r932", "%r933", "%r942", "%r943", + "%r952", "%r953", "%r962", "%r963", + "%r972", "%r973", "%r982", "%r983", + "%r992", "%r993", "%r1002", "%r1003", + "%r1012", "%r1013", "%r1022", "%r1023", + "%r1032", "%r1033", "%r1042", "%r1043", + "%r1052", "%r1053", "%r1062", "%r1063", + "%r1072", "%r1073", "%r1082", "%r1083", + "%r1092", "%r1093", "%r1102", "%r1103", + "%r1112", "%r1113", "%r1122", "%r1123", + "%r1132", "%r1133", "%r1142", "%r1143", + "%r1152", "%r1153", "%r1162", "%r1163", + "%r1172", "%r1173", "%r1182", "%r1183", + "%r1192", "%r1193", "%r1202", "%r1203", + "%r1212", "%r1213", "%r1222", "%r1223", + "%r1232", "%r1233", "%r1242", "%r1243", + "%r1252", "%r1253", "%r1262", "%r1263", + "%r1272", "%r1273", "%r1282", "%r1283", + "%r1292", "%r1293", "%r1302", "%r1303", + "%r1312", "%r1313", "%r1322", "%r1323", + "%r1332", "%r1333", "%r1342", "%r1343", + "%r1352", "%r1353", "%r1362", "%r1363", + "%r1372", "%r1373", "%r1382", "%r1383", + "%r1392", "%r1393", "%r1402", "%r1403", + "%r1412", "%r1413", "%r1422", "%r1423", + "%r1432", "%r1433", "%r1442", "%r1443", + "%r1452", "%r1453", "%r1462", "%r1463", + "%r1472", "%r1473", "%r1482", "%r1483", + "%r1492", "%r1493", "%r1502", "%r1503", + "%r1512", "%r1513", "%r1522", "%r1523", + "%r1532", "%r1533", "%r1542", "%r1543", + "%r1552", "%r1553", "%r1562", "%r1563", + "%r1572", "%r1573", "%r1582", "%r1583", + "%r1592", "%r1593", "%r1602", "%r1603", + "%r1612", "%r1613", "%r1622", "%r1623", + "%r1632", "%r1633", "%r1642", "%r1643", + "%r1652", "%r1653", "%r1662", "%r1663", + "%r1672", "%r1673", "%r1682", "%r1683", + "%r1692", "%r1693", "%r1702", "%r1703", + "%r1712", "%r1713", "%r1722", "%r1723", + "%r1732", "%r1733", "%r1742", "%r1743", + "%r1752", "%r1753", "%r1762", "%r1763", + "%r1772", "%r1773", "%r1782", "%r1783", + "%r1792", "%r1793", "%r1802", "%r1803", + "%r1812", "%r1813", "%r1822", "%r1823", + "%r1832", "%r1833", "%r1842", "%r1843", + "%r1852", "%r1853", "%r1862", "%r1863", + "%r1872", "%r1873", "%r1882", "%r1883", + "%r1892", "%r1893", "%r1902", "%r1903", + "%r1912", "%r1913", "%r1922", "%r1923", + "%r1932", "%r1933", "%r1942", "%r1943", + "%r1952", "%r1953", "%r1962", "%r1963", + "%r1972", "%r1973", "%r1982", "%r1983", + "%r1992", "%r1993", "%r2002", "%r2003", + "%r2012", "%r2013", "%r2022", "%r2023", + "%r2032", "%r2033", "%r2042", "%r2043", + "%r2052", "%r2053", "%r2062", "%r2063", + "%r2072", "%r2073", "%r2082", "%r2083", +] + + +def stages(): + """Oracle stage table: name -> (line after which the store block goes, registers). + + The names carry a `d1` prefix on purpose. make_ptx.py's swin_debug() falls + back from a `(layer, stage)` key to the bare `stage` name when it serves a + layer that has no kernels/rr/swin__debug_stages.py, and enc0's + unkeyed table already owns "a", "p1".."p7", "p5o", "e5", "e5a", "e6" -- a + dec1 stage called "p1" would silently resolve to enc0's line 4128. Keeping + the debug stages in this module (rather than in a *_debug_stages.py that + would hand the splice to the shared block) also keeps the payload in the + param_0+8 buffer: the shared swin_debug_block() hardcodes param_0+48, which + is dec1's *output* plane and is rewritten in full by E25 after every stage + line.""" + return { + "d1a": (1485, A1_REGS), + "d1p": (2490, P1_REGS), + } + + # d1probe is not a stage: it is consumed by recipe() below, which splices + # probe_block() instead of debug_block(). + return { + "d1a": (1485, A1_REGS), + "d1p": (2490, P1_REGS), + } + + +def probe_block(regs): + """The magic word and the low 32 bits of every `param_0+k` pointer, stored at + `param_0+48 + 0`, spliced at the end of the entry. + + Two measured facts force this shape. (a) The launch dump names each argument + `base+` but never says where inside the dumped block a given + `param_0+k` pointer lands, so that offset has to be measured, not assumed. + (b) `param_0+8` is *not* a usable payload buffer for dec1: a 68-byte store + there at line 1485 kills the run with `HW Exception ... GPU Hang` (measured; + build /tmp/d4r-dec1/orc-probe, log /tmp/d4r-rr-perf/d1-probe2), which is why + the older `d1p` oracle stage hangs too. `param_0+48` is the arena E25 itself + writes, so it is mapped writable, and splicing at the end of the entry keeps + E25's stores from overwriting the probe. + + Stored word 0 is 111, word 9 is 222 and word 15 is 333, so the signature is + unambiguous against ambient buffer content. + """ + assert len(regs) == 1 + return """// d4r pointer probe +{ +.reg .b32 %rp<20>; +.reg .b64 %rq<32>; +ld.param.u64 %rq1, [cuda_dldn_engine_swin_dec1_kernel_param_0+0]; +ld.param.u64 %rq2, [cuda_dldn_engine_swin_dec1_kernel_param_0+8]; +ld.param.u64 %rq3, [cuda_dldn_engine_swin_dec1_kernel_param_0+24]; +ld.param.u64 %rq4, [cuda_dldn_engine_swin_dec1_kernel_param_0+40]; +ld.param.u64 %rq5, [cuda_dldn_engine_swin_dec1_kernel_param_0+48]; +ld.param.u64 %rq6, [cuda_dldn_engine_swin_dec1_kernel_param_0+80]; +ld.param.u64 %rq7, [cuda_dldn_engine_swin_dec1_kernel_param_0+88]; +ld.param.u64 %rq8, [cuda_dldn_engine_swin_dec1_kernel_param_0+96]; +ld.param.u64 %rq9, [cuda_dldn_engine_swin_dec1_kernel_param_0+104]; +ld.param.u64 %rq10, [cuda_dldn_engine_swin_dec1_kernel_param_0+112]; +ld.param.u64 %rq11, [cuda_dldn_engine_swin_dec1_kernel_param_0+120]; +ld.param.u64 %rq12, [cuda_dldn_engine_swin_dec1_kernel_param_0+128]; +cvta.to.global.u64 %rq29, %rq5; +cvta.to.global.u64 %rq17, %rq1; +cvta.to.global.u64 %rq18, %rq3; +cvta.to.global.u64 %rq19, %rq4; +cvta.to.global.u64 %rq20, %rq5; +cvta.to.global.u64 %rq21, %rq6; +cvta.to.global.u64 %rq22, %rq7; +cvta.to.global.u64 %rq23, %rq8; +cvta.to.global.u64 %rq24, %rq9; +cvta.to.global.u64 %rq25, %rq10; +cvta.to.global.u64 %rq26, %rq11; +cvta.to.global.u64 %rq27, %rq12; +mov.u32 %rp1, 111; +cvt.u32.u64 %rp2, %rq17; +cvt.u32.u64 %rp3, %rq29; +cvt.u32.u64 %rp4, %rq18; +cvt.u32.u64 %rp5, %rq19; +cvt.u32.u64 %rp6, %rq20; +cvt.u32.u64 %rp7, %rq21; +cvt.u32.u64 %rp8, %rq22; +cvt.u32.u64 %rp10, %rq23; +cvt.u32.u64 %rp11, %rq24; +cvt.u32.u64 %rp12, %rq25; +cvt.u32.u64 %rp13, %rq26; +cvt.u32.u64 %rp14, %rq27; +mov.u32 %rp9, 222; +mov.u32 %rp15, 333; +mov.u32 %rp16, %r2195; +mov.u32 %rp17, %r2196; +st.global.u32 [%rq29], %rp1; +st.global.u32 [%rq29+4], %rp2; +st.global.u32 [%rq29+8], %rp3; +st.global.u32 [%rq29+12], %rp4; +st.global.u32 [%rq29+16], %rp5; +st.global.u32 [%rq29+20], %rp6; +st.global.u32 [%rq29+24], %rp7; +st.global.u32 [%rq29+28], %rp8; +st.global.u32 [%rq29+32], %rp9; +st.global.u32 [%rq29+36], %rp10; +st.global.u32 [%rq29+40], %rp11; +st.global.u32 [%rq29+44], %rp12; +st.global.u32 [%rq29+48], %rp13; +st.global.u32 [%rq29+52], %rp14; +st.global.u32 [%rq29+56], %rp15; +st.global.u32 [%rq29+60], %rp16; +st.global.u32 [%rq29+64], %rp17; +} +""" + + +def cut_call(): + """The PTX that replaces the mma region.""" + args = A_REGS + C_REGS + decl = "\n".join("\t.param .b32 p%d;" % i for i in range(len(args))) + store = "\n".join("\tst.param.b32 [p%d+0], %s;" % (i, r) + for i, r in enumerate(args)) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store += (f"\n\tst.param.b64 [pw+0], {W_REG};" + f"\n\tst.param.b64 [pv+0], {V_REG};" + f"\n\tmov.u32 %rswin0, {SCRATCH};" + "\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join(["p%d" % i for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join("\tld.shared.b32 %s, [%%rswin1+%d];" % (r, 4 * i) + for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store} +\tcall.uni {CALLEE}, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {RET_STRIDE}, %rswin0; +{gets} +}}""" + + +def extern(): + """The .extern .func declaration of the callee, matching cut_call()'s arguments.""" + args = ", ".join([".param .b32 d4r_a%d" % i + for i in range(len(A_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func {CALLEE}\n(\n\t{args}\n)\n;\n" + + +def recipe(): + """make_ptx.py's recipe for this kernel.""" + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + if stage: + if stage == "d1probe": + # D4R_RRSWIN_DEBUG=d1probe: measure where each `param_0+k` pointer + # lands inside the block the launch dump writes, so every later stage + # extracts its payload at a measured offset instead of an assumed one. + # NOTE: make_ptx.py rejects any debug line that is not a phase's last + # mma ("debug line N is not phase 1's last mma"), so the probe cannot be + # spliced past the last mma at line 38472. Splicing at 38472 instead + # would be after every store, which is what this probe wants. + # (First attempt, with the probe at param_0+8 + 0 / line 1485: run exit + # 137, "Killed" by the 240 s harness timeout -- GPU hang.) + return dict(file=MODULE, debug=(38472, [A_REGS[0]]), debug_block=probe_block) + s = stages().get(stage) + if s is None: + if stage == "none": + # D4R_RRSWIN_DEBUG=none: NVIDIA's own body, unedited -- the + # baseline the cut and the debug stages are measured against. + return dict(file=MODULE) + raise SystemExit(f"swin_dec1_recipe: no debug stage {stage!r}") + return dict(file=MODULE, debug=s, debug_block=debug_block) + return dict(file=MODULE, cut_call=CUT_CALL, call=cut_call(), extern=extern()) diff --git a/kernels/rr/swin_dec2_debug_stages.py b/kernels/rr/swin_dec2_debug_stages.py new file mode 100755 index 0000000..97121e2 --- /dev/null +++ b/kernels/rr/swin_dec2_debug_stages.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python3 +"""Oracle debug stages for cuda_dldn_engine_swin_dec2_kernel. + +make_ptx.py loads this module and keys its stages() by (layer, stage), so these +names do not collide with enc0's unkeyed table. Each entry is +(line after which the store block goes, the registers to store); the store block +itself is make_ptx.py's shared swin_debug_block(), which writes to param_0+48 + +D4R_RRSWIN_DEBUG_BASE + block*slot + lane*n*4 with block = ctaid.y*161 + ctaid.x +below 64. rrswin_dec2.hip's debug_store() writes the same bytes from its own +values, so the two launch dumps compare byte for byte. + +**Why every stage splices after E37 (line 36892).** dec2's plane arena is a +5,652,480-byte window at byte 60,293,120 of the 65,945,600-byte block the bridge +dumps as arg048's allocation (measured from a D4R_CUDA_REPLAY_DUMP capture: +`pointer 48 0 60293120`). E37 -- the 12 `st.global.u32` plane-arena scatters -- +rewrites essentially all of it: diffing a pre-launch replay capture against the +post-launch reference dump shows 5,564,929 of 5,652,480 arena bytes changed. A +splice placed next to a phase's mma is therefore erased before the dump. Line +36892 is the `;` of phase 38's last mma, i.e. after E37 and before E38 (which +never touches param_0+48), so the payload survives. + +The accumulators are intact at line 36892: a last-definition scan over the whole +entry shows every phase-n D register is written for the last time before line +33,227, and never rewritten after. + +make_ptx.py additionally requires the first stored register to appear in the 4000 +lines before the splice point. Phases 2..28 name registers the late window never +mentions, so those lists start with %r19329 -- phase 38's C bias seed, a +weight-image load the native body reproduces trivially -- and the phase's own +accumulators follow. + +The lists are generated from the corpus PTX rather than written out, so they +follow the corpus: each phase's mma run in statement order, contributing its D +pair. +""" + +import os +import re +import sys + +_HERE = os.path.dirname(os.path.abspath(__file__)) +_CORPUS = os.environ.get("D4R_DLSSD_PTX_DIR", os.path.expanduser("~/.cache/d4r-rr-corpus")) +_PTX = os.path.join(_CORPUS, "0021-PREPASS_ENTRYPOINT_NAME.ptx") + +# the line the store block follows: phase 38's last mma +SPLICE_LINE = 36892 +# phase 38's first C bias seed: live at the splice point and inside make_ptx's window +SENTINEL = "%r19329" + +RE_ENTRY = re.compile(r"\.entry\s+cuda_dldn_engine_swin_dec2_kernel\s*\(") +RE_MMA = re.compile(r"mma\.sync[^(]*\{([^}]*)\}") + + +def _entry_lines(): + lines = open(_PTX).read().split("\n") + next(i for i, l in enumerate(lines) if RE_ENTRY.search(l)) + return lines + + +def _mma_runs(): + """Per phase (1-based), that phase's D registers in mma statement order.""" + sys.path.insert(0, _HERE) + import rr_layer_spec as R + lines = open(_PTX).read().split("\n") + body = next((a, b) for n, a, b in R.find_entries(lines) + if n == "cuda_dldn_engine_swin_dec2_kernel") + stmts, _ = R.linearise(lines, *body) + runs, prev = [], False + for s in stmts: + if not s.is_mma: + prev = False + continue + if not prev: + runs.append([]) + runs[-1].extend(x.strip() for x in RE_MMA.match(s.text).group(1).split(",")) + prev = True + return runs + + +def stages(): + """name -> (line after which the store block goes, registers).""" + window = "\n".join(_entry_lines()[SPLICE_LINE - 4000:SPLICE_LINE]) + # swin_debug_block() emits v4 stores, so a list whose length is not a multiple + # of four would produce a short vector and fail PTX translation; pad with the + # sentinel, which both sides store identically. + out = {} + for phase, regs in enumerate(_mma_runs(), start=1): + # make_ptx.py's own check: the first stored register must appear in the window + lead = [] if regs[0] in window else [SENTINEL] + full = lead + regs + full += [SENTINEL] * (-len(full) % 4) + out["p%d" % phase] = (SPLICE_LINE, full) + return out \ No newline at end of file diff --git a/kernels/rr/swin_dec2_recipe.py b/kernels/rr/swin_dec2_recipe.py new file mode 100644 index 0000000..2b454aa --- /dev/null +++ b/kernels/rr/swin_dec2_recipe.py @@ -0,0 +1,130 @@ +#!/usr/bin/env python3 +"""Splice recipe for cuda_dldn_engine_swin_dec2_kernel (nvngx_dlssd.dll 310.7). + +kernels/tex/make_ptx.py's per-layer hook imports this module by path and returns +`recipe()`. Everything here is self-contained: nothing is imported from +make_ptx.py or rr_layer_spec.py. + +The cut replaces the whole 38-phase mma region of the entry -- physical lines +1535-36889 of ~/.cache/d4r-rr-corpus/0021-PREPASS_ENTRYPOINT_NAME.ptx, statement +range s452-s15510, 726 mma -- with one `call.uni d4r_swin_dec2`. NVIDIA's +prologue (lines 1-1534: the 60 plane-arena loads that stage phase 1's twelve A +fragments, its 24 weight-fragment loads and its twelve bias seeds, all with the +per-tid.z strides 12288 and 192) and its final epilogue (line 36893 to the end: +the plane-arena guards, the shared staging of phase 38's four accumulators, the +row max, the softmax, the 3x3 colour gather, the two integer-coordinate texture +reads at param_0+96/+104 and the surface store to param_0+112) stay in PTX. + +Everything between -- all 38 phases and all 37 epilogues -- is the native body's +job. Only four registers cross back into PTX (rr_layer_spec.py's live_across on +s452-s15510): phase 38's four D halves %r19360 %r19361 %r19370 %r19371. + +The callee is handed, in this order: + + * the 48 A registers of phase 1 (twelve .f16.e4m3 fragments of four b32, in + the order the 144 mma first use them: m-tile 0's four k-slices, then m-tile + 1's, then m-tile 2's), + * the twelve C bias seeds phase 1 reads from the weight image at + +49152..+49328 (every other mma's C operand is another mma's D register, + which the body computes itself, so no other C register is passed), + * the weight image pointer (%rd32, the `cvta.to.global` of param_0+40), + * the parameter block pointer (%rd7, param_0 itself), + * the address of the entry's 9600-byte .shared array. + +`call.uni` return values cannot come back to PTX (ZLUDA lowers them to an LLVM +return type with no .param-space object), so the four accumulators cross the cut +through the shared scratch, 16 bytes per lane, as dec1's do. + +Phase 1's geometry, read off the mma list and NOT off rr_layer_spec.py's M/N +columns (those count the four k-slices of each fragment as four m-tiles and four +n-tiles, so they print 192x384 for what is a 48x96x128 GEMM): + + * twelve A fragments = 3 m-tiles of 16 rows x 4 k-slices of 32 k, + * forty-eight B fragments = 12 n-tiles of 8 columns x 4 k-slices, + * 144 mma = 3 m-tiles x 12 n-tiles x 4 k-steps, in 36 chains of four, so + M = 48, N = 96, K = 128 and 3*12*4 = 144. + +D4R_RRSWIN_DEBUG= is handled before this module is consulted: make_ptx.py's +swin_debug() finds the stage in kernels/rr/swin_dec2_debug_stages.py (which this +module's A_REGS/C_REGS and phase 1's mma order generate) and keeps NVIDIA's whole +body with that stage's registers stored into the plane arena, which +kernels/rr/rrswin_dec2.hip reproduces with -DD4R_RRSWIN_DEBUG_STAGE=. +""" + +MODULE = "0021-PREPASS_ENTRYPOINT_NAME.ptx" +CALLEE = "d4r_swin_dec2" + +# the mma region: the first mma's first physical line, and the line after the last +# mma's last physical line +CUT_CALL = (1535, 36893) + +# phase 1's A fragments, in the order the 144 mma first use them (the first mma +# reads %r1040..%r1043; s595 reads %r2060..%r2063) +A_REGS = [ + "%r1040", "%r1041", "%r1042", "%r1043", + "%r1060", "%r1061", "%r1062", "%r1063", + "%r1080", "%r1081", "%r1082", "%r1083", + "%r1100", "%r1101", "%r1102", "%r1103", + "%r1520", "%r1521", "%r1522", "%r1523", + "%r1540", "%r1541", "%r1542", "%r1543", + "%r1560", "%r1561", "%r1562", "%r1563", + "%r1580", "%r1581", "%r1582", "%r1583", + "%r2000", "%r2001", "%r2002", "%r2003", + "%r2020", "%r2021", "%r2022", "%r2023", + "%r2040", "%r2041", "%r2042", "%r2043", + "%r2060", "%r2061", "%r2062", "%r2063",] + +# phase 1's twelve bias seeds, in weight-image offset order (+49152, +49168, ...) +C_REGS = [ + "%r1597", "%r1607", "%r1677", "%r1687", + "%r1757", "%r1767", "%r1837", "%r1847", + "%r1917", "%r1927", "%r1997", "%r2007", +] + +# what the epilogue reads back out of the deleted region: phase 38's four D halves +RET_REGS = ["%r19360", "%r19361", "%r19370", "%r19371"] +RET_STRIDE = 4 * len(RET_REGS) + +SCRATCH = "_ZZ33cuda_dldn_engine_swin_dec2_kernel33DldnEngineSwinEncParamsStructBaseE4smem" + +# registers the splice reads: %rd32 is the globalised weight image (s8), %rd7 is +# param_0 itself (s1) +W_REG = "%rd32" +V_REG = "%rd7" + + +def cut_call(): + """The PTX that replaces the mma region.""" + args = A_REGS + C_REGS + decl = "\n".join("\t.param .b32 p%d;" % i for i in range(len(args))) + store = "\n".join("\tst.param.b32 [p%d+0], %s;" % (i, r) + for i, r in enumerate(args)) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store += (f"\n\tst.param.b64 [pw+0], {W_REG};" + f"\n\tst.param.b64 [pv+0], {V_REG};" + f"\n\tmov.u32 %rswin0, {SCRATCH};" + "\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join(["p%d" % i for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join("\tld.shared.b32 %s, [%%rswin1+%d];" % (r, 4 * i) + for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store} +\tcall.uni {CALLEE}, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {RET_STRIDE}, %rswin0; +{gets} +}}""" + + +def extern(): + """The .extern .func declaration of the callee, matching cut_call()'s arguments.""" + args = ", ".join([".param .b32 d4r_a%d" % i + for i in range(len(A_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func {CALLEE}\n(\n\t{args}\n)\n;\n" + + +def recipe(): + """make_ptx.py's recipe for this kernel.""" + return dict(file=MODULE, cut_call=CUT_CALL, call=cut_call(), extern=extern()) diff --git a/kernels/rr/swin_dec3_recipe.py b/kernels/rr/swin_dec3_recipe.py new file mode 100755 index 0000000..7fdb64b --- /dev/null +++ b/kernels/rr/swin_dec3_recipe.py @@ -0,0 +1,243 @@ +#!/usr/bin/env python3 +"""Splice recipe for cuda_dldn_engine_swin_dec3_kernel (Ray Reconstruction denoiser, decoder 3). + +`kernels/tex/make_ptx.py` imports this module by path and calls `recipe()` whenever the +kernel name matches, so the layer owns its own splice and make_ptx.py stays untouched. + +What the recipe produces + * `cut_call` = (1658, 46566): the file lines of the mma region. Line 1658 is the + first `mma.sync` (statement s543) and line 46565 is the `;` of the last one + (s19381), so everything outside is NVIDIA's texture prologue and the surface + epilogue of E48. + * `extern`: the `.extern .func` declaration of the callee `d4r_swin_dec3`. + * `call`: the block spliced in place of the cut. It hands the callee the staged + A fragments, phase 1's sixteen bias seeds, the weight image, the parameter block + and the base of the shared scratch, then reads the accumulators back. + +Everything below was read out of `~/.cache/d4r-rr-corpus/0020-PREPASS_ENTRYPOINT_NAME.ptx` +by `kernels/rr/rr_layer_spec.py dec3` and by hand; each block says where its numbers +come from. + +Set D4R_RRSWIN_DEBUG_DEC3= to build the *oracle* instead of the cut: NVIDIA's +whole body with a store of that stage's registers spliced into the plane arena at ++46,000,000 (the region the kernel never writes), which `rrswin_dec3.hip`'s +-D4R_RRSWIN_DEBUG_STAGE= reproduces from its own registers. +""" + +import os + +# --------------------------------------------------------------------------- +# The cut. File lines, not statement indices: make_ptx.py slices `lines` with these. +# rr_layer_spec.py dec3 prints "cut s543-s19381 (file lines 1658-46562)"; the last mma +# is a four-line instruction, so its `;` -- the line the region ends on -- is 46565. +# --------------------------------------------------------------------------- +CUT_FIRST = 1658 +CUT_LAST = 46566 + +KERNEL = "cuda_dldn_engine_swin_dec3_kernel" +PARAM = KERNEL + "_param_0" +# the entry's only shared array (declared at file line 1027, 12800 bytes) +SMEM = "_ZZ33cuda_dldn_engine_swin_dec3_kernel33DldnEngineSwinEncParamsStructBaseE4smem" + +# --------------------------------------------------------------------------- +# Live-in registers. +# +# A in (60 b32 = 15 fragments of four): the staged block input the prologue gathered +# with `ld.global.u32` at s67, s109, s127, s145, s163, s200, s237, s255, s273, s291, +# s328, s365, s383, s401, s419 -- fifteen 16-row x 32-k e4m3 fragments. Listed in the +# order the mma read them (fragment f is %r+0..3, ascending, which for dec3 is +# also the numerical order the tool prints). +# --------------------------------------------------------------------------- +A_BASES = [1556, 1576, 1596, 1616, 1636, # m-block 0, k-slices 0..4 + 2356, 2376, 2396, 2416, 2436, # m-block 1 + 3156, 3176, 3196, 3216, 3236] # m-block 2 +A_REGS = ["%%r%d" % (b + o) for b in A_BASES for o in range(4)] + +# C in: the sixteen bias seeds, the only C operands of the region that come from +# outside it (the other 384 are D registers of an earlier mma of phase 1 itself). +# They are the sixteen `ld.global.u32` at file lines 1633-1648, reading +# W + z*256 + ((laneid<<2)&12) + 81920 + 16*i; the callee reads the same words +# itself from the weight image, so they are passed for the record only. +C_REGS = ["%%r%d" % r for r in (2453, 2463, 2553, 2563, 2653, 2663, 2753, 2763, + 2853, 2863, 2953, 2963, 3053, 3063, 3153, 3163)] + +# --------------------------------------------------------------------------- +# Live-out registers: written inside the cut, read by E48 after it. rr_layer_spec.py +# prints four of them; a corrected destination scan finds six, because an mma writes a +# brace group and `dest_regs` truncates at the first comma inside it: +# %r26071/%r26072 phase 48's mma #7 D (row g, row g+8), read at 46581/46600 +# %r26081/%r26082 phase 48's mma #8 D, read at 46586/46603 +# %r26210 the shared array's base, read at 46580 +# %r26211 %tid.z << 4, read at 46575 +# %r26212 (the %tid.z they come from) and %r26073/%r26083 are dead after the cut, so +# the splice re-materialises the first two instead of paying for four parameters. +# --------------------------------------------------------------------------- +RET_REGS = ["%r26071", "%r26072", "%r26081", "%r26082"] +RET_STRIDE = 4 * len(RET_REGS) + +# --------------------------------------------------------------------------- +# Oracle debug stages: name -> (file line the store block goes after, registers). +# +# A stage is reproducible from its tuple alone: make_ptx.py's swin_debug_block writes +# the registers to arena + 46,000,000 + block*slot + lane*len*4, and rrswin_dec3.hip's +# debug_store writes the same registers of its own phase in the same order. Only the +# last k-step of each phase's chains carries a value into the epilogue, so those are the +# stages; operand stages (the A fragments and C seeds as the mma reads them) fix the +# fragment order independently of the arithmetic. +# --------------------------------------------------------------------------- +# phase 1: the 48 chain finals (n-tile pair per group, m-tile major, group minor), +# each the (row g, row g+8) pair the mma writes. +PHASE1_FINALS = sum((["%%r%d" % (844 + 100 * g + 80 + 10 * c), "%%r%d" % (845 + 100 * g + 80 + 10 * c)] + for g in range(24) for c in range(2)), []) + +DEBUG_STAGES = { + # phase 1's 48 accumulators (the last k-step of every chain) + "p1": (3334, PHASE1_FINALS), + # phase 1's A fragments and C seeds as the mma reads them: 60 + 16 registers + "a": (1657, A_REGS + C_REGS), +} + +# 32 lanes x 8 bytes per wave-pair; blockDim is (32, 1, 4), so the debug slot is keyed +# by (ctaid.y, ctaid.x, tid.z) without needing the grid's extent. +DEBUG_WAVES = 4 +DEBUG_BLOCKS_X = 8 # ctaid.x < 8 +DEBUG_BLOCKS_Y = 2 # ctaid.y < 2 -> 8*2*4 = 64 slots, one per block/wave pair +# dec3's plane arena is the tail of a 65,945,600-byte scratch block that all eleven +# denoiser layers share: dec3's arg048 sits at block offset 35,799,040, so the arena +# is [35,799,040, 65,945,600) and the family default of 46,000,000 lands outside the +# block entirely -- the dump of arg008 would never see the payload. A payload must +# also clear every other layer's sub-buffer inside the arena, because a stage store +# that overlaps one corrupts the frame. D4R_CUDA_REPLAY_DUMP_FILTER=swin_ manifests +# for all eleven launches record the block offsets in use: 0, 30146560, 35799040, +# 36387840, 36535040, 37683200, 39567360, 45219840, 60293120. dec3's own inputs are +# 37683200 (param+24, the skip image) and 39567360 (param+8, the e4m3 features), and +# dec3 itself writes only the first 8*ex*ey = 8*160*92 words = 471,040 bytes of its +# arena (E47's scatter). Nothing is placed above 60293120, so the tail is the only +# region large enough for 64 slots x 32 KiB. +# D4R_RRSWIN_DEBUG_BASE steers it, exactly as it steers make_ptx.py's +# swin_debug_block; the default is the tail described above. A native build must be +# given the same value (-DD4R_RRSWIN_DEBUG_BASE= in D4R_TEX_CFLAGS), because that +# side bakes the constant into debug_store(). +DEBUG_BASE = int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", 27000000)) +DEBUG_ARENA_BYTES = 65945600 - 35799040 +DEBUG_MIN_SLOT = 8192 +if DEBUG_BASE + DEBUG_BLOCKS_X * DEBUG_BLOCKS_Y * DEBUG_WAVES * 32768 >= DEBUG_ARENA_BYTES: + raise SystemExit("swin_dec3_recipe: the debug payload does not fit dec3's plane arena") + + +def debug_slot(nregs): + """Per-block-slot bytes: 32 lanes x NREGS x 4, at least DEBUG_MIN_SLOT, a power of two.""" + want = max(DEBUG_MIN_SLOT, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +def debug_block(regs): + """PTX storing REGS (u32 each) into the plane arena, one slot per (block, wave). + + Same shape as make_ptx.py's swin_debug_block, but keyed by (ctaid.y, ctaid.x, tid.z) + instead of enc0's flat block index: dec3's block is four waves deep (blockDim.z = 4, + %tid.z is the slab index the prologue scales its loads by), so a flat index would have + the four waves of one block overwrite each other. + """ + n = len(regs) + slot = debug_slot(n) + stores = "\n".join( + f"@%pdbg1 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(regs[i * 4:i * 4 + 4])}}};" + for i in range((n + 3) // 4)) + return f"""// d4r debug stage (swin_dec3_recipe.py) +{{ +.reg .pred %pdbg<4>; +.reg .b32 %rdbg<10>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{PARAM}+48]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mov.u32 %rdbg3, %tid.z; +setp.lt.u32 %pdbg1, %rdbg1, {DEBUG_BLOCKS_X}; +setp.lt.u32 %pdbg2, %rdbg2, {DEBUG_BLOCKS_Y}; +setp.lt.u32 %pdbg3, %rdbg3, {DEBUG_WAVES}; +and.pred %pdbg1, %pdbg1, %pdbg2; +and.pred %pdbg1, %pdbg1, %pdbg3; +mad.lo.s32 %rdbg4, %rdbg2, {DEBUG_BLOCKS_X}, %rdbg1; +mad.lo.s32 %rdbg4, %rdbg4, {DEBUG_WAVES}, %rdbg3; +shl.b32 %rdbg5, %rdbg4, {slot.bit_length() - 1}; +mov.u32 %rdbg6, %laneid; +mad.lo.s32 %rdbg7, %rdbg6, {n * 4}, %rdbg5; +add.s32 %rdbg8, %rdbg7, {DEBUG_BASE}; +cvt.u64.u32 %rddbg2, %rdbg8; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +def extern(): + """The `.extern .func` declaration of the callee: A registers, C registers, the weight + image, the parameter block and the shared scratch, in that order.""" + args = ", ".join([f".param .b32 d4r_p{i}" for i in range(len(A_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func d4r_swin_dec3\n(\n\t{args}\n)\n;\n" + + +def call(): + """The block spliced in place of the cut. + + The parameter space of `call.uni` is built explicitly (ZLUDA lowers the arguments as + PTX parameter-space objects, not as an LLVM argument list), the weight image is + materialised here from the parameter block so the callee gets a global pointer, and + the four live-out accumulators come back through the shared scratch: ZLUDA turns a + multi-value C++ return into LLVM's function return type, so there is no callee-side + .param-space object to read them from. + + %r26210 (the shared base) and %r26211 (%tid.z << 4) are re-materialised rather than + handed back -- the epilogue's own code at 46481/46480 shows exactly what they are. + """ + args = A_REGS + C_REGS + decl = "\n".join(f"\t.param .b32 p{i};" for i in range(len(args))) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store = "\n".join(f"\tst.param.b32 [p{i}+0], {r};" for i, r in enumerate(args)) + store += ("\n\tst.param.b64 [pw+0], %rd4;\n\tst.param.b64 [pv+0], %rd2;" + "\n\tst.param.b32 [ps+0], %r26210;") + hel = ", ".join([f"p{i}" for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join(f"\tld.shared.b32 {r}, [%r681+{4 * i}];" + for i, r in enumerate(RET_REGS)) + return f"""{{ +{decl} + mov.b64 %rd2, {PARAM}; + ld.param.u64 %rd3, [%rd2+40]; + cvta.to.global.u64 %rd4, %rd3; + mov.u32 %r26210, {SMEM}; +{store} + call.uni d4r_swin_dec3, ({hel}); + mov.u32 %r26212, %tid.z; + shl.b32 %r26211, %r26212, 4; + mov.u32 %r681, %r26210; + mad.lo.s32 %r681, %laneid, {RET_STRIDE}, %r681; +{gets} +}}""" + + +def recipe(): + """The dict make_ptx.py consumes. D4R_RRSWIN_DEBUG_DEC3 builds the oracle instead.""" + stage = os.environ.get("D4R_RRSWIN_DEBUG_DEC3", "") + if stage: + if stage not in DEBUG_STAGES: + raise SystemExit(f"swin_dec3_recipe: unknown debug stage {stage!r}; " + f"have {', '.join(sorted(DEBUG_STAGES))}") + after, regs = DEBUG_STAGES[stage] + return dict(file="0020-PREPASS_ENTRYPOINT_NAME.ptx", debug=(after, regs), + debug_block=debug_block) + return dict(file="0020-PREPASS_ENTRYPOINT_NAME.ptx", cut_call=(CUT_FIRST, CUT_LAST), + extern=extern(), call=call()) + + +if __name__ == "__main__": + import sys + what = sys.argv[1] if len(sys.argv) > 1 else "recipe" + value = recipe() + if what == "recipe": + for k, v in sorted(value.items()): + print(f"== {k} ==") + print(v) + else: + print(value[what]) \ No newline at end of file diff --git a/kernels/rr/swin_dec4_debug_stages.py b/kernels/rr/swin_dec4_debug_stages.py new file mode 100755 index 0000000..a5c7cc3 --- /dev/null +++ b/kernels/rr/swin_dec4_debug_stages.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +"""Oracle debug stages for cuda_dldn_engine_swin_dec4_kernel's phase 1. + +Each stage is a (file line after which the store block goes, registers in order) tuple for +kernels/tex/make_ptx.py's SWIN_DEBUG_STAGES, so D4R_RRSWIN_DEBUG=p1 builds NVIDIA's own +body with that stage's registers stored into the plane arena, which +kernels/rr/rrswin_dec4.hip's D4R_RRSWIN_DEBUG_STAGE reproduces from its own registers. + +Phase 1 is 300 mma in sixty five-step chains: the C operand of each mma is the D pair of +the mma two statements earlier, so a chain accumulates over five k-steps and is seeded +once. A stage therefore keeps the mma whose D pair no other mma of the phase reads as its +C -- the last k-step of each chain -- and lists the sixty pairs in mma statement order, each +as the (row g, row g+8) pair its mma wrote. + +The register numbers are read out of the corpus PTX +(~/.cache/d4r-rr-corpus/0019-PREPASS_ENTRYPOINT_NAME.ptx, entry +cuda_dldn_engine_swin_dec4_kernel): statement i of the phase writes {%r(1218+10*i), +%r(1219+10*i)}, verified over all 300 mma of file lines 1707-3803. +""" + + +def stages(): + """The stage table: name -> (splice line, registers).""" + # phase 1: 300 mma, 60 output tiles, splice after file line 3803 (the last mma's `;`) + last = [(1218 + 10 * i, 1219 + 10 * i) for i in range(300) if i % 10 in (8, 9)] + return { + "p1": (3803, [f"%r{a}" for pair in last for a in pair]), + # p1a: phase 1's fifteen A fragments as the mma reads them (four b32 each), the + # sixty A registers the splice hands the callee + "p1a": (3803, [f"%r{b + o}" for b in (2130, 2150, 2170, 2190, 2210, + 3130, 3150, 3170, 3190, 3210, + 4130, 4150, 4170, 4190, 4210) + for o in range(4)]), + # p1s: phase 1's twenty bias seeds, the C operands the splice hands the callee + "p1s": (3803, [f"%r{3227 + 100 * (j // 2) + 10 * (j % 2)}" for j in range(20)]), + } diff --git a/kernels/rr/swin_dec4_recipe.py b/kernels/rr/swin_dec4_recipe.py new file mode 100755 index 0000000..042f4bb --- /dev/null +++ b/kernels/rr/swin_dec4_recipe.py @@ -0,0 +1,188 @@ +#!/usr/bin/env python3 +"""Mirror-cut splice for cuda_dldn_engine_swin_dec4_kernel (nvngx_dlssd.dll 310.7). + +dec4 is the widest of the eleven Swin layers: its attention/MLP width is 160, so +every register count below is *not* interchangeable with dec3's. Everything here is +read out of `kernels/rr/rr_layer_spec.py dec4`'s "cut ABI" section and out of the +corpus PTX itself (`~/.cache/d4r-rr-corpus/0019-PREPASS_ENTRYPOINT_NAME.ptx`, entry +`cuda_dldn_engine_swin_dec4_kernel`, which opens at file line 1016). + +The cut keeps NVIDIA's prologue (the texture/plane gathers of lines 1-1706) and its +surface epilogue (from line 58080) and replaces the 1606 `mma` of the 62 phases +(file lines 1707-58079) with one `call.uni` into `kernels/rr/rrswin_dec4.hip`. + + phase table 62 phases, 1606 mma, 24447 statements + cut s571-s24164, file lines 1707-58076 (`entry` is line 1707) + parameter block 144 bytes (arg040 = the prepared weight image, arg048 = S) + launch no .maxntid in this module; reads %tid.x, %tid.z, %ctaid.x, + %ctaid.y, %laneid; block z is eight waves + A in 60 regs = phase 1's fifteen 16-row A fragments, in the first + mma's operand order (four b32 each) + C in phase 1's twenty bias seeds, each read as a single u32 and + duplicated into both C halves of its mma + returns %r34761, %r34762, %r34771, %r34772 -- phase 62's four + accumulators, stored to `SM` past the cut (lines 58096, 58101, + 58113, 58116) and read back there for E62's softmax + weight image 534804 bytes (phase 62's second C seed at +534800) + +The accumulators cross the cut through shared memory rather than `call.uni`'s return +parameters: ZLUDA lowers a return value to the *function's* LLVM return type +(llvm_zluda/ptx/src/pass/llvm/emit.rs, emit_call), so there is no .param-space object +behind it and the callee would read 0x0 in every slot. `SM` +(`...33DldnEngineSwinEncParamsStructBaseE4smem`, 16384 bytes) is *not* dead after the +cut -- E62 reads it back at line 58152 -- so the handoff uses the top of the array, +past every offset the epilogue touches. See the offset arithmetic in `swin_cut_call`. + +`recipe()` is self-contained: it imports nothing from make_ptx.py and re-derives the +small amount of splice text it needs, so kernels/tex/make_ptx.py stays untouched by +the ten layers being written in parallel. +""" + + +def _a_regs(): + """Phase 1's fifteen A fragments, in the order the first mma lists them. + + VERIFIED against the corpus: 300 mma, 15 distinct four-b32 A fragments, and every + one of the 60 registers is defined in the prologue before file line 1707 (the cut's + first line), so the splice can read all of them. The register numbers come from + the mma statements themselves, s571-s870 / file lines 1707-3803. + """ + bases = [2130, 2150, 2170, 2190, 2210, # %r2130.., %r2150.., ... %r2210.. + 3130, 3150, 3170, 3190, 3210, # %r3130.., ... %r3210.. + 4130, 4150, 4170, 4190, 4210] # %r4130.., ... %r4210.. + return [f"%r{b + o}" for b in bases for o in range(4)] + + +def _c_regs(): + """Phase 1's twenty bias seeds, in chain-root order. + + Phase 1 is 300 mma in sixty five-step chains (the C operand of each mma is the D + pair of the mma two statements earlier, so each chain accumulates over the five + k-steps of one tile and is seeded once). The sixty roots use twenty distinct seed + registers, three chains each: `ld.global.u32 %r3227, [%rd203+102400]` and its + nineteen successors at +16 bytes (file lines 1686-1705), read at + `W + z*320 + ((laneid<<2)&12) + 102400 + 16*j`. + + Order matters: it is the order the roots appear in the mma stream, which is + %r3227, %r3237, %r3327, %r3337, ... (each pair 10 apart, each decade 100 apart). + VERIFIED by walking the chain structure of all 300 mma. + """ + return [f"%r{3227 + 100 * (j // 2) + 10 * (j % 2)}" for j in range(20)] + + +A_REGS = _a_regs() +C_REGS = _c_regs() +# The registers the surviving epilogue (file line 58080 on) reads and that the cut +# deletes the definition of. VERIFIED by walking every instruction from line 58080 to +# the `ret` and listing the registers used but never defined there: six of them, +# three mma D pairs -- +# s24177 `st.shared.u32 [%r998], %r34761` / s24178 with %r34762, +# s24181 `st.shared.u32 [%r998+16], %r34771` / s24182 with %r34772, +# s24170 `shl.b32 %r997, %r34888, 4` / s24173 `add.s32 %r998, %r34889, %r34788`. +# Leaving any of them undefined makes ZLUDA's optimizer fold the whole entry to +# `unreachable` (VERIFIED: the run then dies with HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION), +# because PTX registers are `undef` on first use, which is poison once it reaches a +# branch or a memory address. `rr_layer_spec.py dec4` names the first member of each +# pair (%r34761, %r34771, %r34888, %r34889); the partners come with them. +RET_REGS = ["%r34761", "%r34762", "%r34771", "%r34772", "%r34888", "%r34889"] + +# The shared scratch the accumulators cross the cut through. `SM` is 16384 bytes. +# +# Only two pieces of NVIDIA's code survive the cut, and both are shallow in `SM`: +# +# * the prologue (file lines 1-1706) touches shared memory exactly zero times -- its +# only mention of the array is the `.shared` declaration itself, line 1027; +# * the epilogue (from line 58080) has eleven shared accesses, all of them E62's +# five-tap staging. Its deepest is `%r34858 = SM + (%r1001*6 + %r1002*48)*4` at +# line 58151, where `%r1001 = tid.x & 7` <= 7 and `%r1002 = (z*32 + tid.x) >> 3` +# <= 32, so the last byte it can reach is (7*6 + 32*48)*4 + 16 = 6328. +# +# Everything between the two -- including the `+14848` immediates of phase 2's A-fragment +# read at line 19189 -- is deleted by the cut and replaced by this call, so those do not +# constrain the choice. The handoff therefore takes the top 32 lanes * 16 bytes = 512 +# bytes of the array, at 16384-512 = 15872, which leaves a 9544-byte margin over the +# epilogue's 6328. +RET_SCRATCH_SYMBOL = "_ZZ33cuda_dldn_engine_swin_dec4_kernel33DldnEngineSwinEncParamsStructBaseE4smem" +# The handoff therefore takes the top 32 lanes * 24 bytes = 768 bytes of the array, at +# 16384-768 = 15616, which leaves a 9288-byte margin over the epilogue's 6328. +RET_STRIDE = 4 * len(RET_REGS) # 24 bytes per lane +RET_BASE = 16384 - 32 * RET_STRIDE # 15616: the top of the array + +# The two addresses the callee needs besides its registers. enc0 hands over the weight +# image and the parameter block as .b64; dec4's equivalents are %rd2 (`ld.param.u64 %rd2, +# [param_0+40]`, file line 1037, still live at the cut -- its last read before line 1707 +# is line 1471) and %rd8 (`mov.b64 %rd8, cuda_dldn_engine_swin_dec4_kernel_param_0`, +# line 1029, whose only other use is line 1032). +WEIGHT_REG = "%rd2" +PARAM_REG = "%rd8" + +# File lines: the cut replaces 1707-58079 inclusive. `before` is the first mma's opcode +# line (make_ptx.py checks lines[before-1] starts with "mma.sync.aligned.m16n8k32") and +# `after` is one past the last mma's closing line (lines 58076-58079 are the final mma, +# its operands, and its `;`). +CUT_BEFORE = 1707 +CUT_AFTER = 58080 + +CALLEE = "d4r_swin_dec4" + +# The label the prologue's slab guard branches to (file line 1049), re-emitted at the end +# of the splice because its definition at line 5591 falls inside the replaced region. +SKIP_LABEL = "$L__BB1_121" + +ENTRY = "cuda_dldn_engine_swin_dec4_kernel" +MODULE = "0019-PREPASS_ENTRYPOINT_NAME.ptx" + + +def cut_call(): + """The PTX that replaces the mma region. + + The callee is handed phase 1's sixty A registers and twenty C seeds, the weight + image, the parameter block and the address of the shared scratch; it writes the four + accumulators there and this splice reads them back into the epilogue's registers. + Mirrors make_ptx.py's swin_cut_call() for enc0, with dec4's register lists. + + The trailing `$L__BB1_121:` is load-bearing. The prologue guards the slab index at + line 1049 -- `setp.gt.u32 %p3, %r9, 3` / `@%p3 bra $L__BB1_121` -- to send the four + idle waves of the eight-wave block past all the work. Its target was defined at + file line 5591, *inside* the region this call replaces, so without a replacement + label the branch dangles and the PTX translator fails with + `UnknownSymbol("$L__BB1_121")`. Re-emitting it here lands those waves just before + the epilogue's opening `bar.sync 0` (line 58082), which is where they must arrive: + they take no part in the call, and the only barriers the working waves execute from + here on are that one and the one at line 58122, both of which they reach. + """ + args = A_REGS + C_REGS + decl = "\n".join(f"\t.param .b32 p{i};" for i in range(len(args))) + store_args = "\n".join(f"\tst.param.b32 [p{i}+0], {r};" for i, r in enumerate(args)) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store_args += (f"\n\tst.param.b64 [pw+0], {WEIGHT_REG};" + f"\n\tst.param.b64 [pv+0], {PARAM_REG};" + f"\n\tmov.u32 %rswin0, {RET_SCRATCH_SYMBOL};" + "\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join([f"p{i}" for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin1+{RET_BASE + 4 * i}];" + for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store_args} +\tcall.uni {CALLEE}, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {RET_STRIDE}, %rswin0; +{gets} +}} +{SKIP_LABEL}:""" + + +def extern(): + """The `.extern .func` declaration, in the same argument order as cut_call().""" + args = ", ".join([f".param .b32 d4r_a{i}" for i in range(len(A_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func {CALLEE}\n(\n\t{args}\n)\n;\n" + + +def recipe(): + """make_ptx.py's per-layer hook: the kernel spec for cuda_dldn_engine_swin_dec4_kernel.""" + return dict(file=MODULE, + cut_call=(CUT_BEFORE, CUT_AFTER), + call=cut_call(), + extern=extern()) diff --git a/kernels/rr/swin_enc0_debug_stages.py b/kernels/rr/swin_enc0_debug_stages.py new file mode 100644 index 0000000..fe0bf7a --- /dev/null +++ b/kernels/rr/swin_enc0_debug_stages.py @@ -0,0 +1,81 @@ +#!/usr/bin/env python3 +"""Oracle debug stages for cuda_dldn_engine_swin_enc0_kernel's phases 8..22. + +Each stage is a (file line after which the store block goes, registers in order) tuple for +kernels/tex/make_ptx.py's SWIN_DEBUG_STAGES, so D4R_RRSWIN_DEBUG=p8 (p8o, p9, p10, ...) +builds NVIDIA's own body with that stage's registers stored into the plane arena, which +kernels/rr/rrswin_enc0.hip's D4R_RRSWIN_DEBUG_STAGE reproduces from its own registers. + +GENERATED by kernels/tools/swin_stages.py from the corpus PTX -- do not edit. An +accumulator stage keeps the mma whose D pair no other mma of the phase reads as its C (the +last k-step of an accumulating chain) and lists the tiles in mma order: m-tile major, +n-tile minor, the row pair (row g, row g+8) at each base. An operand stage lists the A +fragments, the B fragment pairs and the C seeds as the mma read them. +""" + + +def swin_pairs(bases): + """One register pair per base: a tile's (row g, row g+8) D registers.""" + return sum(([f"%r{b + rh}" for rh in (0, 1)] for b in bases), []) + + +def swin_quads(bases): + """One A fragment per base: four b32.""" + return sum(([f"%r{b + o}" for o in range(4)] for b in bases), []) + + +def stages(): + """The stage table: name -> (splice line, registers).""" + return { + # phase 8: 24 mma, 24 output tiles, splice after file line 19934 + "p8": (19934, swin_pairs([6503, 6513, 6523, 6533, 6543, 6553, 6563, 6573, 6583, 6593, 6603, 6613, 6623, 6633, 6643, 6653, 6663, 6673, 6683, 6693, 6703, 6713, 6723, 6733])), + # HAND-ADDED (not produced by kernels/tools/swin_stages.py): phase 8's 32 operand registers + # followed by its 48 accumulator registers, so one capture gives a phase's inputs and its + # output from the same run -- the pilot needs both from one frame. Both sets are live at + # line 19934 (the operands because phase 8's mma have not overwritten them, the + # accumulators because the store is after its last mma). Slot is 16384 for 80 registers. + "p8c": (19934, ['%r6784', '%r6785', '%r6786', '%r6787', '%r6824', '%r6825', '%r6826', '%r6827', '%r6864', '%r6865', '%r6866', '%r6867', '%r6904', '%r6905', '%r6906', '%r6907', '%r6944', '%r6945', '%r6946', '%r6947', '%r6984', '%r6985', '%r6986', '%r6987', '%r6495', '%r6496', '%r6497', '%r6498', '%r6499', '%r6500', '%r6501', '%r6502', '%r6503', '%r6504', '%r6513', '%r6514', '%r6523', '%r6524', '%r6533', '%r6534', '%r6543', '%r6544', '%r6553', '%r6554', '%r6563', '%r6564', '%r6573', '%r6574', '%r6583', '%r6584', '%r6593', '%r6594', '%r6603', '%r6604', '%r6613', '%r6614', '%r6623', '%r6624', '%r6633', '%r6634', '%r6643', '%r6644', '%r6653', '%r6654', '%r6663', '%r6664', '%r6673', '%r6674', '%r6683', '%r6684', '%r6693', '%r6694', '%r6703', '%r6704', '%r6713', '%r6714', '%r6723', '%r6724', '%r6733', '%r6734']), +"p8o": (19934, swin_quads([6784, 6824, 6864, 6904, 6944, 6984]) + swin_pairs([6495, 6497, 6499, 6501])), # A fragments, B fragment pairs; 32 registers + # phase 9: 24 mma, 24 output tiles, splice after file line 20115 + "p9": (20115, swin_pairs([6752, 6762, 6772, 6782, 6792, 6802, 6812, 6822, 6832, 6842, 6852, 6862, 6872, 6882, 6892, 6902, 6912, 6922, 6932, 6942, 6952, 6962, 6972, 6982])), + "p9o": (20115, swin_quads([6784, 6824, 6864, 6904, 6944, 6984]) + swin_pairs([6744, 6746, 6748, 6750])), # A fragments, B fragment pairs; 32 registers + # phase 10: 48 mma, 48 output tiles, splice after file line 20832 + "p10": (20832, swin_pairs([7169, 7179, 7189, 7199, 7209, 7219, 7229, 7239, 7249, 7259, 7269, 7279, 7289, 7299, 7309, 7319, 7329, 7339, 7349, 7359, 7369, 7379, 7389, 7399, 7409, 7419, 7429, 7439, 7449, 7459, 7469, 7479, 7489, 7499, 7509, 7519, 7529, 7539, 7549, 7559, 7569, 7579, 7589, 7599, 7609, 7619, 7629, 7639])), + "p10o": (20832, swin_quads([7281, 7401, 7521, 7641]) + swin_pairs([7535, 7545, 7555, 7565, 7575, 7585, 7595, 7605, 7615, 7625, 7635, 7645]) + ["%r6993", "%r6994", "%r6995", "%r6996", "%r7009", "%r7010", "%r7011", "%r7012", "%r7025", "%r7026", "%r7027", "%r7028", "%r7041", "%r7042", "%r7043", "%r7044", "%r7057", "%r7058", "%r7059", "%r7060", "%r7073", "%r7074", "%r7075", "%r7076", "%r6997", "%r6998", "%r6999", "%r7000", "%r7013", "%r7014", "%r7015", "%r7016", "%r7029", "%r7030", "%r7031", "%r7032", "%r7045", "%r7046", "%r7047", "%r7048", "%r7061", "%r7062", "%r7063", "%r7064", "%r7077", "%r7078", "%r7079", "%r7080", "%r7001", "%r7002", "%r7003", "%r7004", "%r7017", "%r7018", "%r7019", "%r7020", "%r7033", "%r7034", "%r7035", "%r7036", "%r7049", "%r7050", "%r7051", "%r7052", "%r7065", "%r7066", "%r7067", "%r7068", "%r7081", "%r7082", "%r7083", "%r7084", "%r7005", "%r7006", "%r7007", "%r7008", "%r7021", "%r7022", "%r7023", "%r7024", "%r7037", "%r7038", "%r7039", "%r7040", "%r7053", "%r7054", "%r7055", "%r7056", "%r7069", "%r7070", "%r7071", "%r7072", "%r7085", "%r7086", "%r7087", "%r7088"]), # A fragments, B fragment pairs, C seeds; 136 registers + # phase 11: 48 mma, 16 output tiles, splice after file line 31306 + "p11": (31306, swin_pairs([10455, 10465, 10515, 10525, 10575, 10585, 10635, 10645, 10695, 10705, 10755, 10765, 10815, 10825, 10875, 10885])), + "p11o": (31306, swin_quads([10487, 10507, 10527, 10607, 10627, 10647, 10727, 10747, 10767, 10847, 10867, 10887]) + swin_pairs([10781, 10791, 10801, 10811, 10821, 10831, 10841, 10851, 10861, 10871, 10881, 10891])), # A fragments, B fragment pairs; 72 registers + # phase 12: 16 mma, 16 output tiles, splice after file line 31543 + "p12": (31543, swin_pairs([10936, 10946, 10956, 10966, 10976, 10986, 10996, 11006, 11016, 11026, 11036, 11046, 11056, 11066, 11076, 11086])), + "p12o": (31543, swin_quads([10968, 11008, 11048, 11088]) + swin_pairs([10896, 10898, 10900, 10902]) + ["%r6334", "%r6335", "%r6344", "%r6345", "%r6354", "%r6355", "%r6364", "%r6365", "%r6374", "%r6375", "%r6384", "%r6385", "%r6394", "%r6395", "%r6404", "%r6405", "%r6414", "%r6415", "%r6424", "%r6425", "%r6434", "%r6435", "%r6444", "%r6445", "%r6454", "%r6455", "%r6464", "%r6465", "%r6474", "%r6475", "%r6484", "%r6485"]), # A fragments, B fragment pairs, C seeds; 56 registers + # phase 13: 16 mma, 16 output tiles, splice after file line 33797 + "p13": (33797, swin_pairs([11424, 11434, 11444, 11454, 11464, 11474, 11484, 11494, 11504, 11514, 11524, 11534, 11544, 11554, 11564, 11574])), + "p13o": (33797, swin_quads([11456, 11496, 11536, 11576]) + swin_pairs([11383, 11385, 11387, 11389]) + ["%r11553", "%r11563", "%r11573", "%r11583"]), # A fragments, B fragment pairs, C seeds; 28 registers + # phase 14: 16 mma, 16 output tiles, splice after file line 36260 + "p14": (36260, swin_pairs([12555, 12565, 12575, 12585, 12595, 12605, 12615, 12625, 12635, 12645, 12655, 12665, 12675, 12685, 12695, 12705])), + "p14o": (36260, swin_quads([12587, 12627, 12667, 12707]) + swin_pairs([12514, 12516, 12518, 12520]) + ["%r12563", "%r12564", "%r12573", "%r12574", "%r12583", "%r12584", "%r12593", "%r12594", "%r12603", "%r12604", "%r12613", "%r12614", "%r12623", "%r12624", "%r12633", "%r12634", "%r12643", "%r12644", "%r12653", "%r12654", "%r12663", "%r12664", "%r12673", "%r12674", "%r12683", "%r12684", "%r12693", "%r12694", "%r12703", "%r12704", "%r12713", "%r12714"]), # A fragments, B fragment pairs, C seeds; 56 registers + # phase 15: 16 mma, 16 output tiles, splice after file line 36508 + "p15": (36508, swin_pairs([12757, 12767, 12777, 12787, 12797, 12807, 12817, 12827, 12837, 12847, 12857, 12867, 12877, 12887, 12897, 12907])), + "p15o": (36508, swin_quads([12789, 12829, 12869, 12909]) + swin_pairs([12716, 12718, 12720, 12722]) + ["%r12886", "%r12896", "%r12906", "%r12916"]), # A fragments, B fragment pairs, C seeds; 28 registers + # phase 16: 16 mma, 16 output tiles, splice after file line 38668 + "p16": (38668, swin_pairs([13887, 13897, 13907, 13917, 13927, 13937, 13947, 13957, 13967, 13977, 13987, 13997, 14007, 14017, 14027, 14037])), + "p16o": (38668, swin_quads([13919, 13959, 13999, 14039]) + swin_pairs([13847, 13849, 13851, 13853]) + ["%r12555", "%r12556", "%r12565", "%r12566", "%r12575", "%r12576", "%r12585", "%r12586", "%r12595", "%r12596", "%r12605", "%r12606", "%r12615", "%r12616", "%r12625", "%r12626", "%r12635", "%r12636", "%r12645", "%r12646", "%r12655", "%r12656", "%r12665", "%r12666", "%r12675", "%r12676", "%r12685", "%r12686", "%r12695", "%r12696", "%r12705", "%r12706"]), # A fragments, B fragment pairs, C seeds; 56 registers + # phase 17: 16 mma, 16 output tiles, splice after file line 38916 + "p17": (38916, swin_pairs([14089, 14099, 14109, 14119, 14129, 14139, 14149, 14159, 14169, 14179, 14189, 14199, 14209, 14219, 14229, 14239])), + "p17o": (38916, swin_quads([14121, 14161, 14201, 14241]) + swin_pairs([14048, 14050, 14052, 14054]) + ["%r14218", "%r14228", "%r14238", "%r14248"]), # A fragments, B fragment pairs, C seeds; 28 registers + # phase 18: 16 mma, 16 output tiles, splice after file line 41076 + "p18": (41076, swin_pairs([15219, 15229, 15239, 15249, 15259, 15269, 15279, 15289, 15299, 15309, 15319, 15329, 15339, 15349, 15359, 15369])), + "p18o": (41076, swin_quads([15251, 15291, 15331, 15371]) + swin_pairs([15179, 15181, 15183, 15185]) + ["%r13887", "%r13888", "%r13897", "%r13898", "%r13907", "%r13908", "%r13917", "%r13918", "%r13927", "%r13928", "%r13937", "%r13938", "%r13947", "%r13948", "%r13957", "%r13958", "%r13967", "%r13968", "%r13977", "%r13978", "%r13987", "%r13988", "%r13997", "%r13998", "%r14007", "%r14008", "%r14017", "%r14018", "%r14027", "%r14028", "%r14037", "%r14038"]), # A fragments, B fragment pairs, C seeds; 56 registers + # phase 19: 16 mma, 16 output tiles, splice after file line 41324 + "p19": (41324, swin_pairs([15421, 15431, 15441, 15451, 15461, 15471, 15481, 15491, 15501, 15511, 15521, 15531, 15541, 15551, 15561, 15571])), + "p19o": (41324, swin_quads([15453, 15493, 15533, 15573]) + swin_pairs([15380, 15382, 15384, 15386]) + ["%r15550", "%r15560", "%r15570", "%r15580"]), # A fragments, B fragment pairs, C seeds; 28 registers + # phase 20: 16 mma, 16 output tiles, splice after file line 43484 + "p20": (43484, swin_pairs([16551, 16561, 16571, 16581, 16591, 16601, 16611, 16621, 16631, 16641, 16651, 16661, 16671, 16681, 16691, 16701])), + "p20o": (43484, swin_quads([16583, 16623, 16663, 16703]) + swin_pairs([16511, 16513, 16515, 16517]) + ["%r15219", "%r15220", "%r15229", "%r15230", "%r15239", "%r15240", "%r15249", "%r15250", "%r15259", "%r15260", "%r15269", "%r15270", "%r15279", "%r15280", "%r15289", "%r15290", "%r15299", "%r15300", "%r15309", "%r15310", "%r15319", "%r15320", "%r15329", "%r15330", "%r15339", "%r15340", "%r15349", "%r15350", "%r15359", "%r15360", "%r15369", "%r15370"]), # A fragments, B fragment pairs, C seeds; 56 registers + # phase 21: 32 mma, 8 output tiles, splice after file line 44258 + "p21": (44258, swin_pairs([17298, 17308, 17378, 17388, 17458, 17468, 17538, 17548])), + "p21o": (44258, swin_quads([17490, 17510, 17530, 17550]) + swin_pairs([17173, 17175, 17177, 17179, 17181, 17183, 17185, 17187, 17189, 17191, 17193, 17195, 17197, 17199, 17201, 17203, 17205, 17207, 17209, 17211, 17213, 17215, 17217, 17219, 17221, 17223, 17225, 17227, 17229, 17231, 17233, 17235]) + ["%r17247", "%r17257", "%r17327", "%r17337", "%r17407", "%r17417", "%r17487", "%r17497"]), # A fragments, B fragment pairs, C seeds; 88 registers + # phase 22: 8 mma, 8 output tiles, splice after file line 44527 + "p22": (44527, swin_pairs([17634, 17644, 17654, 17664, 17674, 17684, 17694, 17704])), + "p22o": (44527, swin_quads([262, 266, 270, 274]) + swin_pairs([17629, 17631]) + ["%r17703", "%r17713"] + ["%r10854", "%r10854"]), # A fragments, B fragment pairs, C seeds; 24 registers + } diff --git a/kernels/rr/swin_enc0_recipe.py b/kernels/rr/swin_enc0_recipe.py new file mode 100644 index 0000000..f6ec828 --- /dev/null +++ b/kernels/rr/swin_enc0_recipe.py @@ -0,0 +1,43 @@ +"""Enc0 cut recipes; isolated phase 8 preserves NVIDIA's other phases.""" +import os +import sys +from pathlib import Path + + +def recipe(): + sys.path.insert(0, str(Path(__file__).resolve().parent.parent / "tex")) + import make_ptx + + if not os.environ.get("D4R_RRSWIN_PHASE8"): + if os.environ.get("D4R_RRSWIN_CUT"): + return dict(file="0013-PREPASS_ENTRYPOINT_NAME.ptx", cut_call=(3964, 44528), + extern=make_ptx.swin_cut_extern()) + return make_ptx.KERNELS["cuda_dldn_engine_swin_enc0_kernel"] + + calls = [] + for mi, base in enumerate((6784, 6824, 6864, 6904, 6944, 6984)): + operands = [f"%r{base + i}" for i in range(4)] + operands += [f"%r{6495 + i}" for i in range(8)] + outputs = [f"%r{6503 + 40 * mi + 10 * nt + rh}" for nt in range(4) for rh in range(2)] + declarations = "\n".join(f"\t.param .b32 p8a{i};" for i in range(12)) + stores = "\n".join(f"\tst.param.b32 [p8a{i}], {reg};" for i, reg in enumerate(operands)) + loads = "\n".join(f"\tld.shared.b32 {reg}, [%p8out+{4 * i}];" for i, reg in enumerate(outputs)) + args = ", ".join([f"p8a{i}" for i in range(12)] + ["p8s"]) + calls.append(f"""{{ +\t.reg .b32 %p8out; +{declarations} +\t.param .b32 p8s; +{stores} +\tst.param.b32 [p8s], %p8base; +\tcall.uni d4r_swin_enc0_p8, ({args}); +\tmad.lo.u32 %p8out, %laneid, 32, %p8base; +{loads} +}}""") + # input_tensor's last read is in the prologue (line 3938); only the + # disjoint input_noise array is read by the final surface epilogue. + call = "{\n\t.reg .b32 %p8base;\n" + call += f"\tmov.u32 %p8base, {make_ptx.SWIN_RET_SCRATCH};\n" + "\n".join(calls) + "\n}" + params = ",\n\t".join([f".param .b32 a{i}" for i in range(12)] + + [".param .b32 scratch"]) + return dict(file="0013-PREPASS_ENTRYPOINT_NAME.ptx", cut_call=(19770, 19935), + call=call, extern=f".extern .func d4r_swin_enc0_p8\n(\n\t{params}\n)\n;\n") diff --git a/kernels/rr/swin_enc1_debug_stages.py b/kernels/rr/swin_enc1_debug_stages.py new file mode 100644 index 0000000..23d5480 --- /dev/null +++ b/kernels/rr/swin_enc1_debug_stages.py @@ -0,0 +1,153 @@ +"""Debug-oracle stages for `cuda_dldn_engine_swin_enc1_kernel`. + +Loaded by `kernels/tex/make_ptx.py` (the `swin_*_debug_stages.py` hook) so that +`D4R_RRSWIN_DEBUG= kernels/build.sh rrswin ` splices a store of that +stage's registers into NVIDIA's own body, at the line recorded here. The native +body reproduces the same registers at `-DD4R_RRSWIN_DEBUG_STAGE=` +(`D4R_TEX_CFLAGS`), so the two launch dumps' payload regions compare byte for byte. + +Stage -> native number, and what the registers are (the order is the store order on +both sides): + + a 10 the two staged A operand sets (phases 1/2/8/9 and 3/4/10/11), the phase-1 + C seed and the three shfl constants (1, 2, -1) -- 52 registers + p1 1 phase 1's 24 mma D pairs, m-tile major / n-tile minor -- 48 registers + p2 2 phase 2's, likewise -- 48 + p3 3 phase 3's -- 48 + p4 4 phase 4's -- 48 + p5 5 phase 5's (the 64x96 score) -- 96 + p5o 8 phase 5's 96 C (score-bias) words in tile order, then its 24 B (key) words + p6 6 phase 6's sixteen chain-final D pairs -- 32 + e6 9 phase 7's 16 A registers, then its 64 C seeds -- 80 + p7 7 phase 7's 32 mma D pairs -- 64 + +Each stage is stored next to its own phase, which is where `make_ptx.py` requires the +insertion line to be (the line must end an `mma` statement, and the stage's first +register must have been defined within the previous 4000 lines). + +The store is *not* readable back from a harness launch dump for enc1. The payload +lives in the plane arena, whose tail later kernels of the same frame rewrite before the +dump reads it back: measured over the payload window, the oracle build's `arg048` +carrier and a plain translated run's are byte-identical, which is exactly the "the +store did not land" signal. So the comparison runs on an isolated single launch of +this kernel instead; see the note above `debug_store()` in +`kernels/rr/rrswin_enc1.hip` for the base and the window. + +Line numbers are 1-based in the corpus module; the store is spliced in after the +recorded line. +""" + + +def stages(): + return { + # 52 registers, inserted after file line 13342 + "a": (13342, [ + "%r11097", "%r11098", "%r11099", "%r11100", "%r11137", "%r11138", "%r11139", "%r11140", + "%r11177", "%r11178", "%r11179", "%r11180", "%r11217", "%r11218", "%r11219", "%r11220", + "%r11257", "%r11258", "%r11259", "%r11260", "%r11297", "%r11298", "%r11299", "%r11300", + "%r11595", "%r11596", "%r11597", "%r11598", "%r11635", "%r11636", "%r11637", "%r11638", + "%r11675", "%r11676", "%r11677", "%r11678", "%r11715", "%r11716", "%r11717", "%r11718", + "%r11755", "%r11756", "%r11757", "%r11758", "%r11795", "%r11796", "%r11797", "%r11798", + "%r15665", "%r16376", "%r16385", "%r16387" + ]), + # 48 registers, inserted after file line 13510 + "p1": (13510, [ + "%r5547", "%r5548", "%r5557", "%r5558", "%r5567", "%r5568", "%r5577", "%r5578", + "%r5587", "%r5588", "%r5597", "%r5598", "%r5607", "%r5608", "%r5617", "%r5618", + "%r5627", "%r5628", "%r5637", "%r5638", "%r5647", "%r5648", "%r5657", "%r5658", + "%r5667", "%r5668", "%r5677", "%r5678", "%r5687", "%r5688", "%r5697", "%r5698", + "%r5707", "%r5708", "%r5717", "%r5718", "%r5727", "%r5728", "%r5737", "%r5738", + "%r5747", "%r5748", "%r5757", "%r5758", "%r5767", "%r5768", "%r5777", "%r5778" + ]), + # 48 registers, inserted after file line 13691 + "p2": (13691, [ + "%r5796", "%r5797", "%r5806", "%r5807", "%r5816", "%r5817", "%r5826", "%r5827", + "%r5836", "%r5837", "%r5846", "%r5847", "%r5856", "%r5857", "%r5866", "%r5867", + "%r5876", "%r5877", "%r5886", "%r5887", "%r5896", "%r5897", "%r5906", "%r5907", + "%r5916", "%r5917", "%r5926", "%r5927", "%r5936", "%r5937", "%r5946", "%r5947", + "%r5956", "%r5957", "%r5966", "%r5967", "%r5976", "%r5977", "%r5986", "%r5987", + "%r5996", "%r5997", "%r6006", "%r6007", "%r6016", "%r6017", "%r6026", "%r6027" + ]), + # 48 registers, inserted after file line 13872 + "p3": (13872, [ + "%r6045", "%r6046", "%r6055", "%r6056", "%r6065", "%r6066", "%r6075", "%r6076", + "%r6085", "%r6086", "%r6095", "%r6096", "%r6105", "%r6106", "%r6115", "%r6116", + "%r6125", "%r6126", "%r6135", "%r6136", "%r6145", "%r6146", "%r6155", "%r6156", + "%r6165", "%r6166", "%r6175", "%r6176", "%r6185", "%r6186", "%r6195", "%r6196", + "%r6205", "%r6206", "%r6215", "%r6216", "%r6225", "%r6226", "%r6235", "%r6236", + "%r6245", "%r6246", "%r6255", "%r6256", "%r6265", "%r6266", "%r6275", "%r6276" + ]), + # 48 registers, inserted after file line 14053 + "p4": (14053, [ + "%r6294", "%r6295", "%r6304", "%r6305", "%r6314", "%r6315", "%r6324", "%r6325", + "%r6334", "%r6335", "%r6344", "%r6345", "%r6354", "%r6355", "%r6364", "%r6365", + "%r6374", "%r6375", "%r6384", "%r6385", "%r6394", "%r6395", "%r6404", "%r6405", + "%r6414", "%r6415", "%r6424", "%r6425", "%r6434", "%r6435", "%r6444", "%r6445", + "%r6454", "%r6455", "%r6464", "%r6465", "%r6474", "%r6475", "%r6484", "%r6485", + "%r6494", "%r6495", "%r6504", "%r6505", "%r6514", "%r6515", "%r6524", "%r6525" + ]), + # 96 registers, inserted after file line 14770 + "p5": (14770, [ + "%r6711", "%r6712", "%r6721", "%r6722", "%r6731", "%r6732", "%r6741", "%r6742", + "%r6751", "%r6752", "%r6761", "%r6762", "%r6771", "%r6772", "%r6781", "%r6782", + "%r6791", "%r6792", "%r6801", "%r6802", "%r6811", "%r6812", "%r6821", "%r6822", + "%r6831", "%r6832", "%r6841", "%r6842", "%r6851", "%r6852", "%r6861", "%r6862", + "%r6871", "%r6872", "%r6881", "%r6882", "%r6891", "%r6892", "%r6901", "%r6902", + "%r6911", "%r6912", "%r6921", "%r6922", "%r6931", "%r6932", "%r6941", "%r6942", + "%r6951", "%r6952", "%r6961", "%r6962", "%r6971", "%r6972", "%r6981", "%r6982", + "%r6991", "%r6992", "%r7001", "%r7002", "%r7011", "%r7012", "%r7021", "%r7022", + "%r7031", "%r7032", "%r7041", "%r7042", "%r7051", "%r7052", "%r7061", "%r7062", + "%r7071", "%r7072", "%r7081", "%r7082", "%r7091", "%r7092", "%r7101", "%r7102", + "%r7111", "%r7112", "%r7121", "%r7122", "%r7131", "%r7132", "%r7141", "%r7142", + "%r7151", "%r7152", "%r7161", "%r7162", "%r7171", "%r7172", "%r7181", "%r7182" + ]), + # 120 registers, inserted after file line 14770 + "p5o": (14770, [ + "%r6535", "%r6536", "%r6537", "%r6538", "%r6539", "%r6540", "%r6541", "%r6542", + "%r6543", "%r6544", "%r6545", "%r6546", "%r6547", "%r6548", "%r6549", "%r6550", + "%r6551", "%r6552", "%r6553", "%r6554", "%r6555", "%r6556", "%r6557", "%r6558", + "%r6559", "%r6560", "%r6561", "%r6562", "%r6563", "%r6564", "%r6565", "%r6566", + "%r6567", "%r6568", "%r6569", "%r6570", "%r6571", "%r6572", "%r6573", "%r6574", + "%r6575", "%r6576", "%r6577", "%r6578", "%r6579", "%r6580", "%r6581", "%r6582", + "%r6583", "%r6584", "%r6585", "%r6586", "%r6587", "%r6588", "%r6589", "%r6590", + "%r6591", "%r6592", "%r6593", "%r6594", "%r6595", "%r6596", "%r6597", "%r6598", + "%r6599", "%r6600", "%r6601", "%r6602", "%r6603", "%r6604", "%r6605", "%r6606", + "%r6607", "%r6608", "%r6609", "%r6610", "%r6611", "%r6612", "%r6613", "%r6614", + "%r6615", "%r6616", "%r6617", "%r6618", "%r6619", "%r6620", "%r6621", "%r6622", + "%r6623", "%r6624", "%r6625", "%r6626", "%r6627", "%r6628", "%r6629", "%r6630", + "%r7077", "%r7078", "%r7087", "%r7088", "%r7097", "%r7098", "%r7107", "%r7108", + "%r7117", "%r7118", "%r7127", "%r7128", "%r7137", "%r7138", "%r7147", "%r7148", + "%r7157", "%r7158", "%r7167", "%r7168", "%r7177", "%r7178", "%r7187", "%r7188" + ]), + # 32 registers, inserted after file line 25249 + "p6": (25249, [ + "%r9997", "%r9998", "%r10007", "%r10008", "%r10057", "%r10058", "%r10067", "%r10068", + "%r10117", "%r10118", "%r10127", "%r10128", "%r10177", "%r10178", "%r10187", "%r10188", + "%r10237", "%r10238", "%r10247", "%r10248", "%r10297", "%r10298", "%r10307", "%r10308", + "%r10357", "%r10358", "%r10367", "%r10368", "%r10417", "%r10418", "%r10427", "%r10428" + ]), + # 64 registers, inserted after file line 26197 + "p7": (26197, [ + "%r10487", "%r10488", "%r10497", "%r10498", "%r10507", "%r10508", "%r10517", "%r10518", + "%r10527", "%r10528", "%r10537", "%r10538", "%r10547", "%r10548", "%r10557", "%r10558", + "%r10567", "%r10568", "%r10577", "%r10578", "%r10587", "%r10588", "%r10597", "%r10598", + "%r10607", "%r10608", "%r10617", "%r10618", "%r10627", "%r10628", "%r10637", "%r10638", + "%r10647", "%r10648", "%r10657", "%r10658", "%r10667", "%r10668", "%r10677", "%r10678", + "%r10687", "%r10688", "%r10697", "%r10698", "%r10707", "%r10708", "%r10717", "%r10718", + "%r10727", "%r10728", "%r10737", "%r10738", "%r10747", "%r10748", "%r10757", "%r10758", + "%r10767", "%r10768", "%r10777", "%r10778", "%r10787", "%r10788", "%r10797", "%r10798" + ]), + # 80 registers, inserted after file line 25973 + "e6": (25973, [ + "%r10559", "%r10560", "%r10561", "%r10562", "%r10639", "%r10640", "%r10641", "%r10642", + "%r10719", "%r10720", "%r10721", "%r10722", "%r10799", "%r10800", "%r10801", "%r10802", + "%r10495", "%r10496", "%r10505", "%r10506", "%r10515", "%r10516", "%r10525", "%r10526", + "%r10535", "%r10536", "%r10545", "%r10546", "%r10555", "%r10556", "%r10565", "%r10566", + "%r10575", "%r10576", "%r10585", "%r10586", "%r10595", "%r10596", "%r10605", "%r10606", + "%r10615", "%r10616", "%r10625", "%r10626", "%r10635", "%r10636", "%r10645", "%r10646", + "%r10655", "%r10656", "%r10665", "%r10666", "%r10675", "%r10676", "%r10685", "%r10686", + "%r10695", "%r10696", "%r10705", "%r10706", "%r10715", "%r10716", "%r10725", "%r10726", + "%r10735", "%r10736", "%r10745", "%r10746", "%r10755", "%r10756", "%r10765", "%r10766", + "%r10775", "%r10776", "%r10785", "%r10786", "%r10795", "%r10796", "%r10805", "%r10806" + ]), + } diff --git a/kernels/rr/swin_enc1_recipe.py b/kernels/rr/swin_enc1_recipe.py new file mode 100644 index 0000000..7a19257 --- /dev/null +++ b/kernels/rr/swin_enc1_recipe.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 +"""Splice recipe for `cuda_dldn_engine_swin_enc1_kernel` (corpus module 0014). + +Self-contained: `kernels/tex/make_ptx.py` imports this module by path when the kernel +name matches and uses what `recipe()` returns. Everything below was derived from the +corpus PTX with `kernels/rr/rr_layer_spec.py enc1` and the register traces recorded in +`kernels/rr/rrswin_enc1_epilogues.md`: + + * the cut is the mma region, statements s8270-s26139, i.e. file lines 13343-66944 + (1072 `mma.sync` in 32 phases). `make_ptx.py` requires line 13343 to start an mma + and line 66944 to end one, so CUT's second entry is 66945. + * the live-in set is the two staged 96x32 e4m3 A operand sets the prologue built + (%r11097.. for phases 1/2/8/9, %r11595.. for phases 3/4/10/11), phase 1's C seed + register (%r15665, the constant zero of `mov.u32 %r15665, 0`), and the 64 packed + f16x2 registers of the dequantised input tile (%r4678..%r4741) that E6 adds to + phase 7's per-column table. The tile is passed in the order E6 consumes it: + (m-tile 0..3, n-tile 0..7, row half 0..1). + * the live-out set is phase 32's eight mma D pairs (16 registers). The two extents + %r31837/%r31838 come from `ld.param.v2.u32 [param_0+0]` inside the cut, so the + splice re-reads them instead of carrying them across. + +ZLUDA lowers `call.uni`'s return parameters to the callee's LLVM return type and forms +no parameter-space object for them (ptx/src/pass/llvm/emit.rs, `emit_call`), so the +accumulators cross the cut through LDS instead. This module's entry declares no +`.shared` array at all -- 0014 has none -- so the splice declares `d4r_scratch` itself: +ZLUDA parses a `.shared` declaration in the middle of a body and sizes the workgroup's +LDS from it (verified with d4r_emit). `kernels/rr/rrswin_enc1.hip` writes the sixteen +accumulators at `base + 64*laneid + 4*i`; the splice reads them back with ld.shared. +""" + +ENTRY = "cuda_dldn_engine_swin_enc1_kernel" +FILE = "0014-PREPASS_ENTRYPOINT_NAME.ptx" + +# cut: the mma region, 1-based inclusive file lines +CUT = (13343, 66945) + +# A operand set 1: phases 1, 2, 8 and 9 (six 16-row fragments x four b32) +AS1 = [ + "%r11097", "%r11098", "%r11099", "%r11100", "%r11137", "%r11138", "%r11139", "%r11140", + "%r11177", "%r11178", "%r11179", "%r11180", "%r11217", "%r11218", "%r11219", "%r11220", + "%r11257", "%r11258", "%r11259", "%r11260", "%r11297", "%r11298", "%r11299", "%r11300" +] + +# A operand set 2: phases 3, 4, 10 and 11 (the prologue's second, normalised packing) +AS2 = [ + "%r11595", "%r11596", "%r11597", "%r11598", "%r11635", "%r11636", "%r11637", "%r11638", + "%r11675", "%r11676", "%r11677", "%r11678", "%r11715", "%r11716", "%r11717", "%r11718", + "%r11755", "%r11756", "%r11757", "%r11758", "%r11795", "%r11796", "%r11797", "%r11798" +] + +# phase 1's C seed: the constant-zero register %r15665 +CSEED = ["%r15665"] + +# the dequantised input tile E6 adds to phase 7's column table, indexed +# (m-tile 0..3, n-tile 0..7, row half 0..1) +RES = [ + "%r4678", "%r4682", "%r4680", "%r4684", "%r4679", "%r4683", "%r4681", "%r4685", + "%r4686", "%r4690", "%r4688", "%r4692", "%r4687", "%r4691", "%r4689", "%r4693", + "%r4694", "%r4698", "%r4696", "%r4700", "%r4695", "%r4699", "%r4697", "%r4701", + "%r4702", "%r4706", "%r4704", "%r4708", "%r4703", "%r4707", "%r4705", "%r4709", + "%r4710", "%r4714", "%r4712", "%r4716", "%r4711", "%r4715", "%r4713", "%r4717", + "%r4718", "%r4722", "%r4720", "%r4724", "%r4719", "%r4723", "%r4721", "%r4725", + "%r4726", "%r4730", "%r4728", "%r4732", "%r4727", "%r4731", "%r4729", "%r4733", + "%r4734", "%r4738", "%r4736", "%r4740", "%r4735", "%r4739", "%r4737", "%r4741" +] + +# live-out: phase 32's eight mma D pairs. %r31837/%r31838 (the extents) are re-read +# from param_0 by the splice, so only the sixteen accumulators cross the cut. +RET_ACCS = [ + "%r31908", "%r31909", "%r31918", "%r31919", "%r31948", "%r31949", "%r31958", "%r31959", + "%r31988", "%r31989", "%r31998", "%r31999", "%r32028", "%r32029", "%r32038", "%r32039" +] + +NP = len(AS1) + len(AS2) + len(CSEED) + len(RES) +B32 = AS1 + AS2 + CSEED + RES +SCRATCH_WORDS = 2048 # 8 KiB of LDS: the phase 5/6 exchange, then the accumulators +RET_STRIDE = 4 * len(RET_ACCS) + + +def extern(): + """`.extern .func` for the callee: the b32 live-ins, then the weight image, the + parameter block and the LDS scratch address.""" + names = [".param .b32 d4r_a{}".format(i) for i in range(NP)] + names += [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"] + return ".extern .func d4r_swin_enc1\n(\n\t" + ", ".join(names) + "\n)\n;\n" + + +def call(): + """The splice that replaces the mma region: hand the live-ins to the native body, + then read the accumulators back out of LDS.""" + stores = "\n".join("\tst.param.b32 [q%d+0], %s;" % (i, r) for i, r in enumerate(B32)) + hel = ", ".join(["q%d" % i for i in range(NP)] + ["qw", "qv", "qs"]) + gets = "\n".join("\tld.shared.b32 %s, [%%rsw1+%d];" % (RET_ACCS[i], 4 * i) + for i in range(len(RET_ACCS))) + return "\n".join([ + "{", + ".reg .b32 %rsw<3>;", + ".reg .b64 %rdw<2>;", + ".shared .b32 d4r_scratch[%d];" % SCRATCH_WORDS, + "mov.u32 %rsw0, d4r_scratch;", + ".param .b32 q<%d>;" % NP, + stores, + ".param .b64 qw;", + "ld.param.u64 %%rdw0, [%s_param_0+40];" % ENTRY, + "cvta.to.global.u64 %rdw0, %rdw0;", + "st.param.b64 [qw+0], %rdw0;", + ".param .b64 qv;", + "mov.b64 %%rdw1, %s_param_0;" % ENTRY, + "st.param.b64 [qv+0], %rdw1;", + ".param .b32 qs;", + "st.param.b32 [qs+0], %rsw0;", + "call.uni d4r_swin_enc1, (%s);" % hel, + "ld.param.v2.u32 {%%r31837, %%r31838}, [%s_param_0+0];" % ENTRY, + "mad.lo.s32 %%rsw1, %%laneid, %d, %%rsw0;" % RET_STRIDE, + gets, + "}", + ]) + + +def recipe(): + return dict(file=FILE, cut_call=CUT, extern=extern(), call=call()) diff --git a/kernels/rr/swin_enc2_recipe.py b/kernels/rr/swin_enc2_recipe.py new file mode 100755 index 0000000..6896d0b --- /dev/null +++ b/kernels/rr/swin_enc2_recipe.py @@ -0,0 +1,220 @@ +#!/usr/bin/env python3 +"""The splice of `cuda_dldn_engine_swin_enc2_kernel` (nvngx_dlssd.dll 310.7). + +One warp per 8x8 token patch, grid (161, 93, 1), block (32, 1, 4); the 630 mma of the +38 phases are statements s4621-s13876, file lines 7669-33949 of +`~/.cache/d4r-rr-corpus/0015-PREPASS_ENTRYPOINT_NAME.ptx`. Everything outside that +region stays NVIDIA's: the input-texture prologue (s1-s4620) and the final epilogue +(s13877-s14199, the staged softmax window, the 3x3 texture gather and the three +surface writes). Inside it, the region becomes one `call.uni` into the native body +`kernels/rr/rrswin_enc2.hip`. + +The call hands over phase 1's staged A fragments (six 16-row fragments read out of the +entry's own `.shared` tile), phase 1's B fragments, its zero C seed, the weight image +(arg040), the parameter block and the base of that same shared tile; the five +registers the epilogue reads but the region computes cross the cut through shared +memory, because ZLUDA lowers `call.uni` return parameters into the callee's LLVM +return type rather than a .param-space object (see kernels/rr/rrswin_enc0.hip). + +Every byte offset, register list and insertion line below was read out of the PTX with +`kernels/rr/rr_layer_spec.py enc2` and the stage table is regenerated by hand from its +mma chain, so `D4R_RRSWIN_DEBUG=` splices a store of *this* layer's registers +into NVIDIA's own body and the native body's `-DD4R_RRSWIN_DEBUG_STAGE=` writes the +same values in the same order. + +Self-contained by contract: nothing is imported from kernels/tex/make_ptx.py. +""" + +import os +import sys + +# --------------------------------------------------------------------------- +# the cut +FILE = "0015-PREPASS_ENTRYPOINT_NAME.ptx" +# (first line of phase 1's first mma, first line after phase 38's last mma) +CUT_CALL = (7669, 33950) + +# phase 1's A operands, in the first mma's operand order: six fragments of four, +# m-tile major. The entry stages eighteen of them (three K=32 slices x six m-tiles) +# at `smem + 512*(3*slice + m-tile) + 16*laneid`, so the body reads the other two +# slices from that same tile itself. +A_REGS = ["%r16120", "%r16121", "%r16122", "%r16123", + "%r16132", "%r16133", "%r16134", "%r16135", + "%r16144", "%r16145", "%r16146", "%r16147", + "%r16156", "%r16157", "%r16158", "%r16159", + "%r16168", "%r16169", "%r16170", "%r16171", + "%r16180", "%r16181", "%r16182", "%r16183"] +# phase 1's B operands: four fragments of two, the lane's 16 bytes of the two +# 512-byte weight tiles at arg040+192 and arg040+704 +B_REGS = ["%r3251", "%r3252", "%r3253", "%r3254", "%r3255", "%r3256", "%r3257", "%r3258"] +# phase 1's C seed: %r8606 = 0, the whole region's zero accumulator start +C_REGS = ["%r8606"] + +# what the epilogue reads but the region computes: param_0[0] (s13138), phase 38's +# two accumulator pairs (the staged softmax window) and the two values E38 itself +# needs from inside the region, %r17746 = 16*tid.z (s13139) and %r17758 = &smem (s13852) +RET_REGS = ["%r16472", "%r17496", "%r17506", "%r17746", "%r17758"] +SCRATCH = "_ZZ33cuda_dldn_engine_swin_enc2_kernel33DldnEngineSwinEncParamsStructBaseE4smem" +RET_STRIDE = 4 * len(RET_REGS) + +CALLEE = "d4r_swin_enc2" +PARAM = "cuda_dldn_engine_swin_enc2_kernel_param_0" + + +def _extern(): + """The `.extern .func` declaration: the operand registers, the weight image, the + parameter block and the shared scratch, in that order.""" + args = ", ".join([f".param .b32 d4r_a{i}" for i in range(len(A_REGS) + len(B_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func {CALLEE}\n(\n\t{args}\n)\n;\n" + + +def _call(): + """The splice: hand the operands over, call, read the five accumulators back.""" + regs = A_REGS + B_REGS + C_REGS + decl = "\n".join(f"\t.param .b32 p{i};" for i in range(len(regs))) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store_args = "\n".join(f"\tst.param.b32 [p{i}+0], {r};" for i, r in enumerate(regs)) + store_args += (f"\n\tst.param.b64 [pw+0], %rd2;\n\tst.param.b64 [pv+0], %rd8;" + f"\n\tmov.u32 %rswin0, {SCRATCH};\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join([f"p{i}" for i in range(len(regs))] + ["pw", "pv", "ps"]) + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin1+{4 * i}];" + for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store_args} +\tcall.uni {CALLEE}, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {RET_STRIDE}, %rswin0; +{gets} +}}""" + + +# --------------------------------------------------------------------------- +# Ground truth for a stage: NVIDIA's own body with a store of that stage's registers +# spliced into the plane arena, past everything the kernel writes, which the launch +# dump then holds for a block/lane. +# +# The arena is arg048, and the launch's arg048 sits at allocation offset 30,146,560 of +# a 65,945,600-byte allocation -- the bridge dumps that whole allocation under arg008 +# (arg008 is the first argument pointing into it), so only 35,799,040 bytes of arena are +# dumped. The family default of 46,000,000 lands past the end of the allocation, which +# is why the first sweep of this layer found no payload at all. 4,000,000 is past +# everything E36 scatters -- its stores are 4 bytes at idx = 8*ex*y + 8*x, so +# idx < 8*320*184 = 471,040 -- and leaves room for 64 slots of up to 32 KiB. +DEBUG_BASE = int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", 4000000)) +DEBUG_ARENA_BYTES = 35799040 +DEBUG_SLOT_FLOOR = 8192 +GRID_X = 41 # grid (41, 24, 1), block (32, 1, 4): 320/8+1 by 184/8+1 patches + +if DEBUG_BASE + 64 * 65536 >= DEBUG_ARENA_BYTES: + raise SystemExit("swin_enc2_recipe: the debug payload does not fit enc2's plane arena") + + +def _debug_block(regs): + """PTX storing REGS (u32 each) to plane arena + DEBUG_BASE + block*slot + lane*len*4.""" + want = max(DEBUG_SLOT_FLOOR, 32 * len(regs) * 4) + slot = 1 << (want - 1).bit_length() + stores = "\n".join( + f"@%pdbg1 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(regs[i * 4:i * 4 + 4])}}};" + for i in range((len(regs) + 3) // 4)) + return f"""// d4r debug stage (enc2) +{{ +.reg .pred %pdbg<3>; +.reg .b32 %rdbg<9>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{PARAM}+48]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mad.lo.s32 %rdbg3, %rdbg2, {GRID_X}, %rdbg1; +// only wave 0 of the block may store: the four z-planes read different weight slabs +// (the 21504-byte stride), so their accumulators differ +mov.u32 %rdbg8, %tid.z; +setp.ne.u32 %pdbg2, %rdbg8, 0; +selp.b32 %rdbg3, 64, %rdbg3, %pdbg2; +setp.lt.u32 %pdbg1, %rdbg3, 64; +shl.b32 %rdbg4, %rdbg3, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg7, %rdbg6, {DEBUG_BASE}; +cvt.u64.u32 %rddbg2, %rdbg7; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +# --------------------------------------------------------------------------- +# Debug stages. "e2p" stores phase n's accumulator registers in mma order (m-tile +# major, n-tile minor, each mma's (row g, row g+8) pair); the line is the last physical +# line of the phase's last mma, so the store lands between the mma block and its +# epilogue. Generated from kernels/rr/rr_layer_spec.py's own mma chain. +# +# The names carry the "e2" prefix because kernels/tex/make_ptx.py's swin_debug() falls +# back to enc0's *unkeyed* stage table when a name is absent from the keyed per-layer +# one, so a bare "p3" would splice enc0's line 7840 into enc2's PTX. With a prefix +# enc2's names miss that table, swin_debug() returns None and recipe() below handles +# the stage itself -- which is required anyway, because enc2's block is keyed by +# (ctaid.x, ctaid.y) with a plane-z guard (see _debug_block), not enc0's flat index. +STAGES = { + # the eighteen staged A fragments the entry reads before the cut, in mma operand + # order: phase 1's (slice 0), phase 3's (slice 1), phase 5's (slice 2), m-tile major + "e2a": (7668, [f"%r{16120 + 4 * q}" for q in range(72)]), + # E6(a): the 96 C seeds of phase 7, the 64x96 f16 score bias; the last load is line 8840 + "e2e6c": (8840, sum(([f"%r{4745 + 4 * o + j}" for j in range(2)] for o in range(24)), [])), + # E6(b): phase 7's 16 A registers (four fragments, m-tile major) and its 24 B + # registers (twelve fragments, n-tile major); the last pack is line 9121 + "e2e6a": (9121, sum(([f"%r{5033 + 120 * q + o}" for o in range(4)] for q in range(4)), [])), + "e2e6b": (9121, sum(([f"%r{5287 + 10 * q + o}" for o in range(2)] for q in range(12)), [])), + # E7(g): phase 8's 48 A registers (the softmax probabilities) and its 24 B + # registers (the movmatrix transpose of phase 6's D); the last pack is line 19600 + "e2e7a": (19600, sum(([f"%r{8239 + 120 * q + o}" for o in range(4)] for q in range(12)), [])), + "e2e7b": (19600, sum(([f"%r{8533 + 10 * q + o}" for o in range(2)] for q in range(12)), [])), +} + + +def _phase_stages(): + """The accumulator registers of every phase, straight from the linearisation.""" + import re + sys.path.insert(0, os.path.dirname(os.path.abspath(__file__))) + import rr_layer_spec as spec + + path, entry = spec.resolve("enc2", None, None) + lines = open(path).read().split("\n") + first = last = None + for name, a, b in spec.find_entries(lines): + if name == entry: + first, last = a, b + break + stmts, _ = spec.linearise(lines, first, last) + phases = spec.build_phases(stmts, spec.collect_mma(stmts, spec.track_weights(stmts, entry))) + out = {} + for p in phases: + i = p.mma[-1].line + while not lines[i - 1].rstrip().endswith(";"): + i += 1 + regs = [] + for m in p.mma: + regs += [r.strip() for r in m.D.split(",")] + out[f"e2p{p.idx}"] = (i, regs) + return out + + + +def stages(): + """Every stage this layer can capture: the operand stages above plus the phases.""" + if "e2p1" not in STAGES: + STAGES.update(_phase_stages()) + return STAGES + + + + +def recipe(): + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + if stage: + if stage not in stages(): + sys.exit(f"swin_enc2: no debug stage {stage!r} (have {', '.join(sorted(stages()))})") + line, regs = stages()[stage] + return dict(file=FILE, debug=(line, regs), debug_block=_debug_block) + return dict(file=FILE, cut_call=CUT_CALL, call=_call(), extern=_extern()) diff --git a/kernels/rr/swin_enc3_recipe.py b/kernels/rr/swin_enc3_recipe.py new file mode 100755 index 0000000..098663f --- /dev/null +++ b/kernels/rr/swin_enc3_recipe.py @@ -0,0 +1,320 @@ +#!/usr/bin/env python3 +"""Mirror-cut splice for cuda_dldn_engine_swin_enc3_kernel. + +`recipe()` is what kernels/tex/make_ptx.py calls for this layer (see its +`kernel_spec`): it returns the recipe dict that replaces NVIDIA's 936 mma of +48 phases with one `call.uni` into kernels/rr/rrswin_enc3.hip. Without +D4R_RRSWIN_DEBUG in the environment it returns the cut; with +D4R_RRSWIN_DEBUG=w it returns make_ptx.py's `debug` recipe instead, which +keeps NVIDIA's whole body and stores phase n's accumulator registers -- that is +the oracle kernels/rr/rrswin_enc3.hip is checked against. + +Layer facts (kernels/rr/rrswin_enc3_epilogues.md, `python3 kernels/rr/rr_layer_spec.py enc3`): + + * grid (21, 13, 1) x block (32, 1, 4): four waves per block, `%tid.z` in 0..3. + The waves are not redundant -- each reads its own 24576-byte slice of the + weight image (s9765 `mul.lo.s32 %r21780, %r12, 12288` -> `mul.wide.u32 + %rd406, %r21780, 2`), so the oracle's per-block debug slots must be + wave-distinct (see debug_block). + * parameter block 144 bytes; the weight image (arg040) is 315732 bytes. + * the shared arena `_ZZ...smem` is 12800 bytes. The mma region rewrites it + (E10 stages P11..P14's A operand, E46 stages P47's), and E48 -- which stays + in PTX -- reads *other waves'* E48(a) rows out of it, so the body may use + the whole array as scratch: E48 writes every word it later reads. + +Cut ABI. The mma region is statements s6124-s16860, at file lines 9812-41980 +of 0016-PREPASS_ENTRYPOINT_NAME.ptx; an mma occupies four physical lines, so +`cut_call` spans 9812..(41980+4). Both numbers are re-derived from the module +below rather than transcribed, so they cannot drift. + +Registers crossing the cut *in*: nothing. The 24 staged A fragments are read +into registers at lines 9771-9794, immediately before the first mma, and the +body is free to re-read them out of the arena at `smem + 16*laneid + 512*i` +(the arena still holds them: its next writer is E10, s10491). The B operands +are loaded from the weight image inside the region and the C seeds are either +zero or a previous phase's accumulator, so both are recomputable. That keeps +the parameter list at the three pointers every layer shares. + +Registers crossing the cut *out*: eight, four of them phase 48's last two +accumulator pairs (%r23106/%r23107 and %r23116/%r23117, the D registers of P48's +mma 6 and 7, stored by E48 at s41999/42004/42018/42021). The other four are +not accumulators and rr_layer_spec.py's "returns" line misses them because it +only looks at mma destinations: + + * %r22182, %r22183 -- the (ex, ey) extents, re-loaded from `param_0+0` inside + E46 (s16487) and read by E48's bounds tests (s42050, s42052, s42263...). The + splice re-loads them instead of the body returning them. + * %r23356 -- `%tid.z << 4`, built inside E47 (s41894) and read by E48(a) + (s41993). The splice re-derives it from `%tid.z`. + * %r23368 -- the shared arena's base address (s41891), read by E48(a) at + s41998 and s42017. The splice re-materialises the symbol. + +The four accumulators cannot travel as `call.uni` return values (ZLUDA lowers +those to the function's LLVM return type -- llvm_zluda/ptx/src/pass/llvm/ +emit.rs, emit_call: one value, or an get_or_create_struct_type struct for +several, distributed with LLVMBuildExtractValue; there is no .param-space object +behind them, so an N x i32 C++ struct return lowers to an sret pointer, which +is a different LLVM signature and will not link). They go through shared +memory instead, in the last 512 bytes of the arena, which E48 never touches +(its own window ends at word 397, byte 1588). +""" + +import os +import re +from pathlib import Path + +FILE = "0016-PREPASS_ENTRYPOINT_NAME.ptx" +ENTRY = "cuda_dldn_engine_swin_enc3_kernel" +SMEM = "_ZZ33cuda_dldn_engine_swin_enc3_kernel33DldnEngineSwinEncParamsStructBaseE4smem" +SMEM_BYTES = 12800 + +CALLEE = "d4r_swin_enc3" + +# --------------------------------------------------------------------------- +# The four accumulators that cross the cut back, and the three shared pointers. +# +# An mma statement is four physical lines (`mma.sync... {d},`, the A, the B and +# the C operand lines, the last ending in `;`). D2R has REG_EXT_REGS mapping +# register name -> (phase, chain index, half) for every mma destination; the +# entries below are P48's chains 2 and 3, i.e. the last two of its eight mma. +RET_REGS = ["%r23106", "%r23107", "%r23116", "%r23117"] +RET_SLOT = SMEM_BYTES - 4 * len(RET_REGS) * 32 # the last 512 bytes: 4 b32 per lane + +EXTERN = f""".extern .func {CALLEE} +( +\t.param .b64 d4r_w, .param .b64 d4r_v, .param .b32 d4r_s +) +; +""" + + +def module_text(): + """The corpus module make_ptx.py will splice. D4R_DLSS_PTX_DIR is what + kernels/build.sh hands both of them (RR_PTX_DIR).""" + d = Path(os.environ.get("D4R_DLSS_PTX_DIR", Path.home() / ".cache/d4r-rr-corpus")) + return (d / FILE).read_text() + + +def statements(lines): + """(line number, text) of every statement of the entry body, in the same + linearisation rr_layer_spec.py documents: a line that is neither blank nor + a bare `//` comment starts a statement, and an `mma.sync` -- this entry's + only multi-line statement, four physical lines -- is joined into one + statement numbered at its first line.""" + out = [] + i = 0 + while i < len(lines): + ln = lines[i] + if not ln.strip() or ln.strip() == "//": + i += 1 + continue + if ln.startswith("mma.sync"): + start = i + while not lines[i].rstrip().endswith(";"): + i += 1 + out.append((start + 1, " ".join(p.strip() for p in lines[start:i + 1]))) + i += 1 + continue + out.append((i + 1, ln)) + i += 1 + return out + + +RE_MMA = re.compile(r"^mma\.sync\.aligned\.m16n8k32\.row\.col\.f16\.e4m3\.e4m3\.f16 " + r"\{([^}]*)\}, \{([^}]*)\}, \{([^}]*)\}, \{([^}]*)\};?$") + + +def phases(lines): + """[(first line, last mma line, [(D regs, C regs)])] over the entry, as + physical lines of the module file. + + Two mma belong to the same phase iff no other statement separates them -- + NVIDIA emits one contiguous mma block per GEMM, so the gaps between those + blocks are exactly the epilogues.""" + stmts = statements(lines) + idx = [i for i, (_, t) in enumerate(stmts) if RE_MMA.match(t)] + out = [] + for j, i in enumerate(idx): + if j == 0 or i != idx[j - 1] + 1: + out.append([stmts[i][0], stmts[i][0], []]) + m = RE_MMA.match(stmts[i][1]) + out[-1][1] = stmts[i][0] + out[-1][2].append((tuple(r.strip() for r in m.group(1).split(",")), + tuple(r.strip() for r in m.group(4).split(",")))) + return out + + +def accumulators(mmas): + """The D pairs a phase's accumulators end up in: the last mma of every + accumulator chain, in chain order. + + A banded phase (P10, P15..P45, P47, P48) chains several mma into one output + tile, so its intermediate D registers are overwritten by the next k-step and + no native body reproduces them -- only the surviving accumulators are + comparable. The chain partition is rr_layer_spec.chains_of's: an mma joins + the chain that produced one of its C registers, otherwise it starts one.""" + owner = {} + chains = [] + for dregs, cregs in mmas: + hit = {owner[r] for r in cregs if r in owner} + ci = hit.pop() if len(hit) == 1 else (chains.append([]) or len(chains) - 1) + chains[ci].append(dregs) + for r in dregs: + owner[r] = ci + return [c[-1] for c in chains] + + +def cut_range(lines): + """(first mma's line, last mma's line + 4): make_ptx.py splices + `lines[:before-1] + call + lines[after-1:]`, so the region removed is the + first mma's line through the last mma's fourth (statement-terminating) + line, and `lines[after-2]` must end in `;`.""" + ph = phases(lines) + assert len(ph) == 48, f"enc3: {len(ph)} phases, expected 48" + return ph[0][0], ph[-1][1] + 4 + + +def entry_lines(lines): + """Every line of the module up to the entry's closing brace. The slice + starts at line 0 so the line numbers phases() derives are the module's own + physical lines, which is what make_ptx.py's cut_call and debug recipes + index. A `}` alone on a line also closes the epilogues' `{ cvt ... ;` + blocks, so the extent is found by brace depth from the entry's opening + brace, exactly as make_ptx.py does.""" + start = next(i for i, ln in enumerate(lines) if ln.startswith(f".visible .entry {ENTRY}(")) + b0 = next(i for i in range(start + 1, len(lines)) if lines[i].strip() == "{") + depth = 0 + for i in range(b0, len(lines)): + depth += lines[i].count("{") - lines[i].count("}") + if i > b0 and depth == 0: + return lines[:i] + raise SystemExit("enc3: entry closing brace not found") + + +def call(): + """The splice: hand the callee the weight image, the parameter block and the + arena's base address; read the four accumulators back out of the arena and + re-materialise the four values E48 reads that were computed inside the + region.""" + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin2+{4 * i}];" for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<3>; +.reg .b64 %rswinp<2>; +.param .b64 pw; +.param .b64 pv; +.param .b32 ps; +ld.param.u64 %rswinp0, [{ENTRY}_param_0+40]; +mov.b64 %rswinp1, {ENTRY}_param_0; +mov.u32 %rswin0, {SMEM}; +add.s32 %rswin1, %rswin0, {RET_SLOT}; +st.param.b64 [pw+0], %rswinp0; +st.param.b64 [pv+0], %rswinp1; +st.param.b32 [ps+0], %rswin0; +\tcall.uni {CALLEE}, (pw, pv, ps); +mad.lo.s32 %rswin2, %laneid, {4 * len(RET_REGS)}, %rswin1; +{gets} +// E48 reads these four inside the cut and cannot recompute them. +mov.b64 %rswinp0, {ENTRY}_param_0; +ld.param.v2.u32 {{%r22182, %r22183}}, [%rswinp0+0]; +mov.u32 %rswin2, %tid.z; +shl.b32 %r23356, %rswin2, 4; +mov.u32 %r23368, {SMEM}; +}}""" + + +# --------------------------------------------------------------------------- +# debug oracle: keep NVIDIA's body, store one phase's accumulators in the plane +# arena past everything the kernel writes. + +DEBUG_BASE = 4194304 # bytes into arg048 past everything the kernel writes + + +def debug_base(): + """Byte offset into the plane arena (arg048) where a stage's payload lands. + + NOT the shared 46,000,000: enc3's arena starts at byte 37,683,200 of a + 65,945,600-byte allocation, so only 28,262,400 bytes exist and 46,000,000 is + past the end of it. Measured: with the base at 524,288 the payload window + comes back byte-identical to the plain translated run -- something later in + the frame rewrites arena bytes 524,288..2,473,984, so a stage store there is + destroyed before the dump is taken. 4,194,304 is above that window, and + 4 MiB + 64 * 16384 = 5,242,880 stays inside the arena. The output buffer + (param+56, arena+1,884,160) is below the base, so the surface comparison is + unaffected. kernels/rr/rrswin_enc3.hip's debug_store uses the same default + and honours D4R_RRSWIN_DEBUG_BASE.""" + return int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", DEBUG_BASE)) + + +DEBUG_SLOT = 8192 # the per-block slot floor (32 lanes x 64 registers x 4 bytes) +GRID_X = 21 # grid (21, 13, 1) +WAVES = 4 # block (32, 1, 4) + + +def debug_slot(nregs): + """Per-block slot for a stage of NREGS registers: 32 lanes x NREGS x 4 bytes, at least + DEBUG_SLOT, rounded up to a power of two so the splice's `shl` can form block * slot.""" + want = max(DEBUG_SLOT, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +def debug_block(regs): + """PTX that stores REGS (u32 each) to plane arena + DEBUG_BASE + block*slot + lane*len*4. + + This layer runs four waves per block and each reads a different slice of the + weight image, so the slot index carries `%tid.z` too: block = + (ctaid.x + 21*ctaid.y)*4 + tid.z, and only the first 64 of those are stored. + kernels/rr/rrswin_enc3.hip's debug_store computes the same index. + """ + slot = debug_slot(len(regs)) + base = debug_base() + stores = "\n".join( + f" @%pdbg1 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(regs[i * 4:i * 4 + 4])}}};" + for i in range((len(regs) + 3) // 4)) + return f"""// d4r debug stage +{{ +.reg .pred %pdbg<2>; +.reg .b32 %rdbg<8>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{ENTRY}_param_0+48]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mad.lo.s32 %rdbg3, %rdbg2, {GRID_X}, %rdbg1; +mov.u32 %rdbg7, %tid.z; +mad.lo.s32 %rdbg3, %rdbg3, {WAVES}, %rdbg7; +setp.lt.u32 %pdbg1, %rdbg3, 64; +shl.b32 %rdbg4, %rdbg3, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg7, %rdbg6, {base}; +cvt.u64.u32 %rddbg2, %rdbg7; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +def debug_stages(lines): + """w -> (line to insert the store after, registers to store), for n = 1..48. + + The insert point is the fourth line of the phase's last mma -- the line the + `;` is on. The registers are the phase's surviving accumulators (see + accumulators()), which for a single-k-step phase is every mma's D pair in + mma order: m-tile major, n-tile minor, the (row g, row g+8) pair each mma + writes. kernels/rr/rrswin_enc3.hip emits the same order.""" + out = {} + for n, (first, last, mmas) in enumerate(phases(lines), 1): + out[f"w{n}"] = (last + 4, [r for pair in accumulators(mmas) for r in pair]) + return out + + +def recipe(): + lines = entry_lines(module_text().split("\n")) + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + if stage: + stages = debug_stages(lines) + if stage not in stages: + raise SystemExit(f"swin_enc3_recipe: no debug stage {stage!r} " + f"(have w1..w{max(int(k[1:]) for k in stages)})") + return dict(file=FILE, debug=stages[stage], debug_block=debug_block) + first, after = cut_range(lines) + return dict(file=FILE, cut_call=(first, after), extern=EXTERN, call=call()) \ No newline at end of file diff --git a/kernels/rr/swin_enc4_recipe.py b/kernels/rr/swin_enc4_recipe.py new file mode 100755 index 0000000..5d89f6d --- /dev/null +++ b/kernels/rr/swin_enc4_recipe.py @@ -0,0 +1,368 @@ +#!/usr/bin/env python3 +"""The mirror cut for cuda_dldn_engine_swin_enc4_kernel (Ray Reconstruction denoiser, encoder 4). + +make_ptx.py's per-layer hook imports this module by path and returns whatever `recipe()` gives, +so the module is self-contained: it duplicates the small generator logic it needs instead of +importing make_ptx.py, and it derives every register list from the corpus PTX rather than trusting +a hand-copied number. Re-derive with + + python3 kernels/rr/rr_layer_spec.py enc4 + +and cross-check the printed `cut ABI` block against the constants below. + +What the cut is +--------------- +The layer is one 62-phase mma region: the ten-phase stem (phases 1-10, two chains of five 96x32x32 +GEMMs over the shared-staged block input), the 64x96 score GEMM and its cubic-exponent softmax +(11-12), the sixteen 16x160 attention projections with their row-RMS norm (13-20), forty MLP +phases in twenty banded pairs (21-60) and the patch merge (61-62). `rr_layer_spec.py enc4` puts the +region at statements s7554-s21344, file lines 11883-52671: 1386 mma in 62 phases. + +NVIDIA's texture prologue (the input plane read, the e4m3 requantisation, the 30-fragment +shared-memory staging and the first weight loads) and the surface epilogue (E62: the 3x3 texture +gather and the three sust.b writes) stay in PTX; only the mma region becomes + + call.uni d4r_swin_enc4, (...) + +`kernels/rr/rrswin_enc4.hip` is the callee. + +The callee's arguments +---------------------- +The prologue leaves the cut with + + * 24 A registers -- the six staged A fragments of phase 1, in the first mma's operand order + (%r11754..%r11757, %r11774..%r11777, %r11794..%r11797, %r11814..%r11817, %r11834..%r11837, + %r11854..%r11857). These are shift group 0's fragments. Groups 1..4 (what phases 3/4, 5/6, + 7/8 and 9/10 read) are *not* among the live-out registers: the callee reads them from the + shared arena itself, exactly as the spliced PTX did, which is why the arena's address is + handed over as well. + * 1 C register -- %r11676, which the prologue sets to 0 at line 11871 (s7547) and which is every + phase 1/2 mma's C operand. The later phases' C operands are the previous phase's D registers, + all inside the cut. + * arg040, the prepared weight image (%rd2), and the parameter block (%rd9). + * the address of the shared arena, so the callee can both read the staged A fragments and hand + its accumulators back. + +Why the accumulators come back through shared memory +--------------------------------------------------- +Exactly as in enc0 (see the comment block above SWIN_A_REGS in kernels/tex/make_ptx.py): ZLUDA +lowers `call.uni`'s return values to the callee's *LLVM* return type, so there is no .param-space +object behind them and the callee would read 0x0 in every return slot. enc4 has five live-out +registers + + %r29719 the x extent, ld.param.v2.u32 at line 50892 (param_0+0) + %r31372 phase 62's D pair + %r31382 phase 62's D pair + %r31608 %tid.z + %r31615 mov.u32 of the shared arena symbol, line 52567 + +so the callee writes five words per lane at `scratch + 20*laneid + 4*i` and the splice reads them +back with five ld.shared.b32. 5 * 32 lanes * 4 bytes = 640 bytes. enc4 has exactly one shared +array (16384 bytes, `_ZZ...smem`), and unlike enc0's `input_tensor` it is *not* dead: phases 13-20 +and 61 still use it. The callee therefore writes the five words as its very last act, at arena +offset 0 (shift group 0's staging slots, which nothing reads after phase 10), and the splice reads +them back before E62 issues a single shared store. The read-back is therefore ordered against +every other user of the arena by the cut itself. +""" + +import os +import re + +# --------------------------------------------------------------------------- +# The corpus module. make_ptx.py resolves it by entry name over the whole directory, so `file` is +# only a hint for the human reader; the path is used here to derive the debug stages. +FILE = "0017-PREPASS_ENTRYPOINT_NAME.ptx" +ENTRY = "cuda_dldn_engine_swin_enc4_kernel" + +# `cut s7554-s21344 (file lines 11883-52671)`: 11883 is the first mma's first line, 52671 the last +# mma's last line, and make_ptx's `after` is the first line it keeps. +CUT_FIRST = 11883 +CUT_AFTER = 52672 + +# The 24 A registers the prologue leaves live, in the first mma's operand order: six fragments of +# four b32, m-tile major. +A_REGS = [ + "%r11754", "%r11755", "%r11756", "%r11757", + "%r11774", "%r11775", "%r11776", "%r11777", + "%r11794", "%r11795", "%r11796", "%r11797", + "%r11814", "%r11815", "%r11816", "%r11817", + "%r11834", "%r11835", "%r11836", "%r11837", + "%r11854", "%r11855", "%r11856", "%r11857", +] + +# The one C seed register (%r11676 = 0). +C_REGS = ["%r11676"] + +# The five live-out registers, in the order the callee writes them. +RET_REGS = ["%r29719", "%r31372", "%r31382", "%r31608", "%r31615"] +RET_STRIDE = 4 * len(RET_REGS) + +# The only shared array in the entry: 16384 bytes, live across the cut (see the module docstring). +SCRATCH = "_ZZ33cuda_dldn_engine_swin_enc4_kernel33DldnEngineSwinEncParamsStructBaseE4smem" + +CALLEE = "d4r_swin_enc4" + +# --------------------------------------------------------------------------- +# Debug-store geometry, identical to the enc0 splice's (SWIN_DEBUG_BASE / SWIN_DEBUG_SLOT in +# make_ptx.py) so a payload region can be compared the same way: bytes into the plane arena the +# kernel never writes, plus block*slot plus lane*len(regs)*4. +# +# enc4's plane arena is arg008, not enc0's arg048: the weight image is arg040 and there is no +# arg048 among this kernel's resources. The launch dump writes arg008 as a 65,945,600-byte file +# whose index 0 is `arena - 0x25bc000`, so an arena offset A appears at dump index A + 39,567,360 +# and only arena offsets below 26,378,240 are observable at all. +# +# The payload sits well inside the arena and 64 slots deep (BLOCK_LIMIT slots would not fit for the +# widest stage: 160 registers at a 32,768-byte slot). D4R_RRSWIN_DEBUG_BASE moves it; both sides +# read the same variable, so a sweep is automatically consistent. +PLANE_ARG = 8 +DEBUG_BASE = int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", "20000000")) +DEBUG_BLOCKS = 64 +DEBUG_SLOT_FLOOR = 8192 + +# enc4 is one 8x8 token patch per block over an 80x46 token grid, four waves per block (tid.z bounds +# to 0..3), so grid (11, 7, 1) x block (32, 1, 4). The four waves of a block compute *different* +# results (each reads its own 27648-byte weight slice and its own staging slots), so the wave has to +# be part of the slot index. The slot is `ctaid.x + 32*ctaid.y + 256*tid.z`: injective over the +# launch's 11x7x4 = 308 waves and, unlike enc0's 64-block scheme, it keeps every wave's registers +# addressable. Only the first DEBUG_BLOCKS slots are compared, because the arena cannot hold all +# 1024 of them; blocks past the limit are not stored by either side. +SLOT_X = 32 +SLOT_Y = 8 +SLOT_Z = 4 +BLOCK_LIMIT = SLOT_X * SLOT_Y * SLOT_Z + + +def debug_slot(nregs): + """Per-block slot for NREGS registers: 32 lanes x NREGS x 4 bytes, at least DEBUG_SLOT_FLOOR, + rounded up to a power of two (the splice's `shl` forms block*slot with a shift).""" + want = max(DEBUG_SLOT_FLOOR, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +# --------------------------------------------------------------------------- +# A small PTX lineariser, duplicating rr_layer_spec.py's convention (a statement ends at its `;`, +# a wrapped `{ ... }` scope is a delimiter but an operand register list is not, blank/`//`/`.reg` +# lines are not statements). Only what the debug stages need is parsed: the runs of adjacent mma. +RE_ENTRY = re.compile(r"\.entry\s+([\w$]+)\s*\(") +RE_MMA = re.compile(r"^mma\.sync") + + +def _entry_lines(): + """The entry's body lines of the corpus module, or None when the corpus is not reachable.""" + roots = [] + if os.environ.get("D4R_DLSSD_PTX_DIR"): + roots.append(os.environ["D4R_DLSSD_PTX_DIR"]) + roots.append(os.path.expanduser("~/.cache/d4r-rr-corpus")) + roots.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "extracted", "rr")) + for root in roots: + path = os.path.join(root, FILE) + if os.path.isfile(path): + lines = open(path).read().split("\n") + for index, line in enumerate(lines): + if not RE_ENTRY.search(line) or ENTRY not in line: + continue + depth, started = 0, False + for j in range(index, len(lines)): + depth += lines[j].count("{") - lines[j].count("}") + if "{" in lines[j]: + started = True + if started and depth == 0: + return lines[index:j + 1], index + 1 + return None, None + return None, None + + +def _mma_runs(body, first_line): + """(last_line, [D regs]) for every maximal run of adjacent mma statements of the entry whose + body starts at file line `first_line`. + + `last_line` is the file line the run's final mma ends on -- the line the debug splice is + inserted after. D regs are the two b32 each mma writes, in statement order; that is the + register list the oracle stores for a phase and the list the native body's own debug_store + reproduces in the same order.""" + runs = [] + cur = None + buf = None + for index, raw in enumerate(body): + line = first_line + index + s = raw.strip() + if not s or s.startswith("//") or s.startswith("."): + continue + while s and s[0] in "{}" and s[1:2] != "%": + s = s[1:].lstrip() + while s.endswith("}") and s[:-1].rstrip().endswith(";"): + s = s[:-1].rstrip() + if not s: + continue + if buf is None: + buf = s + else: + buf += " " + s + while buf is not None and buf.endswith(";"): + text, buf, last = buf[:-1].strip(), None, line + if RE_MMA.match(text): + groups = re.findall(r"\{([^}]*)\}", text) + dest = re.findall(r"%r\d+", groups[0]) if groups else [] + if cur is None: + cur = [last, []] + cur[0] = last + cur[1].extend(dest) + elif cur is not None: + runs.append(tuple(cur)) + cur = None + if cur is not None: + runs.append(tuple(cur)) + return runs + + +def _stage_lines(): + """[(line, D registers)] per phase: the line the oracle's debug store goes after, and the + phase's D registers in mma statement order.""" + body, first = _entry_lines() + if body is None: + return [] + entry = next(i for i, line in enumerate(body) if line.startswith(".visible .entry")) + return _mma_runs(body[entry + 1:], first + entry + 1) + + +# --------------------------------------------------------------------------- +# The splice and its declaration +def cut_call(): + """The PTX that replaces the mma region. + + The callee is handed the staged A fragments, the C seed, the weight image, the parameter block + and the address of the shared arena; it writes the five live-out registers into the arena and + this splice reads them back into the epilogue's registers.""" + args = A_REGS + C_REGS + decl = "\n".join(f"\t.param .b32 p{i};" for i in range(len(args))) + store = "\n".join(f"\tst.param.b32 [p{i}+0], {r};" for i, r in enumerate(args)) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store += ("\n\tst.param.b64 [pw+0], %rd2;\n\tst.param.b64 [pv+0], %rd9;" + f"\n\tmov.u32 %rswin0, {SCRATCH};" + "\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join([f"p{i}" for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin1+{4 * i}];" for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store} +\tcall.uni {CALLEE}, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {RET_STRIDE}, %rswin0; +{gets} +}}""" + + +def cut_extern(): + args = ", ".join([f".param .b32 d4r_a{i}" for i in range(len(A_REGS) + len(C_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func {CALLEE}\n(\n\t{args}\n)\n;\n" + + +# --------------------------------------------------------------------------- +# The oracle's debug stage: keep NVIDIA's whole body and store one phase's D registers past the +# end of the plane arena the kernel writes, so the launch dump holds the translated values for a +# block/lane. Built with -DD4R_RRSWIN_DEBUG_STAGE= (kernels/build.sh rrswin, D4R_TEX_CFLAGS), +# kernels/rr/rrswin_enc4.hip stores the same registers of its own phase n in the same order, so the +# two dumps compare byte for byte. +def debug_block(regs): + """PTX that stores REGS (u32 each) to plane arena + DEBUG_BASE + block*slot + lane*len(regs)*4. + + Works on either side of the splice: it is inserted into NVIDIA's own PTX for the reference and + reproduced by the native body's debug flag, and both sides compute the same slot index. The + predicate is `ctaid.x < SLOT_X && ctaid.y < SLOT_Y && tid.z < SLOT_Z && slot < DEBUG_BLOCKS`, + so the mapping stays injective however the kernel is launched. The DEBUG_BLOCKS term is what + keeps the region inside arg008: the arena cannot hold all BLOCK_LIMIT slots of the widest + stage, and both sides drop the rest rather than write past the end.""" + slot = debug_slot(len(regs)) + # `st.global.v4.u32` needs a multiple of four operands, and stage e4a stores 25 registers + # (24 A + the C seed); pad the tail by repeating the last register. The comparison reads + # only the first len(regs) words, so the padding is invisible on both sides. + padded = list(regs) + [regs[-1]] * (-len(regs) % 4) + stores = "\n".join( + f"@%pdbg5 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(padded[i * 4:i * 4 + 4])}}};" + for i in range(len(padded) // 4)) + return f"""// d4r debug stage +{{ +.reg .pred %pdbg<7>; +.reg .b32 %rdbg<8>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{ENTRY}_param_0+{PLANE_ARG}]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mov.u32 %rdbg3, %tid.z; +setp.lt.u32 %pdbg1, %rdbg1, {SLOT_X}; +setp.lt.u32 %pdbg2, %rdbg2, {SLOT_Y}; +setp.lt.u32 %pdbg3, %rdbg3, {SLOT_Z}; +and.pred %pdbg4, %pdbg1, %pdbg2; +and.pred %pdbg5, %pdbg4, %pdbg3; +shl.b32 %rdbg4, %rdbg2, 5; +add.s32 %rdbg4, %rdbg4, %rdbg1; +shl.b32 %rdbg5, %rdbg3, 8; +add.s32 %rdbg4, %rdbg4, %rdbg5; +setp.lt.u32 %pdbg6, %rdbg4, {DEBUG_BLOCKS}; +and.pred %pdbg5, %pdbg5, %pdbg6; +shl.b32 %rdbg4, %rdbg4, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg6, %rdbg6, {DEBUG_BASE}; +cvt.u64.u32 %rddbg2, %rdbg6; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +def _stage_table(): + """{stage name: (line, D registers)} for every phase of the entry. + + Every name carries the `e4` prefix. make_ptx.py's swin_debug() is consulted *before* this + recipe, and its unkeyed SWIN_DEBUG_STAGES table holds enc0's `a`, `p1`..`p7` with enc0's line + numbers and enc0's param_0+48 plane address; an unprefixed name would silently splice enc0's + registers into enc4's module and store them to a parameter enc4 never had. The keyed + `("enc4", name)` hook (swin_enc4_debug_stages.py) is checked first, and an unrecognised name + falls through here -- so `e4p*` is what actually reaches this table. + + `p` is phase n's D registers (however many the phase has) in mma statement order; `e4a` is + the staged A operand the callee is handed, which pins the prologue independently of the body's + arithmetic. + + Every stage's register count is padded to a multiple of four. The lane stride is + `len(regs)*4`, and the store is a `st.global.v4.u32`, which needs 16-byte alignment: with 25 + registers the stride is 100 bytes, so every odd lane's store is misaligned and the hardware + drops it (measured: the oracle stored zeros for odd lanes while the native side's scalar + stores wrote real values). Phase stages are already 40, 48, 96 or 160 registers wide and so + need no padding; only the 25-register `e4a` does. + """ + table = {} + stages = _stage_lines() + a_regs = A_REGS + C_REGS + table["e4a"] = (CUT_FIRST - 1, a_regs + [a_regs[-1]] * (-len(a_regs) % 4)) + for n, (line, regs) in enumerate(stages, start=1): + table[f"e4p{n}"] = (line, regs) + return table + + +def recipe(): + """The make_ptx.py spec for this layer. + + D4R_RRSWIN_DEBUG= selects the oracle build: NVIDIA's whole body with that stage's + registers stored past the plane arena. Otherwise the mirror cut, built and served.""" + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + if stage: + table = _stage_table() + if stage not in table: + raise SystemExit( + f"swin_enc4_recipe: no stage {stage!r}; known: " + ", ".join(sorted(table))) + line, regs = table[stage] + return dict(file=FILE, debug=(line, regs), debug_block=debug_block) + return dict(file=FILE, cut_call=(CUT_FIRST, CUT_AFTER), extern=cut_extern(), call=cut_call()) + + +if __name__ == "__main__": + # self-check: print the recipe and the stage table + import pprint + pprint.pprint({k: (v if k != "call" else "") for k, v in recipe().items()}) + for name, (line, regs) in sorted(_stage_table().items(), + key=lambda kv: (len(kv[1][1]), kv[0])): + print(f"{name:>4s} line {line:6d} {len(regs):3d} registers") \ No newline at end of file diff --git a/kernels/rr/swin_enc5_recipe.py b/kernels/rr/swin_enc5_recipe.py new file mode 100755 index 0000000..7d0b148 --- /dev/null +++ b/kernels/rr/swin_enc5_recipe.py @@ -0,0 +1,187 @@ +#!/usr/bin/env python3 +"""Mirror-cut splice for cuda_dldn_engine_swin_enc5_kernel. + +`recipe()` is what kernels/tex/make_ptx.py calls for this layer (see its +`kernel_spec`): it returns the recipe dict that replaces NVIDIA's mma region +with one `call.uni` into kernels/rr/rrswin_enc5.hip. + +Cut ABI (from `python3 kernels/rr/rr_layer_spec.py enc5`, cut section): + + * the mma region is statements s7554-s20065, 1306 mma in 61 phases, at file + lines 11883-50752 of 0018-PREPASS_ENTRYPOINT_NAME.ptx. An mma occupies + four physical lines, so `cut_call` ends one line *past* the last mma's + first line -- that is what make_ptx.py's `lines[after - 1:]` splice wants, + and it is the same convention the built-in enc0 entry uses (44524 + 4). + * the callee takes no operand registers. Unlike enc0 the thirty staged A + fragments are still in shared memory when the cut is taken (the PTX reads + them back into registers at lines 11835-11864, immediately before the + first mma, and never writes shared memory again until E61), so the body + re-reads them from `smem + laneid*16 + 512*i` itself. That keeps the + parameter list at the three pointers every layer shares. + * six registers cross the cut back: phase 61's four accumulators + (%r29601, %r29602, %r29611, %r29612) and the two values E61 reads that are + *computed inside* the region -- %r29781 (`%tid.z`) and %r29782 (the shared + base, line 50649). rr_layer_spec's "returns" line misses the latter two + because it only looks for mma destinations; E61 stores %r29601/%r29611 and + loads %r29782 with them, so all six have to come back. + * `call.uni` return values cannot carry them (ZLUDA lowers them to the + function's LLVM return type), so they travel through shared memory, which + E61's own shared window (at most 2832 bytes in) never touches. The return + window is the last 768 bytes of the 16384-byte array. + +Debug stages: with D4R_RRSWIN_DEBUG=w (n = 1..12) this module returns +make_ptx.py's `debug` recipe instead, keeping NVIDIA's whole body and storing +phase n's accumulator registers; kernels/rr/rrswin_enc5.hip stores the same +registers under -DD4R_RRSWIN_DEBUG_STAGE=, so the two payload regions at +plane-arena + 46,000,000 compare byte for byte. +""" + +import os + +FILE = "0018-PREPASS_ENTRYPOINT_NAME.ptx" +ENTRY = "cuda_dldn_engine_swin_enc5_kernel" +SMEM = "_ZZ33cuda_dldn_engine_swin_enc5_kernel33DldnEngineSwinEncParamsStructBaseE4smem" + +CUT_FIRST = 11883 # the first mma's line +CUT_AFTER = 50756 # the last mma's line (50752) plus its three continuation lines + +CALLEE = "d4r_swin_enc5" +EXTERN = f""".extern .func {CALLEE} +( +\t.param .b64 d4r_w, .param .b64 d4r_v, .param .b32 d4r_s +) +; +""" + +# %r29601, %r29602, %r29611, %r29612, %r29781, %r29782 -- in the order the splice reads them +RET_REGS = ["%r29601", "%r29602", "%r29611", "%r29612", "%r29781", "%r29782"] +RET_SLOT = 16384 - 4 * len(RET_REGS) * 32 # the last 768 bytes of the shared array + + +def call(): + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin2+{4 * i}];" for i, r in enumerate(RET_REGS)) + return f"""{{ +.reg .b32 %rswin<3>; +.reg .b64 %rswinp<2>; +.param .b64 pw; +.param .b64 pv; +.param .b32 ps; +ld.param.u64 %rswinp0, [{ENTRY}_param_0+40]; +mov.b64 %rswinp1, {ENTRY}_param_0; +mov.u32 %rswin0, {SMEM}; +add.s32 %rswin1, %rswin0, {RET_SLOT}; +st.param.b64 [pw+0], %rswinp0; +st.param.b64 [pv+0], %rswinp1; +st.param.b32 [ps+0], %rswin0; +\tcall.uni {CALLEE}, (pw, pv, ps); +mad.lo.s32 %rswin2, %laneid, {4 * len(RET_REGS)}, %rswin1; +{gets} +}}""" + + +# --------------------------------------------------------------------------- +# debug oracle: keep NVIDIA's body, store one stage's registers in the plane arena + +DEBUG_BASE = int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", "4000000")) + # bytes into arg048 (this layer's plane arena) the kernel + # never writes: past E60's 147,200-byte scatter and inside + # the allocation the harness dumps. Both sides take it from + # the environment, so the two payloads land at the same place. +DEBUG_SLOT = 8192 # the per-block slot floor (32 lanes x 64 registers x 4 bytes) + + +def debug_slot(nregs): + """Per-block slot for a stage of NREGS registers: 32 lanes x NREGS x 4 bytes, at least + DEBUG_SLOT, rounded up to a power of two so the splice's `shl` can form block * slot.""" + want = max(DEBUG_SLOT, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +def debug_block(regs): + """PTX that stores REGS (u32 each) to plane arena + DEBUG_BASE + block*slot + lane*len*4. + + This layer launches grid (5,3,1) x block (32,1,8), so `block = ctaid.x + 5*ctaid.y` and only + one %tid.z group fits in a slot: the store is predicated on %tid.z == 0, which is what + kernels/rr/rrswin_enc5.hip's debug_store does too. + """ + slot = debug_slot(len(regs)) + stores = "\n".join( + f"@%pdbg1 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(regs[i * 4:i * 4 + 4])}}};" + for i in range((len(regs) + 3) // 4)) + return f"""// d4r debug stage +{{ +.reg .pred %pdbg<3>; +.reg .b32 %rdbg<8>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{ENTRY}_param_0+48]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mad.lo.s32 %rdbg3, %rdbg2, 5, %rdbg1; +mov.u32 %rdbg7, %tid.z; +setp.eq.u32 %pdbg2, %rdbg7, 0; +setp.lt.u32 %pdbg1, %rdbg3, 64; +and.pred %pdbg1, %pdbg1, %pdbg2; +shl.b32 %rdbg4, %rdbg3, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg7, %rdbg6, {DEBUG_BASE}; +cvt.u64.u32 %rddbg2, %rdbg7; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +def _win_dregs(base): + """Phase 1-10's forty-eight accumulator registers: m-tile major, n-tile minor, the row pair + (row g, row g+8) each of the phase's twenty-four mma writes. The mma of m-tile mi and n-tile + nt writes base + 40*mi + 10*nt and its second register *one* further on -- the five-apart + registers the pair does not touch are dead virtuals, and a store of one of those reads back + whatever physical register the translator had left it aliased to.""" + return [f"%r{base + 40 * mi + 10 * nt + rh}" + for mi in range(6) for nt in range(4) for rh in (0, 1)] + + +def _score_dregs(): + """Phase 11's ninety-six accumulator registers: m-tile major, n-tile minor, the row pair. + Its mma j = 12*mi + nt writes %r7862 + 120*mi + 10*nt and its second register one on.""" + return [f"%r{7862 + 120 * mi + 10 * nt + rh}" + for mi in range(4) for nt in range(12) for rh in (0, 1)] + + +def _pv_dregs(): + """Phase 12's thirty-two accumulator registers: the last k-step of each of its sixteen + chains, m-tile major and n-tile minor. The chain of (mi, nt) ends at mma + j = 12*mi + 6*(nt>>1) + 4 + (nt&1), whose D pair is %r11108 + 10*j.""" + return [f"%r{11108 + 10 * (12 * mi + 6 * (nt >> 1) + 4 + (nt & 1)) + rh}" + for mi in range(4) for nt in range(4) for rh in (0, 1)] + + +# (line after which to insert, registers to store). The line is the last mma's line plus four. +STAGES = { + "w1": (12048, _win_dregs(5204)), + "w2": (12229, _win_dregs(5453)), + "w3": (12410, _win_dregs(5702)), + "w4": (12591, _win_dregs(5951)), + "w5": (12772, _win_dregs(6200)), + "w6": (12953, _win_dregs(6449)), + "w7": (13134, _win_dregs(6698)), + "w8": (13315, _win_dregs(6947)), + "w9": (13496, _win_dregs(7196)), + "w10": (13677, _win_dregs(7445)), + "w11": (14394, _score_dregs()), + "w12": (24874, _pv_dregs()), + # phase 13: its forty C seeds (%r11944 + 10*nt is row g's column pair, the + # register one on row g+8's) and its forty accumulators (%r11936 + 10*nt) + "p13c": (25621, [f"%r{11944 + 10 * nt + rh}" for nt in range(20) for rh in (0, 1)]), + "p13d": (25621, [f"%r{11936 + 10 * nt + rh}" for nt in range(20) for rh in (0, 1)]), +} + + +def recipe(): + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + if stage: + if stage not in STAGES: + raise SystemExit(f"swin_enc5_recipe: no debug stage {stage!r} (have {sorted(STAGES)})") + return dict(file=FILE, debug=STAGES[stage], debug_block=debug_block) + return dict(file=FILE, cut_call=(CUT_FIRST, CUT_AFTER), extern=EXTERN, call=call()) diff --git a/kernels/tex/make_ptx.py b/kernels/tex/make_ptx.py index 230d9ce..ec8a753 100755 --- a/kernels/tex/make_ptx.py +++ b/kernels/tex/make_ptx.py @@ -3,6 +3,7 @@ usage: make_ptx.py KERNEL OUT.ptx """ +import importlib.util import os import re import sys @@ -11,6 +12,76 @@ from pathlib import Path # PTX extracted from nvngx_dlss.dll by kernels/tools/extract_dlss_ptx.py (kernels/build.sh does this) PTX_DIR = Path(os.environ.get("D4R_DLSS_PTX_DIR", Path(__file__).resolve().parent.parent / "extracted" / "ptx")) +# Ray Reconstruction enc0 mirror cut: PTX keeps the prologue (textures, input staging, the A/B/bias +# register setup up to line 3963) and the surface epilogue (from line 44528); the 536 mma of the 22 +# phases (lines 3964-44527) become one call to the native body, which is handed the six staged A +# fragments, the four bias seeds, the weight image and the parameter block. Phase 22's eight mma each +# write a *pair* of b32 (four f16 per lane), and the epilogue's `selp` chains (stmts 15595-15609, +# 15643-15676, 15718-15720) select between the halves on `laneid & 3`, so both halves of every pair +# must cross the cut -- returning only the even halves (the previous list) left the odd ones undefined +# in the spliced PTX and made byte-exact output impossible. +# +# The eighteen accumulators come back through shared memory, not `call.uni`'s return parameters. +# ZLUDA lowers those to the *function's* LLVM return type (llvm_zluda/ptx/src/pass/llvm/emit.rs, +# emit_call: one value, or an `get_or_create_struct_type` struct for several, distributed with +# LLVMBuildExtractValue). There is no .param-space object behind them and no pointer is ever formed, +# so the callee sees 0x0 in all eighteen slots and stores through them fault the launch; an 18 x i32 +# C++ struct return lowers to an sret pointer, which is a different LLVM signature and will not link. +# +# So the callee is handed the address of `input_tensor` (3200 bytes of .shared, dead after the cut -- +# its last ld.shared is line 3938 and no register derived from its base is read past it) and writes +# the eighteen values at `base + 72*laneid + 4*i`; the spliced PTX reads them back with eighteen +# ld.shared.b32. 72 * 32 lanes = 2304 bytes, inside the 3200. Per-block LDS is what makes this safe: +# a global scratch slot would be shared by all 14973 blocks, and sizing it per block and lane +# (14973 * 32 * 72 = 34.5 MB) would not fit past the 45,219,840 arena bytes the kernel writes either. +# enc0_tail already uses this shape (d4r_enc0_tail takes the shared base as a plain b32 argument). +SWIN_A_REGS = ["%r120", "%r136", "%r128", "%r144", "%r152", "%r168", "%r160", "%r176", + "%r184", "%r200", "%r192", "%r208", "%r216", "%r232", "%r224", "%r240", + "%r246", "%r257", "%r253", "%r1042", "%r1079", "%r1080", "%r1081", "%r1082"] +SWIN_BIAS_REGS = ["%r1086", "%r1096", "%r1106", "%r1116"] +SWIN_RET_REGS = ["%r17597", "%r18203"] + sum( + ([f"%r{d}", f"%r{d + 1}"] for d in range(17634, 17706, 10)), []) + +# the .shared scratch the accumulators cross the cut through: 18 b32 per lane, 72 bytes apart +SWIN_RET_SCRATCH = "_ZZ33cuda_dldn_engine_swin_enc0_kernel35DldnEngineFusedSwinEnc0ParamsStructE12input_tensor" +SWIN_RET_STRIDE = 4 * len(SWIN_RET_REGS) + +SWIN_P2_A_REGS = ["%r1207", "%r1208", "%r1209", "%r1210", "%r1247", "%r1248", "%r1249", "%r1250", + "%r1287", "%r1288", "%r1289", "%r1290", "%r1327", "%r1328", "%r1329", "%r1330", + "%r1367", "%r1368", "%r1369", "%r1370", "%r1407", "%r1408", "%r1409", "%r1410"] + +def swin_cut_call(): + """The native body is handed the staged A fragments, the four bias seeds, the weight image, the + parameter block and the address of the shared scratch; it writes the eighteen accumulators there + and this splice reads them back into the epilogue's registers.""" + args = SWIN_A_REGS + SWIN_BIAS_REGS + decl = "\n".join(f"\t.param .b32 p{i};" for i in range(len(args))) + store_args = "\n".join(f"\tst.param.b32 [p{i}+0], {r};" for i, r in enumerate(args)) + decl += "\n\t.param .b64 pw;\n\t.param .b64 pv;\n\t.param .b32 ps;" + store_args += ("\n\tst.param.b64 [pw+0], %rd367;\n\tst.param.b64 [pv+0], %rd368;" + f"\n\tmov.u32 %rswin0, {SWIN_RET_SCRATCH};" + "\n\tst.param.b32 [ps+0], %rswin0;") + hel = ", ".join([f"p{i}" for i in range(len(args))] + ["pw", "pv", "ps"]) + gets = "\n".join(f"\tld.shared.b32 {r}, [%rswin1+{4 * i}];" + for i, r in enumerate(SWIN_RET_REGS)) + return f"""{{ +.reg .b32 %rswin<2>; +{decl} +{store_args} +\tcall.uni d4r_swin_enc0, ({hel}); +\tmad.lo.s32 %rswin1, %laneid, {SWIN_RET_STRIDE}, %rswin0; +{gets} +}}""" + + +def swin_cut_extern(): + args = ", ".join([f".param .b32 d4r_a{i}" for i in range(len(SWIN_A_REGS) + len(SWIN_BIAS_REGS))] + + [".param .b64 d4r_w", ".param .b64 d4r_v", ".param .b32 d4r_s"]) + return f".extern .func d4r_swin_enc0\n(\n\t{args}\n)\n;\n" + + + + ENC0_TAIL = """{{ .param .b32 q0; st.param.b32 [q0+0], {smem}; @@ -33,6 +104,30 @@ ret; }} """ +SWIN_EXTERN = """.extern .func d4r_swin_enc0 +( + .param .b64 d4r_e0, .param .b32 d4r_e1, .param .b32 d4r_e2 +) +; +""" + +# NVIDIA's own entry takes the address of its parameter block (`mov.b64 %rd368, `), so the +# native body is handed that pointer plus the two shared arrays' addresses. The registers are ones the +# entry already declares; the body between them is deleted. +SWIN_STUB = """mov.b64 %rd376, cuda_dldn_engine_swin_enc0_kernel_param_0; +mov.u32 %r18228, _ZZ33cuda_dldn_engine_swin_enc0_kernel35DldnEngineFusedSwinEnc0ParamsStructE11input_noise; +mov.u32 %r18227, _ZZ33cuda_dldn_engine_swin_enc0_kernel35DldnEngineFusedSwinEnc0ParamsStructE12input_tensor; +{ + .param .b64 q0; + st.param.b64 [q0+0], %rd376; + .param .b32 q1; + st.param.b32 [q1+0], %r18228; + .param .b32 q2; + st.param.b32 [q2+0], %r18227; + call.uni d4r_swin_enc0, (q0, q1, q2); +} +ret;""" + KERNELS = { # enc0: cut after the bar.warp.sync that ends the smem staging of the GEMM A operand "rrlite_enc0_4x4_mvhi_hdr_folded": dict( @@ -83,6 +178,15 @@ KERNELS = { call.uni d4r_dec0_head, (q0, q1, q2, q3, q4, q5, q6); }""", ), + # Ray Reconstruction denoiser Swin layers (kernels/rr/rrswin_*.hip): the whole entry body of the + # module's Shwin entry is replaced by a call into the native implementation, linked in as bitcode. + # PREPASS_ENTRYPOINT_NAME, the module's other entry, is left untouched. + "cuda_dldn_engine_swin_enc0_kernel": dict( + file="0013-PREPASS_ENTRYPOINT_NAME.ptx", + replace_body=True, + extern=SWIN_EXTERN, + stub=SWIN_STUB, + ), # post and downsample: only the formatted surface stores become native (inline format conversion # instead of ZLUDA's per-channel surface_formatted_store_bits calls) "rrlite_post_3_2_mvhi_hdr_folded": dict(file="dlss-0176-00.ptx", sust=True, extern=""), @@ -497,7 +601,193 @@ def enc0_variant(name): tail=ENC0_TAIL.format(**regs)) +SWIN_DEBUG_BASE = 46000000 # bytes into the plane arena (arg048) the kernel never writes +SWIN_DEBUG_SLOT = 8192 # the per-block slot floor: 32 lanes x 64 registers x 4 bytes + + +def swin_debug_slot(nregs): + """Per-block slot for a stage of NREGS registers: 32 lanes x NREGS x 4 bytes, at least + SWIN_DEBUG_SLOT, rounded up to a power of two so the splice's `shl` can form block * slot.""" + want = max(SWIN_DEBUG_SLOT, 32 * nregs * 4) + return 1 << (want - 1).bit_length() + + +def swin_p5_regs(): + """Phase 5's 48 mma D pairs in the mma statement order: m-tile major, n-tile minor, the row + pair (row g, row g+8) each mma writes. 2566 + 120*mi + 10*tt is the first mma of group mi.""" + return sum(([f"%r{2566 + 120 * mi + 10 * tt + rh}" for rh in (0, 1)] + for mi in range(4) for tt in range(12)), []) + + + +def swin_p5_operand_regs(): + """Phase 5's 48 mma C pairs (the position bias: 24 tiles of four words, tile T at 2390 + 4*T) and + the twelve B fragment pairs (the e4m3 keys, 2932 + 10*tt) -- the operands the 48 mma read.""" + return (sum(([f"%r{2390 + 4 * t + w}" for w in range(4)] for t in range(24)), []) + + sum(([f"%r{2932 + 10 * t}", f"%r{2933 + 10 * t}"] for t in range(12)), [])) + + +def swin_e5_regs(): + """Phase 6's twelve A fragments (four b32 each, mma operand order) and twelve B fragment pairs: + the softmax probabilities and the transposed V that E5 packs.""" + return (sum(([f"%r{5884 + 120 * (a // 3) + 20 * (a % 3) + o}" for o in range(4)] + for a in range(12)), []) + + sum(([f"%r{6178 + 10 * b}", f"%r{6179 + 10 * b}"] for b in range(12)), [])) + + +def swin_e5a_regs(): + """Phase 6's twelve A fragments alone: the softmax probabilities E5 packs.""" + return sum(([f"%r{5884 + 120 * (a // 3) + 20 * (a % 3) + o}" for o in range(4)] + for a in range(12)), []) + + +def swin_p6_regs(): + """Phase 6's sixteen mma D pairs, each the third (last) k-step of its chain: m-tile major, + n-tile minor, the row pair (row g, row g+8).""" + return sum(([f"%r{5852 + 120 * mi + 10 * nt + 40 * (nt >> 1) + rh}" for rh in (0, 1)] + for mi in range(4) for nt in range(4)), []) + + +def swin_e6_regs(): + """Phase 7's sixteen A registers (four fragments of four) and its thirty-two C registers (the + residual plus the per-column table), m-tile major and n-tile minor.""" + return (sum(([f"%r{6366 + 40 * mi + o}" for o in range(4)] for mi in range(4)), []) + + sum(([f"%r{6342 + 40 * mi + 10 * nt + rh}" for rh in (0, 1)] + for mi in range(4) for nt in range(4)), [])) + + +def swin_p7_regs(): + """Phase 7's sixteen mma D pairs, m-tile major and n-tile minor.""" + return sum(([f"%r{6334 + 10 * (4 * mi + nt) + rh}" for rh in (0, 1)] + for mi in range(4) for nt in range(4)), []) + + +# a debug stage: (line after which to insert, registers to store); the per-block slot follows from +# the register count, so a stage is reproducible from its tuple alone +SWIN_DEBUG_STAGES = { + # the staged block input: the 24 A registers in the first mma's operand order plus the four bias seeds + "a": (3962, ["%r120", "%r136", "%r128", "%r144", "%r152", "%r168", "%r160", "%r176", + "%r184", "%r200", "%r192", "%r208", "%r216", "%r232", "%r224", "%r240", + "%r246", "%r257", "%r253", "%r1042", "%r1079", "%r1080", "%r1081", "%r1082", + "%r1086", "%r1096", "%r1106", "%r1116"]), + # phase 1's 24 accumulator register pairs (m-tile major, n-tile minor) + "p1": (4128, ["%r877", "%r878", "%r887", "%r888", "%r897", "%r898", "%r907", "%r908", + "%r917", "%r918", "%r927", "%r928", "%r937", "%r938", "%r947", "%r948", + "%r957", "%r958", "%r967", "%r968", "%r977", "%r978", "%r987", "%r988", + "%r997", "%r998", "%r1007", "%r1008", "%r1017", "%r1018", "%r1027", "%r1028", + "%r1037", "%r1038", "%r1047", "%r1048", "%r1057", "%r1058", "%r1067", "%r1068", + "%r1077", "%r1078", "%r1087", "%r1088", "%r1097", "%r1098", "%r1107", "%r1108"]), + # phase 2's accumulator pairs: its last mma's `;` is line 4489 + "p2": (4489, sum(([f"%r{d + 10 * i + j}" for i in range(4) for j in range(2)] + for d in range(1175, 1406, 40)), [])), + # phase 3's (the fused Q projection); its last mma ends on line 7840 + "p3": (7840, sum(([f"%r{d + 10 * i + j}" for i in range(4) for j in range(2)] + for d in range(1900, 2131, 40)), [])), + # phase 4's (V); its last mma ends on line 8021 + "p4": (8021, sum(([f"%r{d + 10 * i + j}" for i in range(4) for j in range(2)] + for d in range(2149, 2380, 40)), [])), + # phase 2's A operands as the epilogue packed them (the last bias load is line 4323) + "a2": (4323, SWIN_P2_A_REGS), + # phase 5 (the score GEMM, Q·Kᵀ with the position bias); its last mma ends on line 8741 + "p5": (8741, swin_p5_regs()), + # phase 5's C (bias) and B (key) operand registers, as the mma reads them + "p5o": (8741, swin_p5_operand_regs()), + # E5's output: phase 6's A and B fragments; the last pack is line 18883 + "e5": (18883, swin_e5_regs()), + # E5's probabilities alone: the fragment's B side is a movmatrix of phase 4's D, which the + # scalar body only reaches through phase 6's accumulators, so it is captured by p6 instead + "e5a": (18883, swin_e5a_regs()), + # phase 6 (P·V); its last mma ends on line 19220 + "p6": (19220, swin_p6_regs()), + # E6's output: phase 7's A fragments and C seeds; the last pack is line 19643 + "e6": (19643, swin_e6_regs()), + # phase 7 (the output projection); its last mma ends on line 19756 + "p7": (19756, swin_p7_regs()), +} + +# Per-layer extra debug stages, so a layer can add its own without editing this file: +# kernels/rr/swin__debug_stages.py exposing stages() -> {name: (line, [regs])}. They are keyed +# by (layer, stage) because two layers can use the same stage name; the entries above stay unkeyed +# and belong to enc0. +for _extra in sorted((Path(__file__).resolve().parent.parent / "rr").glob("swin_*_debug_stages.py")): + _layer = _extra.stem[len("swin_"):-len("_debug_stages")] + _spec = importlib.util.spec_from_file_location(_extra.stem, _extra) + _mod = importlib.util.module_from_spec(_spec) + _spec.loader.exec_module(_mod) + for _stage, _where in _mod.stages().items(): + SWIN_DEBUG_STAGES[(_layer, _stage)] = _where + + + + +def swin_debug_block(regs, entry="cuda_dldn_engine_swin_enc0_kernel", base=None): + """PTX that stores REGS (u32 each) to the output buffer + base + block*slot + lane*len(regs)*4. + + The region must be past the bytes the kernel itself writes; enc0's plane arena is 45,219,840 bytes + and a layer whose output buffer is smaller sets D4R_RRSWIN_DEBUG_BASE lower (both sides of the + comparison read the same value). Blocks above 63 are skipped so the first 64 blocks (one warp + each) land in distinct slots. Works on either side of the splice: it is inserted into NVIDIA's own + PTX for the reference and reproduced by the native body's debug flag. + """ + if base is None: + base = int(os.environ.get("D4R_RRSWIN_DEBUG_BASE", SWIN_DEBUG_BASE)) + slot = swin_debug_slot(len(regs)) + stores = "\n".join( + f"@%pdbg1 st.global.v4.u32 [%rddbg3+{i * 16}], {{{', '.join(regs[i * 4:i * 4 + 4])}}};" + for i in range((len(regs) + 3) // 4)) + return f"""// d4r debug stage +{{ +.reg .pred %pdbg<2>; +.reg .b32 %rdbg<8>; +.reg .b64 %rddbg<4>; +ld.param.u64 %rddbg1, [{entry}_param_0+48]; +mov.u32 %rdbg1, %ctaid.x; +mov.u32 %rdbg2, %ctaid.y; +mad.lo.s32 %rdbg3, %rdbg2, 161, %rdbg1; +setp.lt.u32 %pdbg1, %rdbg3, 64; +shl.b32 %rdbg4, %rdbg3, {slot.bit_length() - 1}; +mov.u32 %rdbg5, %laneid; +mad.lo.s32 %rdbg6, %rdbg5, {len(regs) * 4}, %rdbg4; +add.s32 %rdbg7, %rdbg6, {base}; +cvt.u64.u32 %rddbg2, %rdbg7; +add.s64 %rddbg3, %rddbg1, %rddbg2; +{stores} +}} +""" + + +def swin_debug(name): + """Debug recipe: keep NVIDIA's whole body and store one stage's accumulator registers.""" + stage = os.environ.get("D4R_RRSWIN_DEBUG", "") + match = re.fullmatch(r"cuda_dldn_engine_swin_(\w+)_kernel", name) + if not stage or match is None: + return None + where = SWIN_DEBUG_STAGES.get((match.group(1), stage)) + if where is None: + where = SWIN_DEBUG_STAGES.get(stage) + if where is None: + return None + return dict(file=module_file(name, {"file": ""}).name, debug=where, + debug_block=lambda regs: swin_debug_block(regs, name)) + + def kernel_spec(name): + d = swin_debug(name) + if d: + return d + # Per-layer recipes: kernels/rr/swin__recipe.py owns one denoiser layer's splice, so the + # ten layers can be written in parallel without sharing this file. Falls through to the built-in + # enc0 entry below when the module is absent. + swin = re.fullmatch(r"cuda_dldn_engine_swin_(\w+)_kernel", name) + if swin is not None: + module_path = Path(__file__).resolve().parent.parent / "rr" / f"swin_{swin.group(1)}_recipe.py" + if module_path.is_file(): + spec = importlib.util.spec_from_file_location(f"swin_{swin.group(1)}_recipe", module_path) + module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(module) + return module.recipe() + if name == "cuda_dldn_engine_swin_enc0_kernel" and os.environ.get("D4R_RRSWIN_CUT"): + return dict(file="0013-PREPASS_ENTRYPOINT_NAME.ptx", cut_call=(3964, 44528), extern=swin_cut_extern()) if name in KERNELS: return KERNELS[name] if ENC0_RE.match(name): @@ -542,6 +832,41 @@ def main(): if (lines[a - 1].strip(), lines[b - 1].strip()) != k["delete_check"]: sys.exit(f"lines {a}/{b} are {lines[a - 1]!r}/{lines[b - 1]!r}, expected {k['delete_check']}") head, tail = lines[:a - 1] + k["insert"].split("\n") + lines[b:], [] + elif "cut_call" in k: + before, after = k["cut_call"] + if not lines[before - 1].startswith("mma.sync.aligned.m16n8k32"): + sys.exit(f"{name}: cut line {before} is not an mma: {lines[before - 1]!r}") + # the line the cut ends on must be the last line of an mma statement; which mma that is + # depends on the layer, so this only checks the shape, not enc0's registers + if not lines[after - 2].rstrip().endswith(";"): + sys.exit(f"{name}: cut end {after} is not the end of an mma statement: {lines[after - 2]!r}") + head = lines[:before - 1] + k.get("call", swin_cut_call()).split("\n") + lines[after - 1:] + tail = [] + elif "debug" in k: + after, regs = k["debug"] + window = "\n".join(lines[max(0, after - 4000):after]) + prev = lines[after - 1].rstrip() + if regs[0] not in window or not (prev.endswith(";") or prev.endswith("//") or not prev): + sys.exit(f"{name}: debug line {after} is not phase 1's last mma: {lines[after - 1]!r}") + head, tail = lines[:after] + k.get("debug_block", swin_debug_block)(regs).split("\n") + lines[after:], [] + elif "replace_body" in k: + e = next(i for i, l in enumerate(lines) if l.startswith(f".visible .entry {name}(")) + b0 = next(i for i in range(e, len(lines)) if lines[i].strip() == "{") + j = b0 + 1 + while j < len(lines) and (not lines[j].strip() + or lines[j].lstrip().startswith((".reg", ".shared", ".param", ".pragma", "//"))): + j += 1 + if not lines[j - 1].lstrip().startswith("//") and lines[j - 1].strip() != "": + sys.exit(f"{name}: could not find the end of the entry declarations (line {j} is {lines[j - 1]!r})") + depth, b = 0, None + for i in range(b0, len(lines)): + depth += lines[i].count("{") - lines[i].count("}") + if i > b0 and depth == 0: + b = i + break + if b is None or lines[b].strip() != "}": + sys.exit(f"{name}: entry closing brace not found") + head, tail = lines[:j] + k["stub"].split("\n") + [""] + lines[b:], [] else: head, tail = lines, [] entry = next(i for i, l in enumerate(head) if l.startswith(".visible .entry")) @@ -560,8 +885,8 @@ def main(): body, n["dec8"] = replace_dec8(body) if n["dec8"] != k["dec8"]: sys.exit(f"{name}: {n['dec8']} e4m3 decodes, expected {k['dec8']}") - k = dict(k, extern=k["extern"] + DEC8_EXTERN) - extern = k["extern"] + (SUST_EXTERN if n["b16"] else "") + (SUST4_EXTERN if n.get("v4b16") else "") + (SUSTP_EXTERN if n["p"] else "") + (SUSTB32_EXTERN if n["b32"] else "") + k = dict(k, extern=k.get("extern", "") + DEC8_EXTERN) + extern = k.get("extern", "") + (SUST_EXTERN if n["b16"] else "") + (SUST4_EXTERN if n.get("v4b16") else "") + (SUSTP_EXTERN if n["p"] else "") + (SUSTB32_EXTERN if n["b32"] else "") text = "\n".join(head[:entry]) + "\n" + extern + "\n".join(body + tail) out.write_text(text) print(f"{out}: {len(text.splitlines())} lines, surface stores replaced: {n}") diff --git a/kernels/tools/rrswin_engine_k16_test.cpp b/kernels/tools/rrswin_engine_k16_test.cpp new file mode 100644 index 0000000..ce908ec --- /dev/null +++ b/kernels/tools/rrswin_engine_k16_test.cpp @@ -0,0 +1,785 @@ +// Steps 1 and 2 of the engine's validation: e4m3 GEMMs in real shared memory, every HIP call +// checked, compared against an independently computed host model. +// +// step 1 one k16 GEMM (the second k16 half is zero) -- operand form, lane/half indexing, +// and the D layout the engine assumes +// step 2 a 64-wide k chain as two k32 steps with the accumulator rounded to f16 between +// them, which is what kernels/tex/enc0_tail.hip does (`acc[i] = (half_t)cf[i]; +// cf[i] = (float)acc[i];`) +// +// The host model is e4m3 decode plus a double-precision sum, written from the layout facts in +// kernels/common/wmma_layout.h and the usage in kernels/tex/enc0_tail.hip; it shares no code +// with the device side. +// +// Build and run: +// hipcc --offload-arch=gfx1201 -DD4R_TEX_FP8 -DD4R_WMMA_LAYOUT=12 -O2 \ +// -o /tmp/engine_test kernels/tools/rrswin_engine_k16_test.cpp && /tmp/engine_test +#include +#include +#include +#include +#include +#include +#include + +#include "../rr/rrswin_engine.h" + +#define CHECK(expr) \ + do \ + { \ + hipError_t e_ = (expr); \ + if (e_ != hipSuccess) \ + { \ + std::printf("HIP error at %s:%d: %s -> %s\n", __FILE__, __LINE__, #expr, \ + hipGetErrorString(e_)); \ + std::exit(2); \ + } \ + } while (0) + +// the documented enc0 weight layout, written here independently of the device header +static int rrswin_waddr_host(int k, int n) +{ + return 512 * (n >> 4) + 64 * (n & 7) + 16 * ((k >> 1) & 3) + 8 * ((n >> 3) & 1) + + 4 * ((k >> 3) & 1) + 2 * ((k >> 4) & 1) + (k & 1); +} + +static const int kRows = 16; +static const int kChunk = 16; // bytes per k16 chunk +static const int kChunks = 4; // k = 64 in four k16 chunks (= two k32 steps) +static const int kRowBytes = kChunk * kChunks; +static const int kSlots = 128; // prepared weight slots: 32 per k32 step (16 rows x 2 k16), two steps per GEMM + +static uint8_t enc(double v) +{ + const int sign = v < 0; + v = std::fabs(v); + if (v < 0.001953125) + return (uint8_t)(sign ? 0x80 : 0x00); + int e = 0; + while (v >= 2.0) { v /= 2.0; ++e; } + while (v < 1.0) { v *= 2.0; --e; } + const int code = ((e + 7) << 3) | (int)std::lround((v - 1.0) * 8.0); + return (uint8_t)(code | (sign ? 0x80 : 0)); +} + +static double dec(uint8_t c) +{ + const int sign = c & 0x80, e = (c >> 3) & 0xf, m = c & 7; + const double mag = e == 0 ? (m / 8.0) * std::pow(2.0, -6.0) : (1.0 + m / 8.0) * std::pow(2.0, e - 7.0); + return sign ? -mag : mag; +} + +// D VGPR i of half h is row i + 8h and lane l is column l & 15, so a value's (row, column) +// fixes the lane and slot that must hold it. +static void check(const char* what, const std::vector& got, const std::vector& w, + const std::vector& x, int kk, double tol) +{ + int bad = 0, checked = 0; + for (int l = 0; l < 32; ++l) + { + const int h = l >> 4, rcol = l & 15; + for (int i = 0; i < 8; ++i) + { + const int row = i + 8 * h; + // weight row `row`'s k16 chunk h of k32 step s is stored at slot 32*s + 16*h + row, + // which is byte 16*slot -- NOT inside the same 16 bytes as the row's first chunk. + auto wslot = [&](int s, int chunk, int r) { return (size_t)(32 * s + 16 * chunk + r); }; + auto dot = [&](int from, int to) { + double s = 0.0; + for (int c = from; c < to; ++c) + s += dec(w[wslot(c / 32, (c % 32) / 16, row) * kChunk + (c % 16)]) * + dec(x[(size_t)rcol * kRowBytes + c]); + return s; + }; + double ref = dot(0, kk); + if (kk > 32) + { + // the caller's f16 rounding of the accumulator between the two k32 steps + const double first = (double)(_Float16)dot(0, 32); + ref = first + dot(32, kk); + } + const float g = got[i * 32 + l]; + ++checked; + if (std::fabs((double)g - ref) > tol * (1.0 + std::fabs(ref))) + { + if (bad < 6) + std::printf(" lane %2d vgpr %d: D[row %2d][col %2d] got %+.6f ref %+.6f\n", + l, i, row, rcol, g, ref); + ++bad; + } + } + } + std::printf("%s: checked %d, mismatched %d\n", what, checked, bad); + if (bad) + { + // report which (row, column) each mismatching value *does* correspond to, which is + // the mapping the engine would have to use + int shown = 0; + for (int l = 0; l < 32 && shown < 4; ++l) + { + for (int i = 0; i < 8 && shown < 4; ++i) + { + const float g = got[i * 32 + l]; + int best_row = -1, best_col = -1; + double best = 1e30; + for (int row = 0; row < 16; ++row) + for (int col = 0; col < 16; ++col) + { + double ref = 0.0; + for (int c = 0; c < kk; ++c) + ref += dec(w[(size_t)(32 * (c / 32) + 16 * ((c % 32) / 16) + row) * kChunk + (c % 16)]) * + dec(x[(size_t)col * kRowBytes + c]); + if (std::fabs((double)g - ref) < best) { best = std::fabs((double)g - ref); best_row = row; best_col = col; } + } + if (best < tol) + { + std::printf(" lane %2d vgpr %d = D[row %2d][col %2d] (engine assumed row %2d col %2d)\n", + l, i, best_row, best_col, i + 8 * (l >> 4), l & 15); + ++shown; + } + } + } + std::exit(1); + } +} + +// The requantisation the device performs in swin_stage_operand, written independently here: +// RNE satfinite e4m3 of an f16 pair, low half to the low byte. +static uint8_t requant_code(uint16_t h) +{ + const uint32_t mag = h & 0x7fffu; + uint32_t normal = ((mag - 0x2000u + 0x3fu + ((mag >> 7) & 1u)) & 0xffffu) >> 7; + const uint32_t e = mag >> 10; + const uint32_t clamped = e < 1u ? 1u : (e > 8u ? 8u : e); + const uint32_t shift = 16u - clamped; + const uint32_t sig = (mag & 0x3ffu) | (e != 0 ? 0x400u : 0u); + const uint32_t sub = (sig + (1u << (shift - 1u)) - 1u + ((sig >> shift) & 1u)) >> shift; + uint32_t code = mag >= 0x2400u ? normal : sub; + if (mag > 0x5f00u) + code = 0x7eu; + if (mag > 0x7c00u) + code = 0x7fu; + return (uint8_t)(((h >> 8) & 0x80u) | code); +} + +// the f16 bits the device would round to, then the e4m3 code +static uint8_t requant_code_bytes(double v) +{ + const _Float16 half = (_Float16)v; + uint16_t bits; + std::memcpy(&bits, &half, sizeof(bits)); + return requant_code(bits); +} + +static double requant(double v) +{ + const _Float16 half = (_Float16)v; + uint16_t bits; + std::memcpy(&bits, &half, sizeof(bits)); + return dec(requant_code(bits)); +} + +__global__ void step1_kernel(const uint8_t* x_img, const uint8_t* w_prep, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 0, 16, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; +} + +__global__ void step2_kernel(const uint8_t* x_img, const uint8_t* w_prep, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 0, 16, img, kRowBytes, 0); + half_t acc[8]; + for (int i = 0; i < 8; ++i) + acc[i] = (half_t)c[i]; + for (int i = 0; i < 8; ++i) + c[i] = (float)acc[i]; + // the second k32 step: slots 32..63 and the image's chunks 2 and 3 + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 32, 16, img + 2 * kChunk, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; +} + +// Step 3: the accumulator-to-operand mapping. A first k32 GEMM produces D, D is staged as +// the next phase's activation image with swin_stage_operand, and a second k32 GEMM consumes +// it against a second weight slot. The host model re-does exactly that, requantising with +// its own e4m3 encoder, so a wrong mapping (row/column/k-half) shows up as a mismatch. +__global__ void step3_kernel(const uint8_t* x_img, const uint8_t* w_prep, uint8_t* staged, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 0, 16, img, kRowBytes, 0); + __syncthreads(); + // the staging writes 16 rows, i.e. k 0..15; the image's second k16 chunk must not keep + // the values the first GEMM's operand left there, or the second GEMM sums them too + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + if ((i % kRowBytes) >= 16) + img[i] = 0; + __syncthreads(); + rrswin::swin_stage_operand(img, kRowBytes, 0, 0, c); + __syncthreads(); + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + staged[i] = img[i]; + __syncthreads(); + f8v d = {0, 0, 0, 0, 0, 0, 0, 0}; + d = rrswin::swin_gemm_tile(d, (const kslot*)w_prep, 64, 16, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = d[i]; +} + +// Step 4: the weight preparation. Lane t prepares weight row t's two k16 slots (32 bytes), then +// the phase runs with a known activation image and the result is compared against a host model +// that reads the weight image through the documented waddr. This is what proves the prep's slot +// addressing, which the GEMM alone cannot see. +__global__ void step4_kernel(const uint8_t* x_img, const uint8_t* wimg, uint8_t* slots, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + const int t = threadIdx.x & 15; + if ((threadIdx.x >> 4) == 0) + rrswin::swin_prep_phase(slots, 0, 16, 1, wimg, rrswin::swin_waddr_enc0); + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)slots, 0, 16, img, kRowBytes, 0); + (void)t; + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; +} + +// Step 4c: a 32-row phase (two m-tiles of 16 weight rows). slot_step is n_rows = 32, so tile 1's +// rows sit past tile 0's second k16 slot; with a fixed step of 16 it would read them as tile 0's +// second k16 operand. +__global__ void step4c_kernel(const uint8_t* x_img, const uint8_t* wimg, uint8_t* slots, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + if (threadIdx.x == 0) + rrswin::swin_prep_phase(slots, 0, 32, 1, wimg, rrswin::swin_waddr_enc0); + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)slots, 0, 32, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; + f8v d = {0, 0, 0, 0, 0, 0, 0, 0}; + d = rrswin::swin_gemm_tile(d, (const kslot*)slots, 16, 32, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[256 + i * 32 + threadIdx.x] = d[i]; +} + +// Step 5: the phase loop. Phase 1 is a 32-row (two m-tiles) x 16-token x k64 GEMM that stages +// its accumulator; phase 2 is 16x16x32 reading that staged image. The host model redoes the +// whole chain, including the e4m3 requantisation between the phases. +__global__ void step5_kernel(const uint8_t* x_img, const uint8_t* wimg, uint8_t* slots, + uint8_t* staged, float* out) +{ + __shared__ uint8_t img[16 * 64]; + __shared__ uint8_t mid[16 * 32]; + for (int i = threadIdx.x; i < 16 * 64; i += blockDim.x) + img[i] = x_img[i]; + for (int i = threadIdx.x; i < 16 * 32; i += blockDim.x) + mid[i] = 0; + __syncthreads(); + if (threadIdx.x == 0) + { + rrswin::swin_prep_phase(slots + 0, 0, 32, 2, wimg, rrswin::swin_waddr_enc0); // phase 1 + rrswin::swin_prep_phase(slots + 32 * 32 * 2, 0, 16, 1, wimg + 8192, rrswin::swin_waddr_enc0); + } + __syncthreads(); + rrswin::Phase p1 = {2, 1, 2, 0, 0, 0}; + rrswin::swin_phase(p1, (const kslot*)slots, 32, img, 64, mid, 32, nullptr); + __syncthreads(); + for (int i = threadIdx.x; i < 16 * 32; i += blockDim.x) + staged[i] = mid[i]; + rrswin::Phase p2 = {1, 1, 1, 128, 1, 0}; // slot 128 = byte 2048, past phase 1's slots + f8v acc[1]; + rrswin::swin_phase(p2, (const kslot*)slots, 16, mid, 32, nullptr, 0, acc); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = acc[0][i]; +} + +// Step 6: the clamped cubic activation. The host model below is written from the specification +// in kernels/rr/rrswin_enc0.hip's comment (y = clamp(x, +-2), out = x * (0.5 + y * (0.412109375 +// - 0.0810546875*|y|)), f16 throughout, constants 0x3698/0x2d30/0x3800/0x4000) rather than from +// the device code, so agreement means the port is faithful. +static uint16_t act_model(uint16_t bits) +{ + const auto as_half = [](uint16_t b) { _Float16 h; std::memcpy(&h, &b, sizeof(h)); return h; }; + const auto as_bits = [](const _Float16& h) { uint16_t b; std::memcpy(&b, &h, sizeof(b)); return b; }; + const _Float16 x = as_half(bits); + const _Float16 two = as_half(0x4000), slope = as_half(0x2d30), mid = as_half(0x3698), half0 = as_half(0x3800); + _Float16 y = x > -two ? x : -two; + y = y < two ? y : two; + y = y > -y ? y : -y; + const _Float16 g = (_Float16)(half0 + y * (mid - slope * y)); + return as_bits((_Float16)(x * g)); +} + +__global__ void step6_kernel(const uint32_t* pairs, uint32_t* out) +{ + const uint32_t p = pairs[threadIdx.x]; + out[threadIdx.x] = rrswin::swin_act_pair(p); +} + +// Step 7: fragment-to-image staging. A host model of the documented layout builds the fragment +// registers from a known image, the device stages them back, and the result must equal the +// original image -- a round trip that fails if any (row, k) mapping is wrong. +static void fragment_model(const std::vector& img, int stride, int m_tiles, + std::vector& frag, int lane) +{ + const int g = lane >> 2, t = lane & 3; + uint32_t* mine = frag.data() + (size_t)4 * m_tiles * lane; // each lane's own registers + for (int mi = 0; mi < m_tiles; ++mi) + for (int j = 0; j < 4; ++j) + { + const uint32_t k0 = 2 * t + (j & 1) + 16u * ((j >> 1) & 1); + const uint32_t k2 = 8u + k0; + mine[4 * mi + 0] |= (uint32_t)img[(size_t)(16 * mi + g) * stride + k0] << (8 * j); + mine[4 * mi + 1] |= (uint32_t)img[(size_t)(16 * mi + g + 8) * stride + k0] << (8 * j); + mine[4 * mi + 2] |= (uint32_t)img[(size_t)(16 * mi + g) * stride + k2] << (8 * j); + mine[4 * mi + 3] |= (uint32_t)img[(size_t)(16 * mi + g + 8) * stride + k2] << (8 * j); + } +} + +__global__ void step7_kernel(const uint32_t* frag, uint8_t* staged, int m_tiles) +{ + __shared__ uint8_t img[64 * 32]; + for (int i = threadIdx.x; i < 64 * 32; i += blockDim.x) + img[i] = 0; + __syncthreads(); + rrswin::swin_stage_fragment(img, 32, frag + 4 * m_tiles * threadIdx.x, m_tiles); + __syncthreads(); + for (int i = threadIdx.x; i < 64 * 32; i += blockDim.x) + staged[i] = img[i]; +} + +int main() +{ + std::vector x(kRows * kRowBytes, 0), w(kSlots * kChunk, 0); + // Well-spread e4m3 codes: small/huge and equal sums must not collide, or the mapping + // search below cannot tell one (row, column) from another. + uint32_t lcg = 0x12345678u; + auto next_code = [&lcg]() -> uint8_t { + lcg = lcg * 1664525u + 1013904223u; + uint32_t mag = (lcg >> 13) & 0x3fu; // exponents 0..7 and mantissas + if (mag == 0) + mag = 0x21; + const uint32_t sign = (lcg >> 7) & 1u; + return (uint8_t)((sign << 7) | mag); + }; + for (int r = 0; r < kRows; ++r) + for (int c = 0; c < kChunks * kChunk; ++c) + { + // row r's k16 chunk h of k32 step `step` lives at slot 32*step + 16*h + r + const int step = c / 32, h = (c % 32) / 16, kk = c % 16; + w[(size_t)(32 * step + 16 * h + r) * kChunk + kk] = next_code(); + x[(size_t)r * kRowBytes + c] = next_code(); + } + + uint8_t *dx, *dw; + float* dout; + CHECK(hipMalloc(&dx, x.size())); + CHECK(hipMalloc(&dw, w.size())); + CHECK(hipMalloc(&dout, 8 * 32 * sizeof(float))); + std::vector got(8 * 32); + + CHECK(hipMemcpy(dx, x.data(), x.size(), hipMemcpyHostToDevice)); + CHECK(hipMemcpy(dw, w.data(), w.size(), hipMemcpyHostToDevice)); + step1_kernel<<<1, 32>>>(dx, dw, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + check("step 1 one k32 step (k 0..31)", got, w, x, 32, 2e-3); + + step2_kernel<<<1, 32>>>(dx, dw, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + check("step 2 k64 as two k32 with f16 rounding", got, w, x, 64, 2e-3); + + // step 3: two chained GEMMs with the accumulator staged as the next operand + { + std::vector w2 = w; // slots 64..95 are zero so far + for (int r = 0; r < kRows; ++r) + for (int c = 0; c < 32; ++c) + { + const int h = c / 16, kk = c % 16; + w2[(size_t)(64 + 16 * h + r) * kChunk + kk] = next_code(); + } + CHECK(hipMemcpy(dw, w2.data(), w2.size(), hipMemcpyHostToDevice)); + uint8_t* dstaged; + CHECK(hipMalloc(&dstaged, kRows * kRowBytes)); + step3_kernel<<<1, 32>>>(dx, dw, dstaged, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + + std::vector staged(kRows * kRowBytes, 0); + CHECK(hipMemcpy(staged.data(), dstaged, staged.size(), hipMemcpyDeviceToHost)); + auto w1_at = [&](int m, int k) { return w[(size_t)(32 * (k / 32) + 16 * ((k % 32) / 16) + m) * kChunk + (k % 16)]; }; + // where did each expected staged byte land, and what is at its expected slot? + int pl = 0; + for (int n = 0; n < 16 && pl < 6; ++n) + for (int m = 0; m < 16 && pl < 6; ++m) + { + double d1 = 0.0; + for (int j = 0; j < 32; ++j) + d1 += dec(w1_at(m, j)) * dec(x[(size_t)n * kRowBytes + j]); + const uint8_t want = requant_code(((_Float16)(float)d1) ? [&] { + const _Float16 h = (_Float16)d1; + uint16_t b; + std::memcpy(&b, &h, sizeof(b)); + return b; + }() : 0); + const uint8_t have = staged[(size_t)n * kRowBytes + m]; + std::printf(" staged[col %2d][k %2d] = 0x%02x, expected 0x%02x%s\n", n, m, have, want, + have == want ? "" : " <-- differs"); + ++pl; + } + auto w2_at = [&](int m, int k) { return w2[(size_t)(64 + 32 * (k / 32) + 16 * ((k % 32) / 16) + m) * kChunk + (k % 16)]; }; + int bad = 0, checked = 0; + for (int l = 0; l < 32; ++l) + { + const int h = l >> 4, col = l & 15; + for (int i = 0; i < 8; ++i) + { + const int m = i + 8 * h; + // The staging covers 16 rows (the first GEMM's m), so the second GEMM's + // k 16..31 operand is zero; the model sums the same 16 k. + double ref = 0.0; + for (int k = 0; k < 16; ++k) + { + double d1 = 0.0; + for (int j = 0; j < 32; ++j) + d1 += dec(w1_at(k, j)) * dec(x[(size_t)col * kRowBytes + j]); + ref += dec(w2_at(m, k)) * requant(d1); + } + const float g = got[i * 32 + l]; + ++checked; + if (std::fabs((double)g - ref) > 2e-3 * (1.0 + std::fabs(ref))) + { + if (bad < 4) + std::printf(" step3 lane %2d vgpr %d: got %+.6f ref %+.6f\n", l, i, g, ref); + ++bad; + } + } + } + std::printf("step 3 accumulator staged as the next operand: checked %d, mismatched %d\n", + checked, bad); + CHECK(hipFree(dstaged)); + if (bad) + std::exit(1); + } + // step 4: weight preparation, checked through the GEMM against the documented layout + { + std::vector wimg(65536, 0); + for (int k = 0; k < 32; ++k) + for (int n = 0; n < 16; ++n) + wimg[rrswin_waddr_host(k, n)] = next_code(); + + uint8_t* dwimg; + uint8_t* dslots; + CHECK(hipMalloc(&dwimg, wimg.size())); + CHECK(hipMalloc(&dslots, 16 * 16 * 2)); + CHECK(hipMemset(dslots, 0, 16 * 16 * 2)); + CHECK(hipMemcpy(dwimg, wimg.data(), wimg.size(), hipMemcpyHostToDevice)); + step4_kernel<<<1, 32>>>(dx, dwimg, dslots, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + + std::vector slotsHost(16 * 16 * 2, 0); + CHECK(hipMemcpy(slotsHost.data(), dslots, slotsHost.size(), hipMemcpyDeviceToHost)); + int bad = 0, checked = 0; + for (int hus = 0; hus < 2; ++hus) + for (int n = 0; n < 16; ++n) + for (int j = 0; j < 16; ++j) + { + const uint8_t have = slotsHost[16 * (16 * hus + n) + j]; + const uint8_t want = wimg[rrswin_waddr_host(16 * hus + j, n)]; + ++checked; + if (have != want) + { + if (bad < 4) + std::printf(" slot[h%u n%2d j%2d] = 0x%02x, expected 0x%02x\n", hus, n, j, have, want); + ++bad; + } + } + std::printf("step 4a prep slots: checked %d, mismatched %d\n", checked, bad); + + int gbad = 0, gchecked = 0; + for (int l = 0; l < 32; ++l) + { + const int h = l >> 4, col = l & 15; + for (int i = 0; i < 8; ++i) + { + const int n = i + 8 * h; + double ref = 0.0; + for (int k = 0; k < 32; ++k) + ref += dec(wimg[rrswin_waddr_host(k, n)]) * dec(x[(size_t)col * kRowBytes + k]); + const float g = got[i * 32 + l]; + ++gchecked; + if (std::fabs((double)g - ref) > 2e-3 * (1.0 + std::fabs(ref))) + { + if (gbad < 4) + std::printf(" step4 GEMM lane %2d vgpr %d: got %+.6f ref %+.6f\n", l, i, g, ref); + ++gbad; + } + } + } + std::printf("step 4b prep through the GEMM: checked %d, mismatched %d\n", gchecked, gbad); + + + CHECK(hipFree(dwimg)); + CHECK(hipFree(dslots)); + if (bad || gbad) + std::exit(1); + } + // step 4c: 32 rows, two m-tiles, slot_step = n_rows + { + std::vector wimg(131072, 0); + for (int k = 0; k < 32; ++k) + for (int n = 0; n < 32; ++n) + wimg[rrswin_waddr_host(k, n)] = next_code(); + + uint8_t* dwimg; + uint8_t* dslots; + float* dout2; + CHECK(hipMalloc(&dwimg, wimg.size())); + CHECK(hipMalloc(&dslots, 32 * 16 * 2)); + CHECK(hipMalloc(&dout2, 512 * sizeof(float))); + CHECK(hipMemset(dslots, 0, 32 * 16 * 2)); + CHECK(hipMemcpy(dwimg, wimg.data(), wimg.size(), hipMemcpyHostToDevice)); + step4c_kernel<<<1, 32>>>(dx, dwimg, dslots, dout2); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got2(512); + CHECK(hipMemcpy(got2.data(), dout2, got2.size() * sizeof(float), hipMemcpyDeviceToHost)); + + int bad = 0, checked = 0; + for (int tile = 0; tile < 2; ++tile) + for (int l = 0; l < 32; ++l) + { + const int h = l >> 4, col = l & 15; + for (int i = 0; i < 8; ++i) + { + const int n = 16 * tile + i + 8 * h; + double ref = 0.0; + for (int k = 0; k < 32; ++k) + ref += dec(wimg[rrswin_waddr_host(k, n)]) * dec(x[(size_t)col * kRowBytes + k]); + const float g = got2[tile * 256 + i * 32 + l]; + ++checked; + if (std::fabs((double)g - ref) > 2e-3 * (1.0 + std::fabs(ref))) + { + if (bad < 4) + std::printf(" step4c tile %d lane %2d vgpr %d: got %+.6f ref %+.6f\n", + tile, l, i, g, ref); + ++bad; + } + } + } + std::printf("step 4c 32-row phase, two m-tiles: checked %d, mismatched %d\n", checked, bad); + CHECK(hipFree(dwimg)); + CHECK(hipFree(dslots)); + CHECK(hipFree(dout2)); + if (bad) + std::exit(1); + } + // step 5: the phase loop, two phases chained through a staged image + { + std::vector wimg(32768, 0); + for (int k = 0; k < 32; ++k) + for (int n = 0; n < 48; ++n) + wimg[(n < 32 ? rrswin_waddr_host(k, n) : 8192 + rrswin_waddr_host(k, n - 32))] = next_code(); + + uint8_t *dwimg, *dslots, *dstaged; + float* dout2; + CHECK(hipMalloc(&dwimg, wimg.size())); + CHECK(hipMalloc(&dslots, (32 * 32 * 2 + 16 * 16 * 2))); + CHECK(hipMalloc(&dstaged, 16 * 32)); + CHECK(hipMalloc(&dout2, 256 * sizeof(float))); + CHECK(hipMemset(dslots, 0, 32 * 32 * 2 + 16 * 16 * 2)); + CHECK(hipMemcpy(dwimg, wimg.data(), wimg.size(), hipMemcpyHostToDevice)); + step5_kernel<<<1, 32>>>(dx, dwimg, dslots, dstaged, dout2); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got2(256); + CHECK(hipMemcpy(got2.data(), dout2, got2.size() * sizeof(float), hipMemcpyDeviceToHost)); + + std::vector staged(16 * 32, 0); + CHECK(hipMemcpy(staged.data(), dstaged, staged.size(), hipMemcpyDeviceToHost)); + auto w1 = [&](int m, int k) { return wimg[rrswin_waddr_host(k, m)]; }; + { + int sbad = 0, schecked = 0; + for (int col = 0; col < 16 && sbad < 4; ++col) + for (int m = 0; m < 32; ++m) + { + double d1 = 0.0; + for (int j = 0; j < 64; ++j) + d1 += dec(w1(m, j)) * dec(x[(size_t)col * kRowBytes + j]); + const uint8_t want = requant_code_bytes(d1); + const uint8_t have = staged[(size_t)col * 32 + m]; + ++schecked; + if (have != want) + { + if (sbad < 4) + std::printf(" staged5[col %2d][k %2d] = 0x%02x, expected 0x%02x\n", col, m, have, want); + ++sbad; + } + } + std::printf("step 5a staged image: checked %d, mismatched %d\n", schecked, sbad); + } + auto w2 = [&](int m, int k) { return wimg[8192 + rrswin_waddr_host(k, m)]; }; + int bad = 0, checked = 0; + for (int l = 0; l < 32; ++l) + { + const int h = l >> 4, col = l & 15; + for (int i = 0; i < 8; ++i) + { + const int n = i + 8 * h; + // phase 1's staged image: row = token col, k = phase 1's m + // phase 2's k spans 32: phase 1's two m-tiles land in the staged image's two + // k16 chunks + double ref = 0.0; + for (int k = 0; k < 32; ++k) + { + double d1 = 0.0; + for (int j = 0; j < 64; ++j) + d1 += dec(w1(k, j)) * dec(x[(size_t)col * kRowBytes + j]); + ref += dec(w2(n, k)) * requant(d1); + } + const float g = got2[i * 32 + l]; + ++checked; + if (std::fabs((double)g - ref) > 3e-3 * (1.0 + std::fabs(ref))) + { + if (bad < 4) + std::printf(" step5 lane %2d vgpr %d: got %+.6f ref %+.6f\n", l, i, g, ref); + ++bad; + } + } + } + std::printf("step 5 phase loop, two phases: checked %d, mismatched %d\n", checked, bad); + CHECK(hipFree(dwimg)); + CHECK(hipFree(dslots)); + CHECK(hipFree(dstaged)); + CHECK(hipFree(dout2)); + if (bad) + std::exit(1); + } + // step 6: the clamped cubic activation, over f16 pairs spanning and crossing the clamps + { + std::vector pairs(64); + for (int i = 0; i < 64; ++i) + { + const _Float16 lo = (_Float16)((i - 32) * 0.21f); + const _Float16 hi = (_Float16)((i - 16) * -0.13f + 1.7f); + uint16_t bl, bh; + std::memcpy(&bl, &lo, sizeof(bl)); + std::memcpy(&bh, &hi, sizeof(bh)); + pairs[i] = (uint32_t)bl | ((uint32_t)bh << 16); + } + uint32_t *dp, *dop; + CHECK(hipMalloc(&dp, pairs.size() * 4)); + CHECK(hipMalloc(&dop, pairs.size() * 4)); + CHECK(hipMemcpy(dp, pairs.data(), pairs.size() * 4, hipMemcpyHostToDevice)); + step6_kernel<<<1, 64>>>(dp, dop); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got6(pairs.size()); + CHECK(hipMemcpy(got6.data(), dop, got6.size() * 4, hipMemcpyDeviceToHost)); + int bad = 0, checked = 0; + for (int i = 0; i < 64; ++i) + { + const uint32_t want = (uint32_t)act_model((uint16_t)(pairs[i] & 0xffff)) + | ((uint32_t)act_model((uint16_t)(pairs[i] >> 16)) << 16); + ++checked; + // The device applies the formula with packed f16x2 operations, which is what the PTX + // does; this scalar _Float16 model can land one ulp away. A logic error moves whole + // clamps, so one ulp is the right bar here; the oracle comparison is the bit-exact + // check, later. + auto within_ulp = [](uint16_t a, uint16_t b) { + // compare as f16 by ordering the sign-magnitude representation + const auto key = [](uint16_t v) -> int { + return (v & 0x8000) ? (int)(0x8000 - (v & 0x7fff)) : (int)(v & 0x7fff); + }; + const int d = key(a) - key(b); + return d >= -1 && d <= 1; + }; + if (!within_ulp((uint16_t)(got6[i] & 0xffff), (uint16_t)(want & 0xffff)) || + !within_ulp((uint16_t)(got6[i] >> 16), (uint16_t)(want >> 16))) + { + if (bad < 4) + std::printf(" act pair %2d: got %08x want %08x\n", i, got6[i], want); + ++bad; + } + } + std::printf("step 6 clamped cubic activation (1 ulp): checked %d, mismatched %d\n", checked, bad); + CHECK(hipFree(dp)); + CHECK(hipFree(dop)); + if (bad) + std::exit(1); + } + // step 7: fragment -> image staging round trip + { + const int m_tiles = 4; + std::vector src(64 * 32, 0); + uint32_t lcg7 = 0x2468ace0u; + for (auto& v : src) + { + lcg7 = lcg7 * 1664525u + 1013904223u; + v = (uint8_t)((lcg7 >> 21) & 0x7fu); + } + std::vector frag(32 * 4 * m_tiles, 0); + for (int lane = 0; lane < 32; ++lane) + fragment_model(src, 32, m_tiles, frag, lane); + + uint32_t* dfrag; + uint8_t* dstaged7; + CHECK(hipMalloc(&dfrag, frag.size() * 4)); + CHECK(hipMalloc(&dstaged7, src.size())); + CHECK(hipMemcpy(dfrag, frag.data(), frag.size() * 4, hipMemcpyHostToDevice)); + CHECK(hipMemset(dstaged7, 0, src.size())); + step7_kernel<<<1, 32>>>(dfrag, dstaged7, m_tiles); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got7(src.size(), 0); + CHECK(hipMemcpy(got7.data(), dstaged7, src.size(), hipMemcpyDeviceToHost)); + int bad = 0, checked = 0; + for (size_t i = 0; i < src.size(); ++i) + { + ++checked; + if (got7[i] != src[i]) + { + if (bad < 4) + std::printf(" stage byte %zu (row %zu k %zu): got 0x%02x want 0x%02x\n", i, i / 32, i % 32, + got7[i], src[i]); + ++bad; + } + } + std::printf("step 7 fragment staging round trip: checked %d, mismatched %d\n", checked, bad); + CHECK(hipFree(dfrag)); + CHECK(hipFree(dstaged7)); + if (bad) + std::exit(1); + } + CHECK(hipFree(dx)); + CHECK(hipFree(dw)); + CHECK(hipFree(dout)); + return 0; +} diff --git a/kernels/tools/rrswin_fp8_unpaired_test.cpp b/kernels/tools/rrswin_fp8_unpaired_test.cpp new file mode 100644 index 0000000..e40a54a --- /dev/null +++ b/kernels/tools/rrswin_fp8_unpaired_test.cpp @@ -0,0 +1,93 @@ +// Test a translated PTX MMA, not a direct call to its lowering helpers. +// The first warp catches masked-EXEC padding (A=1, B=0.5, C=1 => D=17). +// The second checks every row/column with A[r,k]=(r+1)/8, B[k,c]=(c+1)/8. +// Its nonuniform bias C[r,c]=8*r+c+0.25 also checks accumulator layout conversion. +// A second MMA checks partial accumulator writes separated by a dependent read: +// double the low-row bias through the shadow, negate the high-row bias. +// All expected values are exactly representable in f16. +// +// Build: hipcc -O2 kernels/tools/rrswin_fp8_unpaired_test.cpp -o /tmp/fp8_unpaired_test +// Emit with the patched ZLUDA d4r_emit example: +// env D4R_ZLUDA_WMMA=1 D4R_ZLUDA_WMMA_FP8=1 D4R_ZLUDA_WMMA_FP8_NATIVE=1 \ +// d4r_emit kernels/tools/rrswin_fp8_unpaired.ptx /tmp/fp8_unpaired gfx1201 +// Run: /tmp/fp8_unpaired_test /tmp/fp8_unpaired/module.hsaco +#include +#include +#include +#include +#include + +#define CHECK(expr) do { \ + const hipError_t error = (expr); \ + if (error != hipSuccess) { \ + std::fprintf(stderr, "%s: %s\n", #expr, hipGetErrorString(error)); \ + std::exit(2); \ + } \ +} while (0) + +static uint16_t half_bits(float value) +{ + const _Float16 half = static_cast<_Float16>(value); + uint16_t bits; + std::memcpy(&bits, &half, sizeof(bits)); + return bits; +} + +int main(int argc, char **argv) +{ + if (argc != 2) { + std::fprintf(stderr, "usage: %s module.hsaco\n", argv[0]); + return 2; + } + constexpr unsigned lanes = 64; + constexpr uint8_t eighths[16] = { + 0x20, 0x28, 0x2c, 0x30, 0x32, 0x34, 0x36, 0x38, + 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40 + }; + uint32_t input[lanes * 8], output[lanes * 4]; + uint16_t expected[lanes * 8]; + for (unsigned i = 0; i < lanes; ++i) { + const unsigned g = (i % 32) / 4, t = i % 4; + const uint32_t low = i < 32 ? 0x38383838u : uint32_t(eighths[g]) * 0x01010101u; + const uint32_t high = i < 32 ? low : uint32_t(eighths[g + 8]) * 0x01010101u; + const uint32_t b = i < 32 ? 0x30303030u : uint32_t(eighths[g]) * 0x01010101u; + uint32_t fragment[8] = {low, high, low, high, b, b, 0, 0}; + for (unsigned row = 0; row < 2; ++row) + for (unsigned column = 0; column < 2; ++column) { + const float bias = i < 32 ? 1.f : float(8 * (g + 8 * row) + 2 * t + column) + 0.25f; + fragment[6 + row] |= uint32_t(half_bits(bias)) << (16 * column); + const float product = i < 32 ? 16.f : float((g + 8 * row + 1) * (2 * t + column + 1)) / 2.f; + expected[i * 8 + row * 2 + column] = half_bits(bias + product); + expected[i * 8 + 4 + row * 2 + column] = half_bits((row == 0 ? 2.f : -1.f) * bias + product); + } + std::memcpy(input + i * 8, fragment, sizeof(fragment)); + } + hipModule_t module; + hipFunction_t function; + CHECK(hipModuleLoad(&module, argv[1])); + CHECK(hipModuleGetFunction(&function, module, "fp8_unpaired")); + uint32_t *device_input, *device_output; + CHECK(hipMalloc(&device_input, sizeof(input))); + CHECK(hipMalloc(&device_output, sizeof(output))); + CHECK(hipMemcpy(device_input, input, sizeof(input), hipMemcpyHostToDevice)); + CHECK(hipMemset(device_output, 0, sizeof(output))); + void *args[] = {&device_input, &device_output}; + CHECK(hipModuleLaunchKernel(function, 2, 1, 1, 32, 1, 1, 0, nullptr, args, nullptr)); + CHECK(hipDeviceSynchronize()); + CHECK(hipMemcpy(output, device_output, sizeof(output), hipMemcpyDeviceToHost)); + uint16_t observed[lanes * 8]; + std::memcpy(observed, output, sizeof(observed)); + unsigned bad = 0; + for (unsigned i = 0; i < lanes * 8; ++i) + if (observed[i] != expected[i]) { + if (bad < 8) + std::fprintf(stderr, "warp=%u lane=%u case=%u half=%u: got %04x, expected %04x\n", + i / 256, (i / 8) % 32, (i / 4) % 2, i % 4, observed[i], expected[i]); + ++bad; + } + CHECK(hipFree(device_output)); + CHECK(hipFree(device_input)); + CHECK(hipModuleUnload(module)); + std::printf("unpaired FP8 MMA and partial accumulators: %u/512 differing half values\n", bad); + return bad ? 1 : 0; +} diff --git a/kernels/tools/rrswin_operand_fit.cpp b/kernels/tools/rrswin_operand_fit.cpp new file mode 100644 index 0000000..9baa077 --- /dev/null +++ b/kernels/tools/rrswin_operand_fit.cpp @@ -0,0 +1,184 @@ +// Fit the engine's D mapping by measurement. +// +// The WMMA computes D[m][n] = sum_k A[m][k] B[k][n]. With A (the prepared weight slot) filled +// as value_for((b + c * r) % 16) in byte b of row r, and B (the activation image) an identity +// selector (row n holds 1.0 at byte n, zero elsewhere), the value that comes out at a given +// (vgpr, lane) is value_for((n + c * m) % 16): one equation in the two indices the engine's +// indexing must report. Two runs with different c (1 and 3, both coprime with 16) solve for +// both. Nothing here assumes which (r, n) is which -- the point is to measure it. +// +// Build and run: +// hipcc --offload-arch=gfx1201 -DD4R_TEX_FP8 -DD4R_WMMA_LAYOUT=12 -O2 \ +// -o /tmp/fit kernels/tools/rrswin_operand_fit.cpp && /tmp/fit +#include +#include +#include +#include +#include +#include + +#include "../rr/rrswin_engine.h" + +#define CHECK(expr) \ + do \ + { \ + hipError_t e_ = (expr); \ + if (e_ != hipSuccess) \ + { \ + std::printf("HIP error at %s:%d: %s -> %s\n", __FILE__, __LINE__, #expr, \ + hipGetErrorString(e_)); \ + std::exit(2); \ + } \ + } while (0) + +static const int kRows = 16, kChunk = 16, kRowBytes = 32; + +static uint8_t value_for(int k) +{ + const int e = 1 + (k & 7), m = (k >> 3) & 1; + return (uint8_t)((e << 3) | (m ? 4 : 0)); +} + +static double dec(uint8_t c) +{ + const int sign = c & 0x80, e = (c >> 3) & 0xf, m = c & 7; + const double mag = e == 0 ? (m / 8.0) * std::pow(2.0, -6.0) : (1.0 + m / 8.0) * std::pow(2.0, e - 7.0); + return sign ? -mag : mag; +} + +static int value_index(double v) +{ + for (int q = 0; q < 16; ++q) + if (std::fabs(v - dec(value_for(q))) < 1e-3) + return q; + return -1; +} + +__global__ void fit_kernel(const uint8_t* x_img, const uint8_t* w_prep, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 0, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; +} + +// run one pattern and return the value_for index at every (vgpr i, lane l) +static std::vector run(int coefficient, const std::vector& x) +{ + std::vector w(32 * kChunk, 0); + for (int r = 0; r < kRows; ++r) + for (int b = 0; b < 16; ++b) + w[(size_t)r * kChunk + b] = value_for((b + coefficient * r) % 16); + + uint8_t *dx, *dw; + float* dout; + CHECK(hipMalloc(&dx, x.size())); + CHECK(hipMalloc(&dw, w.size())); + CHECK(hipMalloc(&dout, 8 * 32 * sizeof(float))); + CHECK(hipMemcpy(dx, x.data(), x.size(), hipMemcpyHostToDevice)); + CHECK(hipMemcpy(dw, w.data(), w.size(), hipMemcpyHostToDevice)); + fit_kernel<<<1, 32>>>(dx, dw, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got(8 * 32); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + std::vector idx(8 * 32); + for (int i = 0; i < 8 * 32; ++i) + idx[i] = value_index(got[i]); + CHECK(hipFree(dx)); + CHECK(hipFree(dw)); + CHECK(hipFree(dout)); + return idx; +} + +// Experiment 3: A row r carries a distinct value at byte 0 only, and every B row is 1.0 at +// byte 0, so D[i][l] reads back the A row that element was actually computed from. This is +// the operand row selection, which experiment 2 cannot separate from the D indexing. +static std::vector run_rows(const std::vector& x) +{ + std::vector w(32 * kChunk, 0); + for (int r = 0; r < kRows; ++r) + w[(size_t)r * kChunk + 0] = value_for(r); + uint8_t *dx, *dw; + float* dout; + CHECK(hipMalloc(&dx, x.size())); + CHECK(hipMalloc(&dw, w.size())); + CHECK(hipMalloc(&dout, 8 * 32 * sizeof(float))); + CHECK(hipMemcpy(dx, x.data(), x.size(), hipMemcpyHostToDevice)); + CHECK(hipMemcpy(dw, w.data(), w.size(), hipMemcpyHostToDevice)); + fit_kernel<<<1, 32>>>(dx, dw, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got(8 * 32); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + std::vector idx(8 * 32); + for (int i = 0; i < 8 * 32; ++i) + idx[i] = value_index(got[i]); + CHECK(hipFree(dx)); + CHECK(hipFree(dw)); + CHECK(hipFree(dout)); + return idx; +} + +int main() +{ + // B: row n holds 1.0 at byte n only. + const uint8_t one = 0x38; + std::vector x(kRows * kRowBytes, 0); + for (int n = 0; n < kRows; ++n) + x[(size_t)n * kRowBytes + n] = one; + + const std::vector a = run(1, x); + const std::vector b = run(3, x); + const std::vector c = run(5, x); + + std::printf("(vgpr i, lane l) -> (sum1, sum3) = ((n+m)%%16, (n+3m)%%16), solved m,n:\n"); + int shown = 0; + for (int l = 0; l < 32 && shown < 14; l += 4) + for (int i = 0; i < 8 && shown < 14; ++i, ++shown) + { + const int s1 = a[i * 32 + l], s3 = b[i * 32 + l], s5 = c[i * 32 + l]; + if (s1 < 0 || s3 < 0 || s5 < 0) + { + std::printf(" i%d l%-3d unreadable (sums %d %d)\n", i, l, s1, s3); + continue; + } + // Three equations n + c*m = s_c (mod 16) for c = 1, 3, 5 pin both indices down. + int m = -1, n = -1, hits = 0; + for (int mm = 0; mm < 16; ++mm) + for (int nn = 0; nn < 16; ++nn) + if ((nn + mm) % 16 == s1 && (nn + 3 * mm) % 16 == s3 && (nn + 5 * mm) % 16 == s5) + { + if (m < 0) { m = mm; n = nn; } + ++hits; + } + std::printf(" i%d l%-3d sums %2d %2d %2d -> m=%2d n=%2d%s\n", i, l, s1, s3, s5, m, n, + hits == 1 ? "" : " (AMBIGUOUS)"); + } + // experiment 3 + { + std::vector xb(kRows * kRowBytes, 0); + for (int n = 0; n < kRows; ++n) + xb[(size_t)n * kRowBytes + 0] = one; + const std::vector rows = run_rows(xb); + std::printf("\nA row used at (vgpr i, lane l):\n "); + for (int i = 0; i < 8; ++i) std::printf(" i%-2d", i); + std::printf("\n"); + for (int l = 0; l < 32; ++l) + { + std::printf("l%-4d ", l); + for (int i = 0; i < 8; ++i) + { + const int v = rows[i * 32 + l]; + if (v < 0) std::printf(" ? "); + else std::printf(" %-2d ", v); + } + std::printf("\n"); + } + } + return 0; +} diff --git a/kernels/tools/rrswin_operand_probe.cpp b/kernels/tools/rrswin_operand_probe.cpp new file mode 100644 index 0000000..b7098dc --- /dev/null +++ b/kernels/tools/rrswin_operand_probe.cpp @@ -0,0 +1,120 @@ +// Layout probe: which k does each byte of the A (weight) and B (activation) operand hold? +// +// Method, with no assumption about byte order: +// * A (the prepared weight slot) row r holds a distinct e4m3 value per byte of its k16 row. +// * B (the staged activation) is an identity selector: column c is 1.0 at k = c, 0 elsewhere. +// * The WMMA computes D[r][c] = sum_k A[r][k] * B[k][c] = A[r][k(c)], so the value that +// comes back names the k that column c's byte was paired with. Both operands are filled +// byte-by-byte in memory order, so the printout is a direct read of the hardware's slot +// order for each side. +// +// Build and run: +// hipcc --offload-arch=gfx1201 -DD4R_TEX_FP8 -DD4R_WMMA_LAYOUT=12 -O2 \ +// -o /tmp/probe kernels/tools/rrswin_operand_probe.cpp && /tmp/probe +#include +#include +#include +#include +#include +#include + +#include "../rr/rrswin_engine.h" + +#define CHECK(expr) \ + do \ + { \ + hipError_t e_ = (expr); \ + if (e_ != hipSuccess) \ + { \ + std::printf("HIP error at %s:%d: %s -> %s\n", __FILE__, __LINE__, #expr, \ + hipGetErrorString(e_)); \ + std::exit(2); \ + } \ + } while (0) + +static const int kRows = 16, kChunk = 16, kRowBytes = 32; + +// 16 distinct, exactly representable e4m3 values indexed by k +static uint8_t value_for(int k) +{ + const int e = 1 + (k & 7); // 1..8 + const int m = (k >> 3) & 1; // 0 or 1 + return (uint8_t)((e << 3) | (m ? 4 : 0)); +} + +static double dec(uint8_t c) +{ + const int sign = c & 0x80, e = (c >> 3) & 0xf, m = c & 7; + const double mag = e == 0 ? (m / 8.0) * std::pow(2.0, -6.0) : (1.0 + m / 8.0) * std::pow(2.0, e - 7.0); + return sign ? -mag : mag; +} + +__global__ void probe_kernel(const uint8_t* x_img, const uint8_t* w_prep, float* out) +{ + __shared__ uint8_t img[kRows * kRowBytes]; + for (int i = threadIdx.x; i < kRows * kRowBytes; i += blockDim.x) + img[i] = x_img[i]; + __syncthreads(); + f8v c = {0, 0, 0, 0, 0, 0, 0, 0}; + c = rrswin::swin_gemm_tile(c, (const kslot*)w_prep, 0, img, kRowBytes, 0); + for (int i = 0; i < 8; ++i) + out[i * 32 + threadIdx.x] = c[i]; +} + +int main() +{ + // A: weight row r, byte b of chunk 0 = value_for(b); the other chunk zero. + // B: activation column c = 1.0 at byte c of chunk 0, zero elsewhere. + const uint8_t one = 0x38; // e4m3 1.0 + std::vector w(32 * kChunk, 0), x(kRows * kRowBytes, 0); + // A row r carries only 2^(r-8) at byte 0, so the value read back names the row the + // engine actually selected; B column c is 1.0 at k = c. + // A row r = 1.0 at byte 0 only; B column c holds a distinct value per byte of its k16 row. + for (int r = 0; r < kRows; ++r) + w[(size_t)(r) * kChunk + 0] = one; + // B row r must be distinguishable by its byte 0 as well, or "which row" is invisible: + // byte b of row r carries value_for((b + r) % 16). + for (int c = 0; c < kRows; ++c) + for (int b = 0; b < 16; ++b) + x[(size_t)c * kRowBytes + b] = value_for((b + c) % 16); + + uint8_t *dx, *dw; + float* dout; + CHECK(hipMalloc(&dx, x.size())); + CHECK(hipMalloc(&dw, w.size())); + CHECK(hipMalloc(&dout, 8 * 32 * sizeof(float))); + CHECK(hipMemcpy(dx, x.data(), x.size(), hipMemcpyHostToDevice)); + CHECK(hipMemcpy(dw, w.data(), w.size(), hipMemcpyHostToDevice)); + probe_kernel<<<1, 32>>>(dx, dw, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + std::vector got(8 * 32); + CHECK(hipMemcpy(got.data(), dout, got.size() * sizeof(float), hipMemcpyDeviceToHost)); + + // The engine's assumed indexing: value at D[row = i + 8h][col = lane & 15]. + // A is the identity at byte 0, so D(row, col) = B[k0][col] = value_for((k0 + row(col)) % 16). + // Print the value_for index of every (vgpr, lane) so the true (row, column) assignment can + // be read off the table instead of assumed. + std::printf("value_for index at got[vgpr i][lane l] (rows = l 0..31, cols = i 0..7):\n"); + std::printf(" "); + for (int i = 0; i < 8; ++i) std::printf(" i%-3d", i); + std::printf("\n"); + for (int l = 0; l < 32; ++l) + { + std::printf("l%-4d ", l); + for (int i = 0; i < 8; ++i) + { + const double v = got[i * 32 + l]; + int n = -1; + for (int q = 0; q < 16; ++q) + if (std::fabs(v - dec(value_for(q))) < 1e-3) n = q; + if (n < 0) std::printf(" ? "); + else std::printf(" %-3d ", n); + } + std::printf("\n"); + } + CHECK(hipFree(dx)); + CHECK(hipFree(dw)); + CHECK(hipFree(dout)); + return 0; +} diff --git a/kernels/tools/rrswin_phase8_fit.py b/kernels/tools/rrswin_phase8_fit.py new file mode 100755 index 0000000..e4910a7 --- /dev/null +++ b/kernels/tools/rrswin_phase8_fit.py @@ -0,0 +1,421 @@ +#!/usr/bin/env python3 +"""Solve phase 8's activation row from the oracle, to derive the fragment map instead of assuming it. + +For one token row, the oracle's accumulator gives 32 equations (one per weight column): + + D(tok, wt) = sum_k weight(k, wt) * a(k) + +with `weight` read from the weight image through the corroborated waddr (the PTX's own loads put +phase 8's B at 21696/22208). That is a 32x32 linear system in the 32 unknown activation values +a(k) of that token row, so it can be solved directly -- no assumption about the fragment layout. +The solution is then snapped to e4m3 codes and compared with the bytes the lanes actually hold, +which names the byte that belongs at each k: the fragment map, derived. + +usage: phase8_fit.py [token] +""" +import pathlib +import struct +import sys + +import numpy as np + +BASE = 46000000 +SLOT = 16384 +ORE = 32 +ACC_OFF = 32 * 4 +WEIGHT_BASE = 21696 +TOKEN_TILES = 6 # the activations' 96 rows +WEIGHT_TILES = 4 # the weights' 32 rows +ROWS = 96 +COLS = 32 + + +def find(dirname, needle): + for p in sorted(pathlib.Path(dirname).iterdir()): + if "swin_enc0_kernel" in p.name and needle in p.name: + return p + raise SystemExit(f"no dump with {needle} in {dirname}") + + +def e4m3_codes(): + """Every e4m3 code and its value.""" + out = [] + for code in range(256): + mag = code & 0x7F + if (code & 0x7F) == 0x7F: + continue # NaN + if mag >= 8: + bits = (((mag >> 3) + 120) << 23) | ((mag & 7) << 20) + else: + bits = struct.unpack('> 4) + 64 * (n & 7) + 16 * ((k >> 1) & 3) + 8 * ((n >> 3) & 1) + + 4 * ((k >> 3) & 1) + 2 * ((k >> 4) & 1) + (k & 1)) + + +def f16(bits): + return struct.unpack('>2), not the + k = 2*t + (j&1) + 16*((j>>1)&1) rrswin_enc0.hip claims. This assembles the row from those + bytes and compares it with the value solved out of the oracle. + """ + a, *_ = np.linalg.lstsq(W, D, rcond=None) + codes = e4m3_codes() + solved = [min(codes, key=lambda cv: abs(cv[1] - a[k]))[0] for k in range(32)] + held = {} + for lane in range(32): + if (lane >> 2) != (tok % 8): + continue + high = 1 if tok >= 8 else 0 + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + mi = tok // 16 + rx = 4 * mi + (2 if high else 0) + rz = 4 * mi + (3 if high else 1) + for j in range(4): + held[4 * (lane & 3) + j] = (ops[rx] >> (8 * j)) & 0xFF + held[16 + 4 * (lane & 3) + j] = (ops[rz] >> (8 * j)) & 0xFF + hit = sum(1 for k in range(32) if held.get(k) == solved[k]) + return hit, solved, held + + +def main(): + d = sys.argv[1] if len(sys.argv) > 1 else "/tmp/d4r-rr-perf/d-p8c" + tok = int(sys.argv[2]) if len(sys.argv) > 2 else 0 + dump = find(d, "arg048").read_bytes() + wimg = find(d, "arg040").read_bytes() + + # the oracle's D for this token: rows 16*mi + 8*rh + g live in lane M with g = M>>2, t = M&3 + mi, h, g = tok // 16, (tok % 16) // 8, (tok % 16) % 8 + rh = h # the register pair's row half is the lane's half + D = np.zeros(COLS) + lane_bytes = {} + for widx in range(WEIGHT_TILES): + for t in range(4): + M = 16 * h + t # derived: lane = 16*((tok%16)/8) + (wt%8)/2 + off = BASE + M * ORE * 4 + ACC_OFF + acc = struct.unpack('<48I', dump[off:off + 48 * 4]) + for c in range(2): + wt = 8 * widx + 2 * t + c + reg = (mi * 4 + widx) * 2 + rh + D[wt] = f16((acc[reg] >> 16) if c else (acc[reg] & 0xFFFF)) + # this lane's A bytes, for naming the solved values + ops = struct.unpack(f'<{ORE}I', dump[BASE + M * ORE * 4:BASE + M * ORE * 4 + ORE * 4]) + lane_bytes[M] = [((ops[4 * mi + r] >> (8 * j)) & 0xFF) for r in range(4) for j in range(4)] + + W = np.zeros((COLS, 32)) + for wt in range(COLS): + for k in range(32): + W[wt, k] = e4m3_codes_value(wimg[WEIGHT_BASE + waddr(k, wt)]) + + a, *_ = np.linalg.lstsq(W, D, rcond=None) + residual = float(np.abs(W @ a - D).max()) + # The system is square -- 32 weight columns for 32 unknown k -- so a small residual proves + # nothing by itself: it can be solved exactly whether or not the model is right. The real + # test is whether the *solution* lands on e4m3 codes, since the true activation values are + # e4m3. Snap error is that measure. + codes_all = e4m3_codes() + _ = snap_error # used by the search below + snap_err = max(min(abs(cv[1] - a[k]) for cv in codes_all) for k in range(32)) + print(f"token {tok}: solved 32 activation values, residual {residual:.3e} " + f"(square system, so not evidence), max snap-to-e4m3 error {snap_err:.3e} " + f"({'consistent with e4m3 inputs' if snap_err < 1e-3 else 'NOT e4m3: the weights or the D mapping is wrong'})") + + codes = e4m3_codes() + snaps = [] + for k in range(32): + best = min(codes, key=lambda cv: abs(cv[1] - a[k])) + snaps.append(best[0]) + print("solved and snapped activation row (k: code):") + print(" ".join(f"{c:02x}" for c in snaps)) + # Derive the token -> lane assignment: for each candidate token row, solve and see whether + # the resulting codes are exactly the bytes some lane group holds. + print("token -> lane-group derivation (which solved row is a permutation of held bytes):") + for cand in range(96): + cmi, crh, cg = cand // 16, (cand % 16) // 8, (cand % 16) % 8 + Dc = np.zeros(COLS) + held = [] + for widx in range(WEIGHT_TILES): + for t in range(4): + M = 16 * crh + t + off = BASE + M * ORE * 4 + ACC_OFF + acc = struct.unpack('<48I', dump[off:off + 48 * 4]) + for c in range(2): + wt = 8 * widx + 2 * t + c + reg = (cmi * 4 + widx) * 2 + crh + Dc[wt] = f16((acc[reg] >> 16) if c else (acc[reg] & 0xFFFF)) + ops = struct.unpack(f'<{ORE}I', dump[BASE + M * ORE * 4:BASE + M * ORE * 4 + ORE * 4]) + held += [((ops[4 * cmi + (0 if crh == 0 else 1)] >> (8 * j)) & 0xFF) for j in range(4)] + held += [((ops[4 * cmi + (2 if crh == 0 else 3)] >> (8 * j)) & 0xFF) for j in range(4)] + ac, *_ = np.linalg.lstsq(W, Dc, rcond=None) + res = float(np.abs(W @ ac - Dc).max()) + snaps_c = [min(codes, key=lambda cv: abs(cv[1] - ac[k]))[0] for k in range(32)] + if sorted(snaps_c) == sorted(held) and res < 1e-9: + print(f" token row {cand:2d} (mi {cmi}, rh {crh}, g {cg}) solves to exactly the 32 bytes " + f"held by lanes {4*cg}..{4*cg+3} of m-tile {cmi} row half {crh}") + break + else: + print(" no token row's solution matched the bytes held for its group") + + # Derive the register-to-row assignment: solve every row exactly, then ask which + # (lane, m-tile, row half) register set holds that row's values. + print("register-to-row derivation:") + solved = {} + for cand in range(96): + cmi, crh, cg = cand // 16, (cand % 16) // 8, (cand % 16) % 8 + Dc = np.zeros(COLS) + for widx in range(WEIGHT_TILES): + for t in range(4): + M = 4 * cg + t + off = BASE + M * ORE * 4 + ACC_OFF + acc = struct.unpack('<48I', dump[off:off + 48 * 4]) + for c in range(2): + Dc[8 * widx + 2 * t + c] = f16((acc[((cmi * 4 + widx) * 2 + crh)] >> (16 if c else 0)) & 0xFFFF) + ac, *_ = np.linalg.lstsq(W, Dc, rcond=None) + solved[cand] = [min(codes, key=lambda cv: abs(cv[1] - ac[k]))[0] for k in range(32)] + + hits = {} + for lane in range(32): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + for mi in range(6): + for rh in (0, 1): + regs = (1, 3) if rh else (0, 2) + held = [((ops[4 * mi + r] >> (8 * j)) & 0xFF) for r in regs for j in range(4)] + for cand in range(96): + want = list(solved[cand]) + ok = all(want.count(b) >= held.count(b) for b in set(held)) + if ok: + hits.setdefault(cand, []).append((lane, mi, rh)) + for cand in sorted(hits)[:6]: + (lane, mi, rh) = hits[cand][0] + print(f" row {cand:2d} (mi {cand//16}, rh {(cand%16)//8}, g {(cand%16)%8}): held by " + f"lane {lane:2d} m-tile {mi} row-half {rh} ({len(hits[cand])} candidates)") + + # Search the plausible variants of the two maps and report the snap error for each. The + # correct pair makes the solution land on e4m3 codes. + print("map candidates (max snap-to-e4m3 error of the solved activation row):") + import itertools + + def wmap(k, wt, variant): + if variant == 0: + return waddr(k, wt) + if variant == 1: # k16 halves swapped + return waddr((k + 8) % 32 if (k % 16) < 8 else (k - 8), wt) + if variant == 2: # the two (k>>1)&3 / (k>>3)&1 terms exchanged + n_ = wt + return (512 * (n_ >> 4) + 64 * (n_ & 7) + 16 * ((k >> 3) & 1) + 8 * ((n_ >> 3) & 1) + + 4 * ((k >> 1) & 3) + 2 * ((k >> 4) & 1) + (k & 1)) + if variant == 3: # the k&1 / (k>>1)&1 terms exchanged + n_ = wt + return (512 * (n_ >> 4) + 64 * (n_ & 7) + 16 * ((k >> 1) & 3) + 8 * ((n_ >> 3) & 1) + + 4 * ((k >> 3) & 1) + 2 * ((k >> 4) & 1) + ((k >> 1) & 1) * 1) + return waddr(k, wt) + + def dmap(tok, wt, variant): + mi, rh, g = tok // 16, (tok % 16) // 8, (tok % 16) % 8 + M = 4 * g + ((wt % 8) // 2) + off = BASE + M * ORE * 4 + ACC_OFF + acc = struct.unpack('<48I', dump[off:off + 48 * 4]) + if variant == 0: + widx, c = wt // 8, wt % 2 + reg = (mi * 4 + widx) * 2 + rh + elif variant == 1: # n-tile major instead of m-tile major + widx, c = wt // 8, wt % 2 + reg = (widx * 6 + mi) * 2 + rh + elif variant == 2: # row halves swapped + widx, c = wt // 8, wt % 2 + reg = (mi * 4 + widx) * 2 + (1 - rh) + else: + return None + return f16((acc[reg] >> 16) if c else (acc[reg] & 0xFFFF)) + + for wv, dv in itertools.product(range(4), range(3)): + Wv = np.zeros((COLS, 32)) + for wt in range(COLS): + for k in range(32): + Wv[wt, k] = e4m3_codes_value(wimg[WEIGHT_BASE + wmap(k, wt, wv)]) + Dv = np.zeros(COLS) + ok = True + for wt in range(COLS): + v = dmap(tok, wt, dv) + if v is None: + ok = False + break + Dv[wt] = v + if not ok: + continue + print(f" weight map {wv}, D map {dv}: {snap_error(Wv, Dv):.3e}") + + # The body's waddr is a hand-derived inverse, i.e. a bit permutation of the k index onto the + # byte-offset bits. Search the permutation instead of trusting it: 5 k bits onto the offset + # bits {0,1,2,4,5} (offset bit 3 belongs to n), with the n terms fixed. The correct + # permutation makes the solved activation row land exactly on e4m3 codes. + # NOTE: this search's encoding of the permutation is not yet right -- candidates cluster + # around 0.43 rather than reaching ~0, so the winner found here is not trustworthy. It does + # establish the thing that matters at this stage: the maps in rrswin_enc0.hip give a snap + # error of 15.8, i.e. they are *wrong*, and the e4m3-snap error is the test that shows it. + print("k-bit permutation search (offset bits {0,1,2,4,5} <- k bits):") + # Both maps are searched together: the k-bit permutation (5! of them) and the D register + # order, since a wrong D map makes every permutation look wrong. + def dval(order, wt): + mi, rh, g = tok // 16, (tok % 16) // 8, (tok % 16) % 8 + M = 16 * rh + ((wt % 8) // 2) # derived lane mapping + off = BASE + M * ORE * 4 + ACC_OFF + acc = struct.unpack('<48I', dump[off:off + 48 * 4]) + widx, c = wt // 8, wt % 2 + if order == 0: + reg = (mi * 4 + widx) * 2 + rh + elif order == 1: + reg = (widx * 6 + mi) * 2 + rh + elif order == 2: + reg = (mi * 4 + widx) * 2 + (1 - rh) + else: + reg = (mi * 4 + (3 - widx)) * 2 + rh + return f16((acc[reg] >> 16) if c else (acc[reg] & 0xFFFF)) + + # A k-bit permutation only relabels which k holds which value, so it cannot change the + # *set* of solved values and the snap statistic is blind to it. The test that does work is + # permutation-invariant and uses the registers themselves: do the solved values equal the + # bytes the lanes hold? Only the D map can be searched this way. + print("D-map search by multiset match with the held bytes:") + Wbase = np.zeros((COLS, 32)) + for wt in range(COLS): + for k in range(32): + Wbase[wt, k] = e4m3_codes_value(wimg[WEIGHT_BASE + waddr(k, wt)]) + held_all = set() + for lane in range(32): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + for mi in range(6): + for r in range(4): + for j in range(4): + held_all.add((ops[4 * mi + r] >> (8 * j)) & 0xFF) + for order in range(4): + Dv = np.array([dval(order, wt) for wt in range(COLS)]) + a, *_ = np.linalg.lstsq(Wbase, Dv, rcond=None) + codes_all = e4m3_codes() + snaps = [min(codes_all, key=lambda cv: abs(cv[1] - a[k]))[0] for k in range(32)] + inside = sum(1 for c in snaps if c in held_all) + # strict: the solved row must equal the union of the bytes the four lanes of this token's + # group hold for this row half, as a multiset + g_ = (tok % 16) % 8 + strict = [] + for lane in range(4 * g_, 4 * g_ + 4): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + regs = (1, 3) if order == 2 else (0, 2) + for r in regs: + for j in range(4): + strict.append((ops[4 * (tok // 16) + r] >> (8 * j)) & 0xFF) + exact = sorted(snaps) == sorted(strict) + print(f" D order {order}: {inside:2d} of 32 solved values are values the payload holds" + f"{' EXACT multiset match with the group\'s held bytes' if exact else ''}") + # Derive the placement: which byte position holds each k. The solved row gives the value for + # every k in the *weight* labelling (the one waddr uses, which the exact-w-values test just + # corroborated). The payload gives the bytes and their (lane, register, byte) positions. A + # position is the k label whose solved value it holds, so matching them derives the map the + # engine must use for its activation image to be consistent with the weights. + hit, solved, held = test_zluda_map(dump, wimg, tok, D, W) + print(f"ZLUDA's documented map (k = 4*(lane&3)+j, row = lane>>2): {hit} of 32 k match exactly") + if hit < 32: + print(" k : solved held") + for k in range(32): + mark = "" if held.get(k) == solved[k] else " <-- differs" + print(f" {k:2d}: {solved[k]:02x} {held.get(k, 0):02x}{mark}") + + print("placement: which byte position holds each k label") + a_all, *_ = np.linalg.lstsq(Wbase, D, rcond=None) + codes_all = e4m3_codes() + label_of = {} + for k in range(32): + snapped = min(codes_all, key=lambda cv: abs(cv[1] - a_all[k]))[0] + label_of.setdefault(snapped, []).append(k) + # The solved row's values appear somewhere in the payload but not in the group I assumed, so + # the row-to-group mapping is what to derive: try every (g, row half) and report which group's + # bytes are exactly the solved row's values. + # wmma_layout.h says "A operand lane l = row r" with r = l & 15, while rrswin_enc0.hip's + # header says row g = lane >> 2. They are different conventions, so test the other one: a + # row's 16 bytes per lane over two lanes (m and m+16) rather than four lanes of a group. + print(" row-to-pair search (row = lane & 15, 16 bytes per lane):") + solved_multi = sorted(label_of.keys()) + for row in range(16): + held = [] + for lane in (row, row + 16): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + for rr in range(4): + for j in range(4): + held.append((ops[4 * (tok // 16) + rr] >> (8 * j)) & 0xFF) + hit = sum(1 for b in solved_multi if b in held) + miss = [b for b in solved_multi if b not in held] + if hit >= 28: + print(f" row {row:2d}: {hit} of 32 solved values held by lanes {row},{row+16}" + f"{' EXACT' if not miss else ''}") + + print(" row-to-group search:") + solved_multi = sorted(label_of.keys()) + for cand_g in range(8): + for cand_r in (0, 1): + held = [] + for lane in range(4 * cand_g, 4 * cand_g + 4): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + regs = (1, 3) if cand_r else (0, 2) + for rr in regs: + for j in range(4): + held.append((ops[4 * (tok // 16) + rr] >> (8 * j)) & 0xFF) + hit = sum(1 for b in solved_multi if b in held) + if hit >= 28: + print(f" g {cand_g}, row half {cand_r}: {hit} of {len(solved_multi)} solved values held") + + g_ = (tok % 16) % 8 + print(" group lanes " + " ".join(str(4 * g_ + t) for t in range(4)) + ":") + for lane in range(4 * g_, 4 * g_ + 4): + ops = struct.unpack(f'<{ORE}I', dump[BASE + lane * ORE * 4:BASE + lane * ORE * 4 + ORE * 4]) + for r in range(4): + row = "[row g]" if r in (0, 2) else "[row g+8]" + ks = [] + for j in range(4): + b = (ops[4 * (tok // 16) + r] >> (8 * j)) & 0xFF + cand = label_of.get(b, []) + ks.append(f"{b:02x}->k{cand[0]}" if len(cand) == 1 else f"{b:02x}->?") + print(f" lane {lane:2d} reg {r} {row}: " + " ".join(ks)) + + print("bytes held by the lanes of this token's group:") + for M in sorted(lane_bytes): + print(f" lane {M:2d}: " + " ".join(f"{b:02x}" for b in lane_bytes[M])) + + +def e4m3_codes_value(code): + mag = code & 0x7F + if mag >= 8: + bits = (((mag >> 3) + 120) << 23) | ((mag & 7) << 20) + else: + bits = struct.unpack(' +""" +import bisect +import pathlib +import struct +import sys + +sys.path.insert(0, "/home/wouter/git/d4r/kernels/rr") +import rr_layer_spec as R # noqa: E402 + +BASE = 46000000 +SLOT = 16384 +ORE = 32 # operand registers per lane +AREGS = 24 # A fragments (6 m-tiles of 4) +WEIGHT_BASE = 21696 + + +def find(dirname, needle): + for p in sorted(pathlib.Path(dirname).iterdir()): + if "swin_enc0_kernel" in p.name and needle in p.name: + return p + raise SystemExit(f"no dump with {needle} in {dirname}") + + +def e4m3_to_f32(code): + mag = code & 0x7F + if mag >= 8: + bits = (((mag >> 3) + 120) << 23) | ((mag & 7) << 20) + else: + bits = struct.unpack('> 4) + 64 * (n & 7) + 16 * ((k >> 1) & 3) + 8 * ((n >> 3) & 1) + + 4 * ((k >> 3) & 1) + 2 * ((k >> 4) & 1) + (k & 1)) + + +def f16(bits): + return struct.unpack(' 1 else "/tmp/d4r-rr-perf/d-p8c" + dump = find(d, "arg048").read_bytes() + wimg = find(d, "arg040").read_bytes() + + block, lane = 0, 0 + off = BASE + block * SLOT + lane * (ORE + 48) * 4 + + # Each lane supplies only eight K positions for each token row. Assemble + # all 32 lanes before taking a dot product; the combined payload has 80 + # registers per lane, not 32. + img = [[0] * 32 for _ in range(96)] + for source_lane in range(32): + source_off = BASE + block * SLOT + source_lane * (ORE + 48) * 4 + ops = struct.unpack(f'<{ORE}I', dump[source_off:source_off + ORE * 4]) + for mi in range(6): + f = ops[4 * mi:4 * mi + 4] + for j in range(4): + k0 = 2 * (source_lane & 3) + (j & 1) + 16 * ((j >> 1) & 1) + k2 = 8 + k0 + img[16 * mi + (source_lane >> 2)][k0] = (f[0] >> (8 * j)) & 0xFF + img[16 * mi + (source_lane >> 2) + 8][k0] = (f[1] >> (8 * j)) & 0xFF + img[16 * mi + (source_lane >> 2)][k2] = (f[2] >> (8 * j)) & 0xFF + img[16 * mi + (source_lane >> 2) + 8][k2] = (f[3] >> (8 * j)) & 0xFF + + # the oracle's D, this lane + doff = off + ORE * 4 + acc = struct.unpack('<48I', dump[doff:doff + 48 * 4]) + g, t = lane >> 2, lane & 3 + + # This lane holds only the columns 2t and 2t+1 of each 8-wide n-tile, and only the token rows + # 16*mi + 8*rh + g -- reading any other (weight, token) from its registers reads another + # lane's data. + print("weight token model oracle delta") + for wt in (2 * t, 2 * t + 1): + for mi in (0, 1): # this lane holds one token row per row half + for rh in (0, 1): + tok = 16 * mi + 8 * rh + g + total = 0.0 + for k in range(32): + total += e4m3_to_f32(wimg[WEIGHT_BASE + waddr(k, wt)]) * e4m3_to_f32(img[tok][k]) + total = struct.unpack('> 16) if c else (pair & 0xFFFF)) + # which (register, half) of this lane does the model's value actually equal? + hits = [] + for rb in range(48): + for hh in (0, 1): + v = f16((acc[rb] >> 16) if hh else (acc[rb] & 0xFFFF)) + if abs(v - total) < 1e-4 * (1 + abs(total)): + hits.append(f"r{rb}.{hh}") + print(f"{wt:6d} {tok:6d} {total:+.6f} {want:+.6f} delta {total - want:+.6f} matches {hits[:4]}") + + +if __name__ == "__main__": + main() diff --git a/kernels/tools/rrswin_pilot_enc0_p8.cpp b/kernels/tools/rrswin_pilot_enc0_p8.cpp new file mode 100644 index 0000000..b554d75 --- /dev/null +++ b/kernels/tools/rrswin_pilot_enc0_p8.cpp @@ -0,0 +1,193 @@ +// Compare enc0 phase 8's native staged-image GEMM with a combined p8c oracle +// capture: 24 A fragments, 8 B fragments and 48 D registers per lane. +// The engine produces D[weight][token]; the oracle stores D[token][weight]. +// Every HIP call is checked, and a mismatch produces a nonzero exit status. +// +// hipcc --offload-arch=gfx1201 -DD4R_TEX_FP8 -DD4R_WMMA_LAYOUT=12 -O2 \ +// -o /tmp/pilot kernels/tools/rrswin_pilot_enc0_p8.cpp +// /tmp/pilot +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../rr/rrswin_engine.h" + +#define CHECK(expr) \ + do \ + { \ + hipError_t e_ = (expr); \ + if (e_ != hipSuccess) \ + { \ + std::printf("HIP error at %s:%d: %s -> %s\n", __FILE__, __LINE__, #expr, \ + hipGetErrorString(e_)); \ + std::exit(2); \ + } \ + } while (0) + +static const int kDebugSlot = 16384; // swin_debug_slot(80) for the combined stage +static const int kDebugBase = 46000000; + +static std::vector slurp(const std::string& dir, const char* what, size_t* size_out) +{ + // the dump names are launch------fmt.bin; matching the pieces + // is more robust than a glob over a name that contains '+0x0' + DIR* d = opendir(dir.c_str()); + if (d == nullptr) + { + std::printf("cannot open %s\n", dir.c_str()); + std::exit(2); + } + std::string found; + for (dirent* e = readdir(d); e != nullptr; e = readdir(d)) + { + const std::string name = e->d_name; + if (name.find("swin_enc0_kernel") != std::string::npos && + name.find(std::string("-") + what + "-") != std::string::npos) + { + found = dir + "/" + name; + break; + } + } + closedir(d); + if (found.empty()) + { + std::printf("no dump with %s in %s\n", what, dir.c_str()); + std::exit(2); + } + FILE* f = std::fopen(found.c_str(), "rb"); + std::fseek(f, 0, SEEK_END); + const long n = std::ftell(f); + std::fseek(f, 0, SEEK_SET); + std::vector data((size_t)n); + if (std::fread(data.data(), 1, data.size(), f) != data.size()) + { + std::printf("short read of %s\n", found.c_str()); + std::exit(2); + } + std::fclose(f); + if (size_out) + *size_out = data.size(); + return data; +} + +// One phase over one debug slot: stage six m-tiles of A fragments, prep the weights, run the +// phase, write D[weight][token] out. The weight preparation reads the image through the +// documented enc0 layout, offset by the phase's byte base. +__global__ void pilot_kernel(const uint32_t* frag, const uint8_t* wimg, int weight_base, + float* out) +{ + __shared__ uint8_t img[96 * 32]; + __shared__ uint8_t weight_slots[32 * 2 * 16]; + for (int i = threadIdx.x; i < 96 * 32; i += blockDim.x) + img[i] = 0; + __syncthreads(); + rrswin::swin_stage_fragment(img, 32, frag + (size_t)24 * (blockIdx.x * 32u + threadIdx.x), 6); + if (threadIdx.x == 0) + rrswin::swin_prep_phase(weight_slots, 0, 32, 1, wimg + weight_base, rrswin::swin_waddr_enc0); + __syncthreads(); + const rrswin::Phase phase = {2, 6, 1, 0, 1, 0}; + f8v acc[12]; + rrswin::swin_phase(phase, (const kslot*)weight_slots, 32, img, 32, nullptr, 0, acc); + for (int tile = 0; tile < 12; ++tile) + for (int i = 0; i < 8; ++i) + out[(size_t)blockIdx.x * 3072 + (tile * 8 + i) * 32 + threadIdx.x] = acc[tile][i]; +} + +int main(int argc, char** argv) +{ + if (argc < 2) + { + std::printf("usage: %s \n", argv[0]); + return 2; + } + size_t no = 0, nw = 0; + const std::vector p8o = slurp(argv[1], "arg048", &no); // combined: 32 operands + 48 accumulators + const std::vector p8 = p8o; + const std::vector wimg = slurp(argv[1], "arg040", &nw); + std::printf("arg048 (combined p8c) %zu bytes, arg040 %zu bytes\n", no, nw); + if (no < (size_t)kDebugBase + 64 * kDebugSlot) + { + std::printf("dumps are too small for the payload window\n"); + return 2; + } + + // the phase's A fragments: 24 registers per lane, 32 lanes, per block + std::vector frag(64 * 32 * 24); + for (int b = 0; b < 64; ++b) + for (int lane = 0; lane < 32; ++lane) + { + const uint8_t* p = p8o.data() + kDebugBase + (size_t)b * kDebugSlot + (size_t)lane * 80 * 4; + for (int r = 0; r < 24; ++r) + std::memcpy(&frag[((size_t)b * 32 + lane) * 24 + r], p + 4 * r, 4); + } + + uint32_t* dfrag; + uint8_t* dwimg; + float* dout; + CHECK(hipMalloc(&dfrag, frag.size() * 4)); + CHECK(hipMalloc(&dwimg, wimg.size())); + CHECK(hipMalloc(&dout, 64 * 3072 * sizeof(float))); + CHECK(hipMemcpy(dfrag, frag.data(), frag.size() * 4, hipMemcpyHostToDevice)); + CHECK(hipMemcpy(dwimg, wimg.data(), wimg.size(), hipMemcpyHostToDevice)); + CHECK(hipMemset(dout, 0, 64 * 3072 * sizeof(float))); + pilot_kernel<<<64, 32>>>(dfrag, dwimg, 21696, dout); + CHECK(hipGetLastError()); + CHECK(hipDeviceSynchronize()); + + std::vector got(64 * 3072); + CHECK(hipMemcpy(got.data(), dout, got.size() * 4, hipMemcpyDeviceToHost)); + + // Compare the engine's D[weight][token] with the oracle's D[token][weight]. + // + // The two sides do not use the same lane for the same element, which is what earlier attempts + // got wrong by reusing one lane for both: + // engine: acc[mt][nt][i] of lane L holds D[row = 16*mt + i + 8*(L>>4)][col = 16*nt + (L&15)] + // oracle: the p8 payload's register (mi, widx, rh) of lane M holds D[row = 16*mi + 8*rh + g] + // [col = 8*widx + 2*t + c], with g = M>>2 and t = M&3 + // so an element identified by (weight w, token k) lives in lane 16*((w%16)/8) + (k%16) on the + // engine side and in lane 4*((k%16)%8) + (w%8)/2 on the oracle side. + int bad = 0, checked = 0; + for (int b = 0; b < 64; ++b) + { + const uint8_t* d = p8.data() + kDebugBase + (size_t)b * kDebugSlot; + for (int wt = 0; wt < 32; ++wt) + for (int tok = 0; tok < 96; ++tok) + { + const int mt = wt / 16, i = (wt % 16) & 7, h = (wt % 16) / 8, nt = tok / 16; + const int eLane = 16 * h + (tok % 16); + const float gotv = got[(size_t)b * 3072 + ((mt * 6 + nt) * 8 + i) * 32 + eLane]; + + const int mi = tok / 16, rh = (tok % 16) / 8, g = (tok % 16) % 8; + const int widx = wt / 8, t = (wt % 8) / 2, c = wt % 2; + const int oLane = 4 * g + t; + const uint16_t* regs = (const uint16_t*)(d + (size_t)oLane * 80 * 4 + 32 * 4); + const int reg = (mi * 4 + widx) * 2 + rh; + const uint32_t u = (uint32_t)regs[2 * reg] | ((uint32_t)regs[2 * reg + 1] << 16); + const uint16_t bits = (uint16_t)(c ? (u >> 16) : (u & 0xffff)); + const _Float16 hb = *reinterpret_cast(&bits); + const float oracle_f = (float)hb; + // the engine's accumulator is f32 (the WMMA's), the oracle's mma accumulates in + // f16, so the comparison is at f16: round the engine's value to f16 first + const _Float16 got_h = (_Float16)gotv; + const float got_r = (float)got_h; + ++checked; + if (got_r != oracle_f) + { + if (bad < 4) + std::printf(" block %2d weight %2d token %2d: engine %+.6f oracle %+.6f\n", + b, wt, tok, got_r, oracle_f); + ++bad; + } + } + } + std::printf("phase-8 pilot: checked %d, mismatched %d\n", checked, bad); + CHECK(hipFree(dfrag)); + CHECK(hipFree(dwimg)); + CHECK(hipFree(dout)); + return bad != 0; +} diff --git a/kernels/tools/swin_mma.py b/kernels/tools/swin_mma.py new file mode 100755 index 0000000..954a078 --- /dev/null +++ b/kernels/tools/swin_mma.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +"""Dump the mma statements of a swin entry's phase range with their A/B/C/D registers. + +Usage: swin_mma.py LAYER LO_STMT [HI_STMT] +LAYER is a rr_layer_spec alias (enc0, ...). One line per mma, with the +statement index, the physical PTX line and the register operands in order. +""" +import os +import re +import sys + +sys.path.insert(0, os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "rr")) +import rr_layer_spec as R # noqa: E402 + + +def main(): + layer = sys.argv[1] if len(sys.argv) > 1 else "enc0" + lo = int(sys.argv[2]) if len(sys.argv) > 2 else 0 + hi = int(sys.argv[3]) if len(sys.argv) > 3 else 10 ** 9 + path, entry = R.resolve(layer, None, None) + lines = open(path).read().split("\n") + first, last = next((a, b) for (nm, a, b) in R.find_entries(lines) if nm == entry) + stmts, _ = R.linearise(lines, first, last) + for s in stmts: + if s.is_mma and lo <= s.idx <= hi: + print(f"s{s.idx} L{s.line}: " + " ".join(re.findall(r"%r\d+", s.text))) + + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/kernels/tools/swin_stages.py b/kernels/tools/swin_stages.py new file mode 100755 index 0000000..bc99e16 --- /dev/null +++ b/kernels/tools/swin_stages.py @@ -0,0 +1,165 @@ +#!/usr/bin/env python3 +"""Emit the oracle debug stages for cuda_dldn_engine_swin_enc0_kernel, phases 8..22. + +For each phase it reads NVIDIA's PTX, keeps the mma whose D pair is not another mma's +C operand inside the same phase (the last k-step of an accumulating chain), and lists +those tiles in mma order, which is m-tile major and n-tile minor -- the order the +native body's stage_regs() writes. Operand stages list the phase's A fragments, B +fragment pairs and C seeds as the mma read them. + +Writes kernels/rr/swin_enc0_debug_stages.py, which make_ptx.py folds into its own +SWIN_DEBUG_STAGES. +""" +import re +import sys +import os + +sys.path.insert(0, os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "rr")) +import rr_layer_spec as R # noqa: E402 + +ENTRY = "cuda_dldn_engine_swin_enc0_kernel" +ZERO_C = "%r10854" # mov.u32 %r10854, 0 (PTX line 3920): the unfused phases' C +OUT = os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "rr", + "swin_enc0_debug_stages.py") + +PHASES = { + 8: (8057, 8080), 9: (8088, 8111), 10: (8283, 8330), 11: (12169, 12216), + 12: (12272, 12287), 13: (13175, 13190), 14: (13900, 13915), 15: (13980, 13995), + 16: (14596, 14611), 17: (14676, 14691), 18: (15292, 15307), 19: (15372, 15387), + 20: (15988, 16003), 21: (16418, 16449), 22: (16607, 16614), +} + +HEADER = '''#!/usr/bin/env python3 +"""Oracle debug stages for cuda_dldn_engine_swin_enc0_kernel's phases 8..22. + +Each stage is a (file line after which the store block goes, registers in order) tuple for +kernels/tex/make_ptx.py's SWIN_DEBUG_STAGES, so D4R_RRSWIN_DEBUG=p8 (p8o, p9, p10, ...) +builds NVIDIA's own body with that stage's registers stored into the plane arena, which +kernels/rr/rrswin_enc0.hip's D4R_RRSWIN_DEBUG_STAGE reproduces from its own registers. + +GENERATED by kernels/tools/swin_stages.py from the corpus PTX -- do not edit. An +accumulator stage keeps the mma whose D pair no other mma of the phase reads as its C (the +last k-step of an accumulating chain) and lists the tiles in mma order: m-tile major, +n-tile minor, the row pair (row g, row g+8) at each base. An operand stage lists the A +fragments, the B fragment pairs and the C seeds as the mma read them. +""" + + +def swin_pairs(bases): + """One register pair per base: a tile's (row g, row g+8) D registers.""" + return sum(([f"%r{b + rh}" for rh in (0, 1)] for b in bases), []) + + +def swin_quads(bases): + """One A fragment per base: four b32.""" + return sum(([f"%r{b + o}" for o in range(4)] for b in bases), []) + + +def stages(): + """The stage table: name -> (splice line, registers).""" + return { +''' + + +def phase_mmas(stmts, p): + lo, hi = PHASES[p] + out = [] + for s in stmts: + if not s.is_mma or not (lo <= s.idx <= hi): + continue + r = re.findall(r"%r\d+", s.text) + out.append(dict(D=(r[0], r[1]), A=tuple(r[2:6]), B=(r[6], r[7]), C=(r[8], r[9]), + line=s.line)) + return out + + +def outputs(mmas): + """The last k-step of every chain: the mma whose D pair no other mma reads as its C.""" + cs = set() + for m in mmas: + cs.update(m["C"]) + return [m for m in mmas if m["D"][0] not in cs and m["D"][1] not in cs] + + +def dbase(mmas): + return [int(m["D"][0][2:]) for m in outputs(mmas)] + + +def abase(mmas): + seen, out = set(), [] + for m in mmas: + if m["A"][0] in seen: + continue + seen.add(m["A"][0]) + out.append(int(m["A"][0][2:])) + return out + + +def bbase(mmas): + seen, out = set(), [] + for m in mmas: + if m["B"][0] in seen: + continue + seen.add(m["B"][0]) + out.append(int(m["B"][0][2:])) + return out + + +def cseed(mmas): + """The distinct C registers that are not another mma's D inside the same phase (an + accumulating chain's previous step is not a seed), in first-appearance order.""" + ds = set() + for m in mmas: + ds.update(m["D"]) + seen, out = set(), [] + for m in mmas: + for r in m["C"]: + if r in seen or r in ds or r == ZERO_C: + continue + seen.add(r) + out.append(r) + return out + + +def nums(xs): + return ", ".join(str(x) for x in xs) + + +def entries(p, mmas, after): + """The two dict entries of one phase: its output tiles, and its mma operands.""" + d, a, b, cs = dbase(mmas), abase(mmas), bbase(mmas), cseed(mmas) + parts = [f"swin_quads([{nums(a)}])", f"swin_pairs([{nums(b)}])"] + n = 4 * len(a) + 2 * len(b) + kinds = "A fragments, B fragment pairs" + if cs: + parts.append("[" + ", ".join(f'"{r}"' for r in cs) + "]") + n += len(cs) + kinds += ", C seeds" + pad = -n % 4 # swin_debug_block stores four registers per v4, so pad with the zero + if pad: + parts.append("[" + ", ".join([f'"{ZERO_C}"'] * pad) + "]") + n += pad + return [f" # phase {p}: {len(mmas)} mma, {len(d)} output tiles, " + f"splice after file line {after}", + f' "p{p}": ({after}, swin_pairs([{nums(d)}])),', + f' "p{p}o": ({after}, {" + ".join(parts)}),' + f" # {kinds}; {n} registers"] + + +def main(): + path, entry_name = R.resolve("enc0", None, None) + lines = open(path).read().split("\n") + first, last = next((a, b) for (nm, a, b) in R.find_entries(lines) if nm == entry_name) + stmts, _ = R.linearise(lines, first, last) + body = [] + for p in sorted(PHASES): + mmas = phase_mmas(stmts, p) + after = max(m["line"] for m in mmas) + 3 + assert lines[after - 1].rstrip().endswith(";"), lines[after - 1] + body.extend(entries(p, mmas, after)) + with open(OUT, "w") as f: + f.write(HEADER + "\n".join(body) + "\n }\n") + + +if __name__ == "__main__": + main() \ No newline at end of file