release: prepare 0.1.5 with RDNA2 kernels and in-game DLSS/FSR switching
- Add native preset K kernels for gfx1030–gfx1036 using software matrix products, with fast and accuracy builds and RDNA2 motion kernels. - Follow OptiScaler's DLSS and RR preset overrides, sanitize unsupported values and select the preset matching the feature's quality mode. - Enable FSR 4 under NVIDIA GPU spoofing by exposing real AMD PCI IDs to OptiScaler and FidelityFX modules; bundle AMD's loader and upscaler. - Keep K on native kernels in engine auto mode unless HIP is selected, and fall back to CUDA for M/L when shader_float8 is unavailable. - Add native-engine K GPU timings, preset recreation harness controls and regression coverage; fix the input-wait test's glibc name clash. - Update configuration, installer guidance and release documentation, simplify the README and move gameplay videos to docs/videos.md. RDNA2 kernels remain untested on RDNA2 hardware; software matrix arithmetic was validated against WMMA on RDNA3.
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@@ -10,6 +10,8 @@
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# D4R_NATIVE_FP8 1 (RDNA4 only): the variant for ZLUDA's native FP8 WMMA (d4r.ini [Kernels] NativeFp8):
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# M's layers on FP8 WMMA with NVIDIA's e4m3 activations, texture tails matching ZLUDA's
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# D4R_ZLUDA_WMMA_FP8_NATIVE lowering. K is the same in both variants.
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# D4R_WMMA_SOFT 1: RDNA2's software matrix products (kernels/common/wmma_layout.h) on an RDNA3 target, to
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# validate and time the RDNA2 kernels on RDNA3 hardware (gfx103x targets always use them)
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# D4R_PREFER_ACCURACY 1: preserve FP8 quantization, per-MMA f16 rounding and denormal handling;
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# build a separate set (default output: kernels/out/native/accuracy).
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# Texture kernels (tex) are NVIDIA's PTX with parts replaced, so they additionally need:
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@@ -35,7 +37,9 @@ FP8="${D4R_NATIVE_FP8:-0}"
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case "$ARCH" in
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gfx11[0-9][0-9]) [[ "$FP8" == 1 ]] && { echo "D4R_NATIVE_FP8 needs an RDNA4 (gfx12) target" >&2; exit 2; } ;;
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gfx12[0-9][0-9]) ;;
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*) echo "unsupported D4R_GPU_ARCH $ARCH (RDNA3 gfx110x or RDNA4 gfx120x)" >&2; exit 2 ;;
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# RDNA2: no WMMA; kernels/common/wmma_layout.h multiplies in software (D4R_WMMA_SOFT)
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gfx103[0-9]) [[ "$FP8" == 1 ]] && { echo "D4R_NATIVE_FP8 needs an RDNA4 (gfx12) target" >&2; exit 2; } ;;
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*) echo "unsupported D4R_GPU_ARCH $ARCH (RDNA2 gfx103x, RDNA3 gfx110x or RDNA4 gfx120x)" >&2; exit 2 ;;
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esac
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CLANG="$ROCM/lib/llvm/bin/clang++"
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[[ -x "$CLANG" ]] || { echo "clang++ not found in $ROCM/lib/llvm/bin (set D4R_ROCM_DIR)" >&2; exit 2; }
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@@ -65,6 +69,7 @@ build_hip() {
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fi
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done
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[[ "$ACCURACY" == 1 ]] && extra+=" -DD4R_ACCURACY"
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[[ "${D4R_WMMA_SOFT:-0}" == 1 ]] && extra+=" -DD4R_WMMA_SOFT"
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# shellcheck disable=SC2086
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(cd "$tmp" && "$CLANG" -x hip --offload-arch="$ARCH" --offload-device-only -O3 $flags $extra -I"$ROCM/include" \
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--rocm-path="$ROCM" --rocm-device-lib-path="$ROCM/amdgcn/bitcode" -I"$(dirname "$src")" \
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@@ -32,6 +32,17 @@
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#if D4R_WMMA_LAYOUT == 11 && defined(__GFX12__)
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#error "the gfx11 WMMA layout does not exist on gfx12"
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#endif
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// RDNA2 (gfx10.3): no WMMA instruction; the gfx11 layout with the products done in software (wm_mma below).
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// The gfx11 true16 assembly (v_cvt_f16_f32 %0.l/.h) does not exist there either; the C conversions replace it.
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#if defined(__GFX10__) && !defined(D4R_WMMA_SOFT)
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#define D4R_WMMA_SOFT 1
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#endif
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#ifdef __GFX10__
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#undef WM_CVT_ASM
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#endif
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#if defined(__GFX10__) && D4R_WMMA_LAYOUT != 11
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#error "RDNA2 kernels use the gfx11 WMMA layout"
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#endif
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#define WM_FN __attribute__((device, always_inline)) static inline
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@@ -324,10 +335,12 @@ WM_FN wm_f8v wm_mma(const wm_op& a, const wm_op& b, wm_f8v c)
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return __builtin_amdgcn_wmma_f32_16x16x16_f16_w32_gfx12(__builtin_bit_cast(wm_h8, a), __builtin_bit_cast(wm_h8, b), c);
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}
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#else
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#ifndef __GFX10__
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WM_FN wm_f8v wm_mma11(const wm_u8v& a, const wm_u8v& b, wm_f8v c)
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{
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return __builtin_amdgcn_wmma_f32_16x16x16_f16_w32(__builtin_bit_cast(wm_h16, a), __builtin_bit_cast(wm_h16, b), c);
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}
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#endif
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#if D4R_WMMA_LAYOUT == 12
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// layout shim: gfx12 operand halves -> one gfx11 operand in K order (half 0's 8 K, then half 1's)
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WM_FN wm_u8v wm_shim_operand(const wm_u4v& v)
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@@ -404,6 +417,49 @@ WM_FN wm_f8v wm_mma_zluda(const wm_op& a, const wm_op& b, wm_f8v c)
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{
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return wm_shim_acc_to12(wm_mma11(wm_shim_operand_zluda(a), wm_shim_operand_zluda(b), wm_shim_acc_to11(c)));
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}
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#elif defined(D4R_WMMA_SOFT)
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// RDNA2 (gfx103x) has no WMMA: the same gfx11 register layout, multiplied with v_dot2_f32_f16. Lane (r, h) holds
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// column r of B and needs rows 2i + h of A, which lanes 2i + h (any half) hold. Half 1's A is rotated by one row
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// first (row_ror:15 on DPP row 1 only), so that one row_share:2i broadcast gives half 0 row 2i and half 1 row
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// 2i + 1. 8 + 64 DPP moves and 64 dot2 per 16x16x16 product, f32 accumulation in K order (two products per step).
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// D4R_WMMA_SOFT on gfx11 runs this path on RDNA3 hardware for validation: there it is bit-identical to the WMMA
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// instruction (random 64-step chains with denormals, and K's whole network over a moving 24-frame sequence).
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WM_FN uint32_t wm_dpp_rot_half1(uint32_t v)
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{
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// DPP control 0x12f = row_ror:15 (lane j of a 16-lane row reads lane (j + 1) & 15); row mask 2 = half 1 only
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return (uint32_t)__builtin_amdgcn_update_dpp((int)v, (int)v, 0x12f, 0x2, 0xf, false);
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}
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// One dot2 per A row with the row_share broadcast folded into the instruction (VOP2 DPP: v_dot2c_f32_f16 on gfx10,
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// v_dot2acc_f32_f16 on gfx11). LLVM's DPP combiner does not fold a v_mov_b32_dpp into these, and a separate move
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// per row doubled the instruction count and kept 64 broadcast values live (spills). gfx10 and gfx11 resolve the
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// VALU -> DPP read dependency in hardware, so no wait states are needed around the assembly.
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#ifdef __GFX10__
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#define WM_DOT2_DPP "v_dot2c_f32_f16_dpp"
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#else
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#define WM_DOT2_DPP "v_dot2acc_f32_f16_dpp"
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#endif
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#define WM_SOFT_ROW(I, LANE) \
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asm(WM_DOT2_DPP " %0, %1, %2 row_share:" #LANE " row_mask:0xf bank_mask:0xf" : "+v"(c[I]) : "v"(x), "v"(column))
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WM_FN wm_f8v wm_mma(const wm_op& a, const wm_op& b, wm_f8v c)
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{
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// Each accumulator sums its K pairs in order 0..7, as the WMMA instruction does on gfx11 (bit-identical there).
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#pragma unroll
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for (int d = 0; d < 8; ++d)
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{
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const uint32_t x = wm_dpp_rot_half1(a[d]);
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const uint32_t column = b[d];
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WM_SOFT_ROW(0, 0);
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WM_SOFT_ROW(1, 2);
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WM_SOFT_ROW(2, 4);
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WM_SOFT_ROW(3, 6);
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WM_SOFT_ROW(4, 8);
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WM_SOFT_ROW(5, 10);
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WM_SOFT_ROW(6, 12);
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WM_SOFT_ROW(7, 14);
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}
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return c;
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}
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#undef WM_SOFT_ROW
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#else
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WM_FN wm_f8v wm_mma(const wm_op& a, const wm_op& b, wm_f8v c)
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{
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@@ -56,6 +56,11 @@ __device__ __forceinline__ uint32_t lane_id()
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return __builtin_amdgcn_mbcnt_lo(~0u, 0u);
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}
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// RDNA2: the f16-accumulator WMMA variants need the instruction; the f32 path (software products) serves them
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#ifdef __GFX10__
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#undef PWIN_NATIVE_F16ACC
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#undef PWIN_F16ACC_NATIVE
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#endif
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typedef wm_op op_t; // WMMA operand: u8v (gfx11) or u4v (gfx12)
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// one k16 step with the f16 accumulator of NVIDIA's f16 wmma (rounded after the step)
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